GDB (xrefs)
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#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "symtab.h"
#include "value.h"
#include "gdbcmd.h"
#include "language.h"
#include "gdbcore.h"
#include "symfile.h"
#include "objfiles.h"
#include "gdbtypes.h"
#include "target.h"
#include "arch-utils.h"
#include "regcache.h"
#include "osabi.h"
#include "riscv-tdep.h"
#include "reggroups.h"
#include "opcode/riscv.h"
#include "elf/riscv.h"
#include "elf-bfd.h"
#include "symcat.h"
#include "dis-asm.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "infcall.h"
#include "floatformat.h"
#include "remote.h"
#include "target-descriptions.h"
#include "dwarf2/frame.h"
#include "user-regs.h"
#include "valprint.h"
#include "gdbsupport/common-defs.h"
#include "opcode/riscv-opc.h"
#include "cli/cli-decode.h"
#include "observable.h"
#include "prologue-value.h"
#include "arch/riscv.h"
#include "riscv-ravenscar-thread.h"
#include "gdbsupport/gdb-safe-ctype.h"
Go to the source code of this file.
Classes | |
struct | riscv_unwind_cache |
class | riscv_pending_register_alias |
struct | riscv_register_feature |
struct | riscv_register_feature::register_info |
struct | riscv_xreg_feature |
struct | riscv_freg_feature |
struct | riscv_virtual_feature |
struct | riscv_csr_feature |
struct | riscv_vector_feature |
class | riscv_insn |
union | riscv_insn::riscv_insn_immediate |
struct | riscv_arg_info |
struct | riscv_arg_info::location |
struct | riscv_arg_reg |
struct | riscv_memory_offsets |
struct | riscv_call_info |
class | riscv_struct_info |
Macros | |
#define | SP_ALIGNMENT 16 |
#define | BIGGEST_ALIGNMENT 16 |
#define | DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) |
#define | riscv_breakpoints_debug_printf(fmt, ...) |
#define | riscv_infcall_debug_printf(fmt, ...) |
#define | RISCV_INFCALL_SCOPED_DEBUG_START_END(fmt, ...) |
#define | riscv_unwinder_debug_printf(fmt, ...) |
#define | riscv_gdbarch_debug_printf(fmt, ...) |
#define | DECLARE_CSR(NAME, VALUE, CLASS, DEFINE_VER, ABORT_VER) |
#define | RISCV_ENCODING_H |
#define | MATCH_SLLI_RV32 0x1013 |
#define | MASK_SLLI_RV32 0xfe00707f |
#define | MATCH_SRLI_RV32 0x5013 |
#define | MASK_SRLI_RV32 0xfe00707f |
#define | MATCH_SRAI_RV32 0x40005013 |
#define | MASK_SRAI_RV32 0xfe00707f |
#define | MATCH_FRFLAGS 0x102073 |
#define | MASK_FRFLAGS 0xfffff07f |
#define | MATCH_FSFLAGS 0x101073 |
#define | MASK_FSFLAGS 0xfff0707f |
#define | MATCH_FSFLAGSI 0x105073 |
#define | MASK_FSFLAGSI 0xfff0707f |
#define | MATCH_FRRM 0x202073 |
#define | MASK_FRRM 0xfffff07f |
#define | MATCH_FSRM 0x201073 |
#define | MASK_FSRM 0xfff0707f |
#define | MATCH_FSRMI 0x205073 |
#define | MASK_FSRMI 0xfff0707f |
#define | MATCH_FSCSR 0x301073 |
#define | MASK_FSCSR 0xfff0707f |
#define | MATCH_FRCSR 0x302073 |
#define | MASK_FRCSR 0xfffff07f |
#define | MATCH_RDCYCLE 0xc0002073 |
#define | MASK_RDCYCLE 0xfffff07f |
#define | MATCH_RDTIME 0xc0102073 |
#define | MASK_RDTIME 0xfffff07f |
#define | MATCH_RDINSTRET 0xc0202073 |
#define | MASK_RDINSTRET 0xfffff07f |
#define | MATCH_RDCYCLEH 0xc8002073 |
#define | MASK_RDCYCLEH 0xfffff07f |
#define | MATCH_RDTIMEH 0xc8102073 |
#define | MASK_RDTIMEH 0xfffff07f |
#define | MATCH_RDINSTRETH 0xc8202073 |
#define | MASK_RDINSTRETH 0xfffff07f |
#define | MATCH_SCALL 0x73 |
#define | MASK_SCALL 0xffffffff |
#define | MATCH_SBREAK 0x100073 |
#define | MASK_SBREAK 0xffffffff |
#define | MATCH_BEQ 0x63 |
#define | MASK_BEQ 0x707f |
#define | MATCH_BNE 0x1063 |
#define | MASK_BNE 0x707f |
#define | MATCH_BLT 0x4063 |
#define | MASK_BLT 0x707f |
#define | MATCH_BGE 0x5063 |
#define | MASK_BGE 0x707f |
#define | MATCH_BLTU 0x6063 |
#define | MASK_BLTU 0x707f |
#define | MATCH_BGEU 0x7063 |
#define | MASK_BGEU 0x707f |
#define | MATCH_JALR 0x67 |
#define | MASK_JALR 0x707f |
#define | MATCH_JAL 0x6f |
#define | MASK_JAL 0x7f |
#define | MATCH_LUI 0x37 |
#define | MASK_LUI 0x7f |
#define | MATCH_AUIPC 0x17 |
#define | MASK_AUIPC 0x7f |
#define | MATCH_ADDI 0x13 |
#define | MASK_ADDI 0x707f |
#define | MATCH_SLLI 0x1013 |
#define | MASK_SLLI 0xfc00707f |
#define | MATCH_SLTI 0x2013 |
#define | MASK_SLTI 0x707f |
#define | MATCH_SLTIU 0x3013 |
#define | MASK_SLTIU 0x707f |
#define | MATCH_XORI 0x4013 |
#define | MASK_XORI 0x707f |
#define | MATCH_SRLI 0x5013 |
#define | MASK_SRLI 0xfc00707f |
#define | MATCH_SRAI 0x40005013 |
#define | MASK_SRAI 0xfc00707f |
#define | MATCH_ORI 0x6013 |
#define | MASK_ORI 0x707f |
#define | MATCH_ANDI 0x7013 |
#define | MASK_ANDI 0x707f |
#define | MATCH_ADD 0x33 |
#define | MASK_ADD 0xfe00707f |
#define | MATCH_SUB 0x40000033 |
#define | MASK_SUB 0xfe00707f |
#define | MATCH_SLL 0x1033 |
#define | MASK_SLL 0xfe00707f |
#define | MATCH_SLT 0x2033 |
#define | MASK_SLT 0xfe00707f |
#define | MATCH_SLTU 0x3033 |
#define | MASK_SLTU 0xfe00707f |
#define | MATCH_XOR 0x4033 |
#define | MASK_XOR 0xfe00707f |
#define | MATCH_SRL 0x5033 |
#define | MASK_SRL 0xfe00707f |
#define | MATCH_SRA 0x40005033 |
#define | MASK_SRA 0xfe00707f |
#define | MATCH_OR 0x6033 |
#define | MASK_OR 0xfe00707f |
#define | MATCH_AND 0x7033 |
#define | MASK_AND 0xfe00707f |
#define | MATCH_ADDIW 0x1b |
#define | MASK_ADDIW 0x707f |
#define | MATCH_SLLIW 0x101b |
#define | MASK_SLLIW 0xfe00707f |
#define | MATCH_SRLIW 0x501b |
#define | MASK_SRLIW 0xfe00707f |
#define | MATCH_SRAIW 0x4000501b |
#define | MASK_SRAIW 0xfe00707f |
#define | MATCH_ADDW 0x3b |
#define | MASK_ADDW 0xfe00707f |
#define | MATCH_SUBW 0x4000003b |
#define | MASK_SUBW 0xfe00707f |
#define | MATCH_SLLW 0x103b |
#define | MASK_SLLW 0xfe00707f |
#define | MATCH_SRLW 0x503b |
#define | MASK_SRLW 0xfe00707f |
#define | MATCH_SRAW 0x4000503b |
#define | MASK_SRAW 0xfe00707f |
#define | MATCH_LB 0x3 |
#define | MASK_LB 0x707f |
#define | MATCH_LH 0x1003 |
#define | MASK_LH 0x707f |
#define | MATCH_LW 0x2003 |
#define | MASK_LW 0x707f |
#define | MATCH_LD 0x3003 |
#define | MASK_LD 0x707f |
#define | MATCH_LBU 0x4003 |
#define | MASK_LBU 0x707f |
#define | MATCH_LHU 0x5003 |
#define | MASK_LHU 0x707f |
#define | MATCH_LWU 0x6003 |
#define | MASK_LWU 0x707f |
#define | MATCH_SB 0x23 |
#define | MASK_SB 0x707f |
#define | MATCH_SH 0x1023 |
#define | MASK_SH 0x707f |
#define | MATCH_SW 0x2023 |
#define | MASK_SW 0x707f |
#define | MATCH_SD 0x3023 |
#define | MASK_SD 0x707f |
#define | MATCH_PAUSE 0x0100000f |
#define | MASK_PAUSE 0xffffffff |
#define | MATCH_FENCE 0xf |
#define | MASK_FENCE 0x707f |
#define | MATCH_FENCE_I 0x100f |
#define | MASK_FENCE_I 0x707f |
#define | MATCH_FENCE_TSO 0x8330000f |
#define | MASK_FENCE_TSO 0xfff0707f |
#define | MATCH_MUL 0x2000033 |
#define | MASK_MUL 0xfe00707f |
#define | MATCH_MULH 0x2001033 |
#define | MASK_MULH 0xfe00707f |
#define | MATCH_MULHSU 0x2002033 |
#define | MASK_MULHSU 0xfe00707f |
#define | MATCH_MULHU 0x2003033 |
#define | MASK_MULHU 0xfe00707f |
#define | MATCH_DIV 0x2004033 |
#define | MASK_DIV 0xfe00707f |
#define | MATCH_DIVU 0x2005033 |
#define | MASK_DIVU 0xfe00707f |
#define | MATCH_REM 0x2006033 |
#define | MASK_REM 0xfe00707f |
#define | MATCH_REMU 0x2007033 |
#define | MASK_REMU 0xfe00707f |
#define | MATCH_MULW 0x200003b |
#define | MASK_MULW 0xfe00707f |
#define | MATCH_DIVW 0x200403b |
#define | MASK_DIVW 0xfe00707f |
#define | MATCH_DIVUW 0x200503b |
#define | MASK_DIVUW 0xfe00707f |
#define | MATCH_REMW 0x200603b |
#define | MASK_REMW 0xfe00707f |
#define | MATCH_REMUW 0x200703b |
#define | MASK_REMUW 0xfe00707f |
#define | MATCH_AMOADD_W 0x202f |
#define | MASK_AMOADD_W 0xf800707f |
#define | MATCH_AMOXOR_W 0x2000202f |
#define | MASK_AMOXOR_W 0xf800707f |
#define | MATCH_AMOOR_W 0x4000202f |
#define | MASK_AMOOR_W 0xf800707f |
#define | MATCH_AMOAND_W 0x6000202f |
#define | MASK_AMOAND_W 0xf800707f |
#define | MATCH_AMOMIN_W 0x8000202f |
#define | MASK_AMOMIN_W 0xf800707f |
#define | MATCH_AMOMAX_W 0xa000202f |
#define | MASK_AMOMAX_W 0xf800707f |
#define | MATCH_AMOMINU_W 0xc000202f |
#define | MASK_AMOMINU_W 0xf800707f |
#define | MATCH_AMOMAXU_W 0xe000202f |
#define | MASK_AMOMAXU_W 0xf800707f |
#define | MATCH_AMOSWAP_W 0x800202f |
#define | MASK_AMOSWAP_W 0xf800707f |
#define | MATCH_LR_W 0x1000202f |
#define | MASK_LR_W 0xf9f0707f |
#define | MATCH_SC_W 0x1800202f |
#define | MASK_SC_W 0xf800707f |
#define | MATCH_AMOADD_D 0x302f |
#define | MASK_AMOADD_D 0xf800707f |
#define | MATCH_AMOXOR_D 0x2000302f |
#define | MASK_AMOXOR_D 0xf800707f |
#define | MATCH_AMOOR_D 0x4000302f |
#define | MASK_AMOOR_D 0xf800707f |
#define | MATCH_AMOAND_D 0x6000302f |
#define | MASK_AMOAND_D 0xf800707f |
#define | MATCH_AMOMIN_D 0x8000302f |
#define | MASK_AMOMIN_D 0xf800707f |
#define | MATCH_AMOMAX_D 0xa000302f |
#define | MASK_AMOMAX_D 0xf800707f |
#define | MATCH_AMOMINU_D 0xc000302f |
#define | MASK_AMOMINU_D 0xf800707f |
#define | MATCH_AMOMAXU_D 0xe000302f |
#define | MASK_AMOMAXU_D 0xf800707f |
#define | MATCH_AMOSWAP_D 0x800302f |
#define | MASK_AMOSWAP_D 0xf800707f |
#define | MATCH_LR_D 0x1000302f |
#define | MASK_LR_D 0xf9f0707f |
#define | MATCH_SC_D 0x1800302f |
#define | MASK_SC_D 0xf800707f |
#define | MATCH_ECALL 0x73 |
#define | MASK_ECALL 0xffffffff |
#define | MATCH_EBREAK 0x100073 |
#define | MASK_EBREAK 0xffffffff |
#define | MATCH_URET 0x200073 |
#define | MASK_URET 0xffffffff |
#define | MATCH_SRET 0x10200073 |
#define | MASK_SRET 0xffffffff |
#define | MATCH_HRET 0x20200073 |
#define | MASK_HRET 0xffffffff |
#define | MATCH_MRET 0x30200073 |
#define | MASK_MRET 0xffffffff |
#define | MATCH_DRET 0x7b200073 |
#define | MASK_DRET 0xffffffff |
#define | MATCH_SFENCE_VM 0x10400073 |
#define | MASK_SFENCE_VM 0xfff07fff |
#define | MATCH_SFENCE_VMA 0x12000073 |
#define | MASK_SFENCE_VMA 0xfe007fff |
#define | MATCH_WFI 0x10500073 |
#define | MASK_WFI 0xffffffff |
#define | MATCH_CSRRW 0x1073 |
#define | MASK_CSRRW 0x707f |
#define | MATCH_CSRRS 0x2073 |
#define | MASK_CSRRS 0x707f |
#define | MATCH_CSRRC 0x3073 |
#define | MASK_CSRRC 0x707f |
#define | MATCH_CSRRWI 0x5073 |
#define | MASK_CSRRWI 0x707f |
#define | MATCH_CSRRSI 0x6073 |
#define | MASK_CSRRSI 0x707f |
#define | MATCH_CSRRCI 0x7073 |
#define | MASK_CSRRCI 0x707f |
#define | MATCH_FADD_S 0x53 |
#define | MASK_FADD_S 0xfe00007f |
#define | MATCH_FSUB_S 0x8000053 |
#define | MASK_FSUB_S 0xfe00007f |
#define | MATCH_FMUL_S 0x10000053 |
#define | MASK_FMUL_S 0xfe00007f |
#define | MATCH_FDIV_S 0x18000053 |
#define | MASK_FDIV_S 0xfe00007f |
#define | MATCH_FSGNJ_S 0x20000053 |
#define | MASK_FSGNJ_S 0xfe00707f |
#define | MATCH_FSGNJN_S 0x20001053 |
#define | MASK_FSGNJN_S 0xfe00707f |
#define | MATCH_FSGNJX_S 0x20002053 |
#define | MASK_FSGNJX_S 0xfe00707f |
#define | MATCH_FMIN_S 0x28000053 |
#define | MASK_FMIN_S 0xfe00707f |
#define | MATCH_FMAX_S 0x28001053 |
#define | MASK_FMAX_S 0xfe00707f |
#define | MATCH_FSQRT_S 0x58000053 |
#define | MASK_FSQRT_S 0xfff0007f |
#define | MATCH_FADD_D 0x2000053 |
#define | MASK_FADD_D 0xfe00007f |
#define | MATCH_FSUB_D 0xa000053 |
#define | MASK_FSUB_D 0xfe00007f |
#define | MATCH_FMUL_D 0x12000053 |
#define | MASK_FMUL_D 0xfe00007f |
#define | MATCH_FDIV_D 0x1a000053 |
#define | MASK_FDIV_D 0xfe00007f |
#define | MATCH_FSGNJ_D 0x22000053 |
#define | MASK_FSGNJ_D 0xfe00707f |
#define | MATCH_FSGNJN_D 0x22001053 |
#define | MASK_FSGNJN_D 0xfe00707f |
#define | MATCH_FSGNJX_D 0x22002053 |
#define | MASK_FSGNJX_D 0xfe00707f |
#define | MATCH_FMIN_D 0x2a000053 |
#define | MASK_FMIN_D 0xfe00707f |
#define | MATCH_FMAX_D 0x2a001053 |
#define | MASK_FMAX_D 0xfe00707f |
#define | MATCH_FCVT_S_D 0x40100053 |
#define | MASK_FCVT_S_D 0xfff0007f |
#define | MATCH_FCVT_D_S 0x42000053 |
#define | MASK_FCVT_D_S 0xfff0007f |
#define | MATCH_FSQRT_D 0x5a000053 |
#define | MASK_FSQRT_D 0xfff0007f |
#define | MATCH_FADD_Q 0x6000053 |
#define | MASK_FADD_Q 0xfe00007f |
#define | MATCH_FSUB_Q 0xe000053 |
#define | MASK_FSUB_Q 0xfe00007f |
#define | MATCH_FMUL_Q 0x16000053 |
#define | MASK_FMUL_Q 0xfe00007f |
#define | MATCH_FDIV_Q 0x1e000053 |
#define | MASK_FDIV_Q 0xfe00007f |
#define | MATCH_FSGNJ_Q 0x26000053 |
#define | MASK_FSGNJ_Q 0xfe00707f |
#define | MATCH_FSGNJN_Q 0x26001053 |
#define | MASK_FSGNJN_Q 0xfe00707f |
#define | MATCH_FSGNJX_Q 0x26002053 |
#define | MASK_FSGNJX_Q 0xfe00707f |
#define | MATCH_FMIN_Q 0x2e000053 |
#define | MASK_FMIN_Q 0xfe00707f |
#define | MATCH_FMAX_Q 0x2e001053 |
#define | MASK_FMAX_Q 0xfe00707f |
#define | MATCH_FCVT_S_Q 0x40300053 |
#define | MASK_FCVT_S_Q 0xfff0007f |
#define | MATCH_FCVT_Q_S 0x46000053 |
#define | MASK_FCVT_Q_S 0xfff0007f |
#define | MATCH_FCVT_D_Q 0x42300053 |
#define | MASK_FCVT_D_Q 0xfff0007f |
#define | MATCH_FCVT_Q_D 0x46100053 |
#define | MASK_FCVT_Q_D 0xfff0007f |
#define | MATCH_FSQRT_Q 0x5e000053 |
#define | MASK_FSQRT_Q 0xfff0007f |
#define | MATCH_FLE_S 0xa0000053 |
#define | MASK_FLE_S 0xfe00707f |
#define | MATCH_FLT_S 0xa0001053 |
#define | MASK_FLT_S 0xfe00707f |
#define | MATCH_FEQ_S 0xa0002053 |
#define | MASK_FEQ_S 0xfe00707f |
#define | MATCH_FLE_D 0xa2000053 |
#define | MASK_FLE_D 0xfe00707f |
#define | MATCH_FLT_D 0xa2001053 |
#define | MASK_FLT_D 0xfe00707f |
#define | MATCH_FEQ_D 0xa2002053 |
#define | MASK_FEQ_D 0xfe00707f |
#define | MATCH_FLE_Q 0xa6000053 |
#define | MASK_FLE_Q 0xfe00707f |
#define | MATCH_FLT_Q 0xa6001053 |
#define | MASK_FLT_Q 0xfe00707f |
#define | MATCH_FEQ_Q 0xa6002053 |
#define | MASK_FEQ_Q 0xfe00707f |
#define | MATCH_FCVT_W_S 0xc0000053 |
#define | MASK_FCVT_W_S 0xfff0007f |
#define | MATCH_FCVT_WU_S 0xc0100053 |
#define | MASK_FCVT_WU_S 0xfff0007f |
#define | MATCH_FCVT_L_S 0xc0200053 |
#define | MASK_FCVT_L_S 0xfff0007f |
#define | MATCH_FCVT_LU_S 0xc0300053 |
#define | MASK_FCVT_LU_S 0xfff0007f |
#define | MATCH_FMV_X_S 0xe0000053 |
#define | MASK_FMV_X_S 0xfff0707f |
#define | MATCH_FCLASS_S 0xe0001053 |
#define | MASK_FCLASS_S 0xfff0707f |
#define | MATCH_FCVT_W_D 0xc2000053 |
#define | MASK_FCVT_W_D 0xfff0007f |
#define | MATCH_FCVT_WU_D 0xc2100053 |
#define | MASK_FCVT_WU_D 0xfff0007f |
#define | MATCH_FCVT_L_D 0xc2200053 |
#define | MASK_FCVT_L_D 0xfff0007f |
#define | MATCH_FCVT_LU_D 0xc2300053 |
#define | MASK_FCVT_LU_D 0xfff0007f |
#define | MATCH_FMV_X_D 0xe2000053 |
#define | MASK_FMV_X_D 0xfff0707f |
#define | MATCH_FCLASS_D 0xe2001053 |
#define | MASK_FCLASS_D 0xfff0707f |
#define | MATCH_FCVT_W_Q 0xc6000053 |
#define | MASK_FCVT_W_Q 0xfff0007f |
#define | MATCH_FCVT_WU_Q 0xc6100053 |
#define | MASK_FCVT_WU_Q 0xfff0007f |
#define | MATCH_FCVT_L_Q 0xc6200053 |
#define | MASK_FCVT_L_Q 0xfff0007f |
#define | MATCH_FCVT_LU_Q 0xc6300053 |
#define | MASK_FCVT_LU_Q 0xfff0007f |
#define | MATCH_FCLASS_Q 0xe6001053 |
#define | MASK_FCLASS_Q 0xfff0707f |
#define | MATCH_FCVT_S_W 0xd0000053 |
#define | MASK_FCVT_S_W 0xfff0007f |
#define | MATCH_FCVT_S_WU 0xd0100053 |
#define | MASK_FCVT_S_WU 0xfff0007f |
#define | MATCH_FCVT_S_L 0xd0200053 |
#define | MASK_FCVT_S_L 0xfff0007f |
#define | MATCH_FCVT_S_LU 0xd0300053 |
#define | MASK_FCVT_S_LU 0xfff0007f |
#define | MATCH_FMV_S_X 0xf0000053 |
#define | MASK_FMV_S_X 0xfff0707f |
#define | MATCH_FCVT_D_W 0xd2000053 |
#define | MASK_FCVT_D_W 0xfff0007f |
#define | MATCH_FCVT_D_WU 0xd2100053 |
#define | MASK_FCVT_D_WU 0xfff0007f |
#define | MATCH_FCVT_D_L 0xd2200053 |
#define | MASK_FCVT_D_L 0xfff0007f |
#define | MATCH_FCVT_D_LU 0xd2300053 |
#define | MASK_FCVT_D_LU 0xfff0007f |
#define | MATCH_FMV_D_X 0xf2000053 |
#define | MASK_FMV_D_X 0xfff0707f |
#define | MATCH_FCVT_Q_W 0xd6000053 |
#define | MASK_FCVT_Q_W 0xfff0007f |
#define | MATCH_FCVT_Q_WU 0xd6100053 |
#define | MASK_FCVT_Q_WU 0xfff0007f |
#define | MATCH_FCVT_Q_L 0xd6200053 |
#define | MASK_FCVT_Q_L 0xfff0007f |
#define | MATCH_FCVT_Q_LU 0xd6300053 |
#define | MASK_FCVT_Q_LU 0xfff0007f |
#define | MATCH_FLI_H 0xf4100053 |
#define | MASK_FLI_H 0xfff0707f |
#define | MATCH_FMINM_H 0x2c002053 |
#define | MASK_FMINM_H 0xfe00707f |
#define | MATCH_FMAXM_H 0x2c003053 |
#define | MASK_FMAXM_H 0xfe00707f |
#define | MATCH_FROUND_H 0x44400053 |
#define | MASK_FROUND_H 0xfff0007f |
#define | MATCH_FROUNDNX_H 0x44500053 |
#define | MASK_FROUNDNX_H 0xfff0007f |
#define | MATCH_FLTQ_H 0xa4005053 |
#define | MASK_FLTQ_H 0xfe00707f |
#define | MATCH_FLEQ_H 0xa4004053 |
#define | MASK_FLEQ_H 0xfe00707f |
#define | MATCH_FLI_S 0xf0100053 |
#define | MASK_FLI_S 0xfff0707f |
#define | MATCH_FMINM_S 0x28002053 |
#define | MASK_FMINM_S 0xfe00707f |
#define | MATCH_FMAXM_S 0x28003053 |
#define | MASK_FMAXM_S 0xfe00707f |
#define | MATCH_FROUND_S 0x40400053 |
#define | MASK_FROUND_S 0xfff0007f |
#define | MATCH_FROUNDNX_S 0x40500053 |
#define | MASK_FROUNDNX_S 0xfff0007f |
#define | MATCH_FLTQ_S 0xa0005053 |
#define | MASK_FLTQ_S 0xfe00707f |
#define | MATCH_FLEQ_S 0xa0004053 |
#define | MASK_FLEQ_S 0xfe00707f |
#define | MATCH_FLI_D 0xf2100053 |
#define | MASK_FLI_D 0xfff0707f |
#define | MATCH_FMINM_D 0x2a002053 |
#define | MASK_FMINM_D 0xfe00707f |
#define | MATCH_FMAXM_D 0x2a003053 |
#define | MASK_FMAXM_D 0xfe00707f |
#define | MATCH_FROUND_D 0x42400053 |
#define | MASK_FROUND_D 0xfff0007f |
#define | MATCH_FROUNDNX_D 0x42500053 |
#define | MASK_FROUNDNX_D 0xfff0007f |
#define | MATCH_FLTQ_D 0xa2005053 |
#define | MASK_FLTQ_D 0xfe00707f |
#define | MATCH_FLEQ_D 0xa2004053 |
#define | MASK_FLEQ_D 0xfe00707f |
#define | MATCH_FLI_Q 0xf6100053 |
#define | MASK_FLI_Q 0xfff0707f |
#define | MATCH_FMINM_Q 0x2e002053 |
#define | MASK_FMINM_Q 0xfe00707f |
#define | MATCH_FMAXM_Q 0x2e003053 |
#define | MASK_FMAXM_Q 0xfe00707f |
#define | MATCH_FROUND_Q 0x46400053 |
#define | MASK_FROUND_Q 0xfff0007f |
#define | MATCH_FROUNDNX_Q 0x46500053 |
#define | MASK_FROUNDNX_Q 0xfff0007f |
#define | MATCH_FLTQ_Q 0xa6005053 |
#define | MASK_FLTQ_Q 0xfe00707f |
#define | MATCH_FLEQ_Q 0xa6004053 |
#define | MASK_FLEQ_Q 0xfe00707f |
#define | MATCH_FCVTMOD_W_D 0xc2801053 |
#define | MASK_FCVTMOD_W_D 0xfff0707f |
#define | MATCH_FMVH_X_D 0xe2100053 |
#define | MASK_FMVH_X_D 0xfff0707f |
#define | MATCH_FMVH_X_Q 0xe6100053 |
#define | MASK_FMVH_X_Q 0xfff0707f |
#define | MATCH_FMVP_D_X 0xb2000053 |
#define | MASK_FMVP_D_X 0xfe00707f |
#define | MATCH_FMVP_Q_X 0xb6000053 |
#define | MASK_FMVP_Q_X 0xfe00707f |
#define | MATCH_CLZ 0x60001013 |
#define | MASK_CLZ 0xfff0707f |
#define | MATCH_CTZ 0x60101013 |
#define | MASK_CTZ 0xfff0707f |
#define | MATCH_CPOP 0x60201013 |
#define | MASK_CPOP 0xfff0707f |
#define | MATCH_MIN 0xa004033 |
#define | MASK_MIN 0xfe00707f |
#define | MATCH_MINU 0xa005033 |
#define | MASK_MINU 0xfe00707f |
#define | MATCH_MAX 0xa006033 |
#define | MASK_MAX 0xfe00707f |
#define | MATCH_MAXU 0xa007033 |
#define | MASK_MAXU 0xfe00707f |
#define | MATCH_SEXT_B 0x60401013 |
#define | MASK_SEXT_B 0xfff0707f |
#define | MATCH_SEXT_H 0x60501013 |
#define | MASK_SEXT_H 0xfff0707f |
#define | MATCH_PACK 0x8004033 |
#define | MASK_PACK 0xfe00707f |
#define | MATCH_PACKH 0x8007033 |
#define | MASK_PACKH 0xfe00707f |
#define | MATCH_PACKW 0x800403b |
#define | MASK_PACKW 0xfe00707f |
#define | MATCH_ANDN 0x40007033 |
#define | MASK_ANDN 0xfe00707f |
#define | MATCH_ORN 0x40006033 |
#define | MASK_ORN 0xfe00707f |
#define | MATCH_XNOR 0x40004033 |
#define | MASK_XNOR 0xfe00707f |
#define | MATCH_ROL 0x60001033 |
#define | MASK_ROL 0xfe00707f |
#define | MATCH_ROR 0x60005033 |
#define | MASK_ROR 0xfe00707f |
#define | MATCH_RORI 0x60005013 |
#define | MASK_RORI 0xfc00707f |
#define | MATCH_GREVI 0x68005013 |
#define | MASK_GREVI 0xfc00707f |
#define | MATCH_GORCI 0x28005013 |
#define | MASK_GORCI 0xfc00707f |
#define | MATCH_SHFLI 0x8001013 |
#define | MASK_SHFLI 0xfe00707f |
#define | MATCH_UNSHFLI 0x8005013 |
#define | MASK_UNSHFLI 0xfe00707f |
#define | MATCH_CLZW 0x6000101b |
#define | MASK_CLZW 0xfff0707f |
#define | MATCH_CTZW 0x6010101b |
#define | MASK_CTZW 0xfff0707f |
#define | MATCH_CPOPW 0x6020101b |
#define | MASK_CPOPW 0xfff0707f |
#define | MATCH_ROLW 0x6000103b |
#define | MASK_ROLW 0xfe00707f |
#define | MATCH_RORW 0x6000503b |
#define | MASK_RORW 0xfe00707f |
#define | MATCH_RORIW 0x6000501b |
#define | MASK_RORIW 0xfe00707f |
#define | MATCH_SH1ADD 0x20002033 |
#define | MASK_SH1ADD 0xfe00707f |
#define | MATCH_SH2ADD 0x20004033 |
#define | MASK_SH2ADD 0xfe00707f |
#define | MATCH_SH3ADD 0x20006033 |
#define | MASK_SH3ADD 0xfe00707f |
#define | MATCH_SH1ADD_UW 0x2000203b |
#define | MASK_SH1ADD_UW 0xfe00707f |
#define | MATCH_SH2ADD_UW 0x2000403b |
#define | MASK_SH2ADD_UW 0xfe00707f |
#define | MATCH_SH3ADD_UW 0x2000603b |
#define | MASK_SH3ADD_UW 0xfe00707f |
#define | MATCH_ADD_UW 0x800003b |
#define | MASK_ADD_UW 0xfe00707f |
#define | MATCH_SLLI_UW 0x800101b |
#define | MASK_SLLI_UW 0xfc00707f |
#define | MATCH_CLMUL 0xa001033 |
#define | MASK_CLMUL 0xfe00707f |
#define | MATCH_CLMULH 0xa003033 |
#define | MASK_CLMULH 0xfe00707f |
#define | MATCH_CLMULR 0xa002033 |
#define | MASK_CLMULR 0xfe00707f |
#define | MATCH_XPERM4 0x28002033 |
#define | MASK_XPERM4 0xfe00707f |
#define | MATCH_XPERM8 0x28004033 |
#define | MASK_XPERM8 0xfe00707f |
#define | MATCH_BCLRI 0x48001013 |
#define | MASK_BCLRI 0xfc00707f |
#define | MATCH_BSETI 0x28001013 |
#define | MASK_BSETI 0xfc00707f |
#define | MATCH_BINVI 0x68001013 |
#define | MASK_BINVI 0xfc00707f |
#define | MATCH_BEXTI 0x48005013 |
#define | MASK_BEXTI 0xfc00707f |
#define | MATCH_BCLR 0x48001033 |
#define | MASK_BCLR 0xfe00707f |
#define | MATCH_BSET 0x28001033 |
#define | MASK_BSET 0xfe00707f |
#define | MATCH_BINV 0x68001033 |
#define | MASK_BINV 0xfe00707f |
#define | MATCH_BEXT 0x48005033 |
#define | MASK_BEXT 0xfe00707f |
#define | MATCH_FLW 0x2007 |
#define | MASK_FLW 0x707f |
#define | MATCH_FLD 0x3007 |
#define | MASK_FLD 0x707f |
#define | MATCH_FLQ 0x4007 |
#define | MASK_FLQ 0x707f |
#define | MATCH_FSW 0x2027 |
#define | MASK_FSW 0x707f |
#define | MATCH_FSD 0x3027 |
#define | MASK_FSD 0x707f |
#define | MATCH_FSQ 0x4027 |
#define | MASK_FSQ 0x707f |
#define | MATCH_FMADD_S 0x43 |
#define | MASK_FMADD_S 0x600007f |
#define | MATCH_FMSUB_S 0x47 |
#define | MASK_FMSUB_S 0x600007f |
#define | MATCH_FNMSUB_S 0x4b |
#define | MASK_FNMSUB_S 0x600007f |
#define | MATCH_FNMADD_S 0x4f |
#define | MASK_FNMADD_S 0x600007f |
#define | MATCH_FMADD_D 0x2000043 |
#define | MASK_FMADD_D 0x600007f |
#define | MATCH_FMSUB_D 0x2000047 |
#define | MASK_FMSUB_D 0x600007f |
#define | MATCH_FNMSUB_D 0x200004b |
#define | MASK_FNMSUB_D 0x600007f |
#define | MATCH_FNMADD_D 0x200004f |
#define | MASK_FNMADD_D 0x600007f |
#define | MATCH_FMADD_Q 0x6000043 |
#define | MASK_FMADD_Q 0x600007f |
#define | MATCH_FMSUB_Q 0x6000047 |
#define | MASK_FMSUB_Q 0x600007f |
#define | MATCH_FNMSUB_Q 0x600004b |
#define | MASK_FNMSUB_Q 0x600007f |
#define | MATCH_FNMADD_Q 0x600004f |
#define | MASK_FNMADD_Q 0x600007f |
#define | MATCH_C_ADDI4SPN 0x0 |
#define | MASK_C_ADDI4SPN 0xe003 |
#define | MATCH_C_FLD 0x2000 |
#define | MASK_C_FLD 0xe003 |
#define | MATCH_C_LW 0x4000 |
#define | MASK_C_LW 0xe003 |
#define | MATCH_C_FLW 0x6000 |
#define | MASK_C_FLW 0xe003 |
#define | MATCH_C_FSD 0xa000 |
#define | MASK_C_FSD 0xe003 |
#define | MATCH_C_SW 0xc000 |
#define | MASK_C_SW 0xe003 |
#define | MATCH_C_FSW 0xe000 |
#define | MASK_C_FSW 0xe003 |
#define | MATCH_C_ADDI 0x1 |
#define | MASK_C_ADDI 0xe003 |
#define | MATCH_C_JAL 0x2001 |
#define | MASK_C_JAL 0xe003 |
#define | MATCH_C_LI 0x4001 |
#define | MASK_C_LI 0xe003 |
#define | MATCH_C_LUI 0x6001 |
#define | MASK_C_LUI 0xe003 |
#define | MATCH_C_SRLI 0x8001 |
#define | MASK_C_SRLI 0xec03 |
#define | MATCH_C_SRLI64 0x8001 |
#define | MASK_C_SRLI64 0xfc7f |
#define | MATCH_C_SRAI 0x8401 |
#define | MASK_C_SRAI 0xec03 |
#define | MATCH_C_SRAI64 0x8401 |
#define | MASK_C_SRAI64 0xfc7f |
#define | MATCH_C_ANDI 0x8801 |
#define | MASK_C_ANDI 0xec03 |
#define | MATCH_C_SUB 0x8c01 |
#define | MASK_C_SUB 0xfc63 |
#define | MATCH_C_XOR 0x8c21 |
#define | MASK_C_XOR 0xfc63 |
#define | MATCH_C_OR 0x8c41 |
#define | MASK_C_OR 0xfc63 |
#define | MATCH_C_AND 0x8c61 |
#define | MASK_C_AND 0xfc63 |
#define | MATCH_C_SUBW 0x9c01 |
#define | MASK_C_SUBW 0xfc63 |
#define | MATCH_C_ADDW 0x9c21 |
#define | MASK_C_ADDW 0xfc63 |
#define | MATCH_C_J 0xa001 |
#define | MASK_C_J 0xe003 |
#define | MATCH_C_BEQZ 0xc001 |
#define | MASK_C_BEQZ 0xe003 |
#define | MATCH_C_BNEZ 0xe001 |
#define | MASK_C_BNEZ 0xe003 |
#define | MATCH_C_SLLI 0x2 |
#define | MASK_C_SLLI 0xe003 |
#define | MATCH_C_SLLI64 0x2 |
#define | MASK_C_SLLI64 0xf07f |
#define | MATCH_C_FLDSP 0x2002 |
#define | MASK_C_FLDSP 0xe003 |
#define | MATCH_C_LWSP 0x4002 |
#define | MASK_C_LWSP 0xe003 |
#define | MATCH_C_FLWSP 0x6002 |
#define | MASK_C_FLWSP 0xe003 |
#define | MATCH_C_MV 0x8002 |
#define | MASK_C_MV 0xf003 |
#define | MATCH_C_ADD 0x9002 |
#define | MASK_C_ADD 0xf003 |
#define | MATCH_C_FSDSP 0xa002 |
#define | MASK_C_FSDSP 0xe003 |
#define | MATCH_C_SWSP 0xc002 |
#define | MASK_C_SWSP 0xe003 |
#define | MATCH_C_FSWSP 0xe002 |
#define | MASK_C_FSWSP 0xe003 |
#define | MATCH_C_NOP 0x1 |
#define | MASK_C_NOP 0xffff |
#define | MATCH_C_ADDI16SP 0x6101 |
#define | MASK_C_ADDI16SP 0xef83 |
#define | MATCH_C_JR 0x8002 |
#define | MASK_C_JR 0xf07f |
#define | MATCH_C_JALR 0x9002 |
#define | MASK_C_JALR 0xf07f |
#define | MATCH_C_EBREAK 0x9002 |
#define | MASK_C_EBREAK 0xffff |
#define | MATCH_C_LD 0x6000 |
#define | MASK_C_LD 0xe003 |
#define | MATCH_C_SD 0xe000 |
#define | MASK_C_SD 0xe003 |
#define | MATCH_C_ADDIW 0x2001 |
#define | MASK_C_ADDIW 0xe003 |
#define | MATCH_C_LDSP 0x6002 |
#define | MASK_C_LDSP 0xe003 |
#define | MATCH_C_SDSP 0xe002 |
#define | MASK_C_SDSP 0xe003 |
#define | MATCH_SM3P0 0x10801013 |
#define | MASK_SM3P0 0xfff0707f |
#define | MATCH_SM3P1 0x10901013 |
#define | MASK_SM3P1 0xfff0707f |
#define | MATCH_SHA256SUM0 0x10001013 |
#define | MASK_SHA256SUM0 0xfff0707f |
#define | MATCH_SHA256SUM1 0x10101013 |
#define | MASK_SHA256SUM1 0xfff0707f |
#define | MATCH_SHA256SIG0 0x10201013 |
#define | MASK_SHA256SIG0 0xfff0707f |
#define | MATCH_SHA256SIG1 0x10301013 |
#define | MASK_SHA256SIG1 0xfff0707f |
#define | MATCH_SHA512SUM0R 0x50000033 |
#define | MASK_SHA512SUM0R 0xfe00707f |
#define | MATCH_SHA512SUM1R 0x52000033 |
#define | MASK_SHA512SUM1R 0xfe00707f |
#define | MATCH_SHA512SIG0L 0x54000033 |
#define | MASK_SHA512SIG0L 0xfe00707f |
#define | MATCH_SHA512SIG0H 0x5c000033 |
#define | MASK_SHA512SIG0H 0xfe00707f |
#define | MATCH_SHA512SIG1L 0x56000033 |
#define | MASK_SHA512SIG1L 0xfe00707f |
#define | MATCH_SHA512SIG1H 0x5e000033 |
#define | MASK_SHA512SIG1H 0xfe00707f |
#define | MATCH_SM4ED 0x30000033 |
#define | MASK_SM4ED 0x3e00707f |
#define | MATCH_SM4KS 0x34000033 |
#define | MASK_SM4KS 0x3e00707f |
#define | MATCH_AES32ESMI 0x26000033 |
#define | MASK_AES32ESMI 0x3e00707f |
#define | MATCH_AES32ESI 0x22000033 |
#define | MASK_AES32ESI 0x3e00707f |
#define | MATCH_AES32DSMI 0x2e000033 |
#define | MASK_AES32DSMI 0x3e00707f |
#define | MATCH_AES32DSI 0x2a000033 |
#define | MASK_AES32DSI 0x3e00707f |
#define | MATCH_SHA512SUM0 0x10401013 |
#define | MASK_SHA512SUM0 0xfff0707f |
#define | MATCH_SHA512SUM1 0x10501013 |
#define | MASK_SHA512SUM1 0xfff0707f |
#define | MATCH_SHA512SIG0 0x10601013 |
#define | MASK_SHA512SIG0 0xfff0707f |
#define | MATCH_SHA512SIG1 0x10701013 |
#define | MASK_SHA512SIG1 0xfff0707f |
#define | MATCH_AES64KS1I 0x31001013 |
#define | MASK_AES64KS1I 0xff00707f |
#define | MATCH_AES64IM 0x30001013 |
#define | MASK_AES64IM 0xfff0707f |
#define | MATCH_AES64KS2 0x7e000033 |
#define | MASK_AES64KS2 0xfe00707f |
#define | MATCH_AES64ESM 0x36000033 |
#define | MASK_AES64ESM 0xfe00707f |
#define | MATCH_AES64ES 0x32000033 |
#define | MASK_AES64ES 0xfe00707f |
#define | MATCH_AES64DSM 0x3e000033 |
#define | MASK_AES64DSM 0xfe00707f |
#define | MATCH_AES64DS 0x3a000033 |
#define | MASK_AES64DS 0xfe00707f |
#define | MATCH_FADD_H 0x4000053 |
#define | MASK_FADD_H 0xfe00007f |
#define | MATCH_FSUB_H 0xc000053 |
#define | MASK_FSUB_H 0xfe00007f |
#define | MATCH_FMUL_H 0x14000053 |
#define | MASK_FMUL_H 0xfe00007f |
#define | MATCH_FDIV_H 0x1c000053 |
#define | MASK_FDIV_H 0xfe00007f |
#define | MATCH_FSGNJ_H 0x24000053 |
#define | MASK_FSGNJ_H 0xfe00707f |
#define | MATCH_FSGNJN_H 0x24001053 |
#define | MASK_FSGNJN_H 0xfe00707f |
#define | MATCH_FSGNJX_H 0x24002053 |
#define | MASK_FSGNJX_H 0xfe00707f |
#define | MATCH_FMIN_H 0x2c000053 |
#define | MASK_FMIN_H 0xfe00707f |
#define | MATCH_FMAX_H 0x2c001053 |
#define | MASK_FMAX_H 0xfe00707f |
#define | MATCH_FCVT_H_S 0x44000053 |
#define | MASK_FCVT_H_S 0xfff0007f |
#define | MATCH_FCVT_S_H 0x40200053 |
#define | MASK_FCVT_S_H 0xfff0007f |
#define | MATCH_FSQRT_H 0x5c000053 |
#define | MASK_FSQRT_H 0xfff0007f |
#define | MATCH_FLE_H 0xa4000053 |
#define | MASK_FLE_H 0xfe00707f |
#define | MATCH_FLT_H 0xa4001053 |
#define | MASK_FLT_H 0xfe00707f |
#define | MATCH_FEQ_H 0xa4002053 |
#define | MASK_FEQ_H 0xfe00707f |
#define | MATCH_FCVT_W_H 0xc4000053 |
#define | MASK_FCVT_W_H 0xfff0007f |
#define | MATCH_FCVT_WU_H 0xc4100053 |
#define | MASK_FCVT_WU_H 0xfff0007f |
#define | MATCH_FMV_X_H 0xe4000053 |
#define | MASK_FMV_X_H 0xfff0707f |
#define | MATCH_FCLASS_H 0xe4001053 |
#define | MASK_FCLASS_H 0xfff0707f |
#define | MATCH_FCVT_H_W 0xd4000053 |
#define | MASK_FCVT_H_W 0xfff0007f |
#define | MATCH_FCVT_H_WU 0xd4100053 |
#define | MASK_FCVT_H_WU 0xfff0007f |
#define | MATCH_FMV_H_X 0xf4000053 |
#define | MASK_FMV_H_X 0xfff0707f |
#define | MATCH_FLH 0x1007 |
#define | MASK_FLH 0x707f |
#define | MATCH_FSH 0x1027 |
#define | MASK_FSH 0x707f |
#define | MATCH_FMADD_H 0x4000043 |
#define | MASK_FMADD_H 0x600007f |
#define | MATCH_FMSUB_H 0x4000047 |
#define | MASK_FMSUB_H 0x600007f |
#define | MATCH_FNMSUB_H 0x400004b |
#define | MASK_FNMSUB_H 0x600007f |
#define | MATCH_FNMADD_H 0x400004f |
#define | MASK_FNMADD_H 0x600007f |
#define | MATCH_FCVT_H_D 0x44100053 |
#define | MASK_FCVT_H_D 0xfff0007f |
#define | MATCH_FCVT_D_H 0x42200053 |
#define | MASK_FCVT_D_H 0xfff0007f |
#define | MATCH_FCVT_H_Q 0x44300053 |
#define | MASK_FCVT_H_Q 0xfff0007f |
#define | MATCH_FCVT_Q_H 0x46200053 |
#define | MASK_FCVT_Q_H 0xfff0007f |
#define | MATCH_FCVT_L_H 0xc4200053 |
#define | MASK_FCVT_L_H 0xfff0007f |
#define | MATCH_FCVT_LU_H 0xc4300053 |
#define | MASK_FCVT_LU_H 0xfff0007f |
#define | MATCH_FCVT_H_L 0xd4200053 |
#define | MASK_FCVT_H_L 0xfff0007f |
#define | MATCH_FCVT_H_LU 0xd4300053 |
#define | MASK_FCVT_H_LU 0xfff0007f |
#define | MATCH_VSETVL 0x80007057 |
#define | MASK_VSETVL 0xfe00707f |
#define | MATCH_VSETIVLI 0xc0007057 |
#define | MASK_VSETIVLI 0xc000707f |
#define | MATCH_VSETVLI 0x00007057 |
#define | MASK_VSETVLI 0x8000707f |
#define | MATCH_VLMV 0x02b00007 |
#define | MASK_VLMV 0xfff0707f |
#define | MATCH_VSMV 0x02b00027 |
#define | MASK_VSMV 0xfff0707f |
#define | MATCH_VLE8V 0x00000007 |
#define | MASK_VLE8V 0xfdf0707f |
#define | MATCH_VLE16V 0x00005007 |
#define | MASK_VLE16V 0xfdf0707f |
#define | MATCH_VLE32V 0x00006007 |
#define | MASK_VLE32V 0xfdf0707f |
#define | MATCH_VLE64V 0x00007007 |
#define | MASK_VLE64V 0xfdf0707f |
#define | MATCH_VSE8V 0x00000027 |
#define | MASK_VSE8V 0xfdf0707f |
#define | MATCH_VSE16V 0x00005027 |
#define | MASK_VSE16V 0xfdf0707f |
#define | MATCH_VSE32V 0x00006027 |
#define | MASK_VSE32V 0xfdf0707f |
#define | MATCH_VSE64V 0x00007027 |
#define | MASK_VSE64V 0xfdf0707f |
#define | MATCH_VLSE8V 0x08000007 |
#define | MASK_VLSE8V 0xfc00707f |
#define | MATCH_VLSE16V 0x08005007 |
#define | MASK_VLSE16V 0xfc00707f |
#define | MATCH_VLSE32V 0x08006007 |
#define | MASK_VLSE32V 0xfc00707f |
#define | MATCH_VLSE64V 0x08007007 |
#define | MASK_VLSE64V 0xfc00707f |
#define | MATCH_VSSE8V 0x08000027 |
#define | MASK_VSSE8V 0xfc00707f |
#define | MATCH_VSSE16V 0x08005027 |
#define | MASK_VSSE16V 0xfc00707f |
#define | MATCH_VSSE32V 0x08006027 |
#define | MASK_VSSE32V 0xfc00707f |
#define | MATCH_VSSE64V 0x08007027 |
#define | MASK_VSSE64V 0xfc00707f |
#define | MATCH_VLOXEI8V 0x0c000007 |
#define | MASK_VLOXEI8V 0xfc00707f |
#define | MATCH_VLOXEI16V 0x0c005007 |
#define | MASK_VLOXEI16V 0xfc00707f |
#define | MATCH_VLOXEI32V 0x0c006007 |
#define | MASK_VLOXEI32V 0xfc00707f |
#define | MATCH_VLOXEI64V 0x0c007007 |
#define | MASK_VLOXEI64V 0xfc00707f |
#define | MATCH_VSOXEI8V 0x0c000027 |
#define | MASK_VSOXEI8V 0xfc00707f |
#define | MATCH_VSOXEI16V 0x0c005027 |
#define | MASK_VSOXEI16V 0xfc00707f |
#define | MATCH_VSOXEI32V 0x0c006027 |
#define | MASK_VSOXEI32V 0xfc00707f |
#define | MATCH_VSOXEI64V 0x0c007027 |
#define | MASK_VSOXEI64V 0xfc00707f |
#define | MATCH_VLUXEI8V 0x04000007 |
#define | MASK_VLUXEI8V 0xfc00707f |
#define | MATCH_VLUXEI16V 0x04005007 |
#define | MASK_VLUXEI16V 0xfc00707f |
#define | MATCH_VLUXEI32V 0x04006007 |
#define | MASK_VLUXEI32V 0xfc00707f |
#define | MATCH_VLUXEI64V 0x04007007 |
#define | MASK_VLUXEI64V 0xfc00707f |
#define | MATCH_VSUXEI8V 0x04000027 |
#define | MASK_VSUXEI8V 0xfc00707f |
#define | MATCH_VSUXEI16V 0x04005027 |
#define | MASK_VSUXEI16V 0xfc00707f |
#define | MATCH_VSUXEI32V 0x04006027 |
#define | MASK_VSUXEI32V 0xfc00707f |
#define | MATCH_VSUXEI64V 0x04007027 |
#define | MASK_VSUXEI64V 0xfc00707f |
#define | MATCH_VLE8FFV 0x01000007 |
#define | MASK_VLE8FFV 0xfdf0707f |
#define | MATCH_VLE16FFV 0x01005007 |
#define | MASK_VLE16FFV 0xfdf0707f |
#define | MATCH_VLE32FFV 0x01006007 |
#define | MASK_VLE32FFV 0xfdf0707f |
#define | MATCH_VLE64FFV 0x01007007 |
#define | MASK_VLE64FFV 0xfdf0707f |
#define | MATCH_VLSEG2E8V 0x20000007 |
#define | MASK_VLSEG2E8V 0xfdf0707f |
#define | MATCH_VSSEG2E8V 0x20000027 |
#define | MASK_VSSEG2E8V 0xfdf0707f |
#define | MATCH_VLSEG3E8V 0x40000007 |
#define | MASK_VLSEG3E8V 0xfdf0707f |
#define | MATCH_VSSEG3E8V 0x40000027 |
#define | MASK_VSSEG3E8V 0xfdf0707f |
#define | MATCH_VLSEG4E8V 0x60000007 |
#define | MASK_VLSEG4E8V 0xfdf0707f |
#define | MATCH_VSSEG4E8V 0x60000027 |
#define | MASK_VSSEG4E8V 0xfdf0707f |
#define | MATCH_VLSEG5E8V 0x80000007 |
#define | MASK_VLSEG5E8V 0xfdf0707f |
#define | MATCH_VSSEG5E8V 0x80000027 |
#define | MASK_VSSEG5E8V 0xfdf0707f |
#define | MATCH_VLSEG6E8V 0xa0000007 |
#define | MASK_VLSEG6E8V 0xfdf0707f |
#define | MATCH_VSSEG6E8V 0xa0000027 |
#define | MASK_VSSEG6E8V 0xfdf0707f |
#define | MATCH_VLSEG7E8V 0xc0000007 |
#define | MASK_VLSEG7E8V 0xfdf0707f |
#define | MATCH_VSSEG7E8V 0xc0000027 |
#define | MASK_VSSEG7E8V 0xfdf0707f |
#define | MATCH_VLSEG8E8V 0xe0000007 |
#define | MASK_VLSEG8E8V 0xfdf0707f |
#define | MATCH_VSSEG8E8V 0xe0000027 |
#define | MASK_VSSEG8E8V 0xfdf0707f |
#define | MATCH_VLSEG2E16V 0x20005007 |
#define | MASK_VLSEG2E16V 0xfdf0707f |
#define | MATCH_VSSEG2E16V 0x20005027 |
#define | MASK_VSSEG2E16V 0xfdf0707f |
#define | MATCH_VLSEG3E16V 0x40005007 |
#define | MASK_VLSEG3E16V 0xfdf0707f |
#define | MATCH_VSSEG3E16V 0x40005027 |
#define | MASK_VSSEG3E16V 0xfdf0707f |
#define | MATCH_VLSEG4E16V 0x60005007 |
#define | MASK_VLSEG4E16V 0xfdf0707f |
#define | MATCH_VSSEG4E16V 0x60005027 |
#define | MASK_VSSEG4E16V 0xfdf0707f |
#define | MATCH_VLSEG5E16V 0x80005007 |
#define | MASK_VLSEG5E16V 0xfdf0707f |
#define | MATCH_VSSEG5E16V 0x80005027 |
#define | MASK_VSSEG5E16V 0xfdf0707f |
#define | MATCH_VLSEG6E16V 0xa0005007 |
#define | MASK_VLSEG6E16V 0xfdf0707f |
#define | MATCH_VSSEG6E16V 0xa0005027 |
#define | MASK_VSSEG6E16V 0xfdf0707f |
#define | MATCH_VLSEG7E16V 0xc0005007 |
#define | MASK_VLSEG7E16V 0xfdf0707f |
#define | MATCH_VSSEG7E16V 0xc0005027 |
#define | MASK_VSSEG7E16V 0xfdf0707f |
#define | MATCH_VLSEG8E16V 0xe0005007 |
#define | MASK_VLSEG8E16V 0xfdf0707f |
#define | MATCH_VSSEG8E16V 0xe0005027 |
#define | MASK_VSSEG8E16V 0xfdf0707f |
#define | MATCH_VLSEG2E32V 0x20006007 |
#define | MASK_VLSEG2E32V 0xfdf0707f |
#define | MATCH_VSSEG2E32V 0x20006027 |
#define | MASK_VSSEG2E32V 0xfdf0707f |
#define | MATCH_VLSEG3E32V 0x40006007 |
#define | MASK_VLSEG3E32V 0xfdf0707f |
#define | MATCH_VSSEG3E32V 0x40006027 |
#define | MASK_VSSEG3E32V 0xfdf0707f |
#define | MATCH_VLSEG4E32V 0x60006007 |
#define | MASK_VLSEG4E32V 0xfdf0707f |
#define | MATCH_VSSEG4E32V 0x60006027 |
#define | MASK_VSSEG4E32V 0xfdf0707f |
#define | MATCH_VLSEG5E32V 0x80006007 |
#define | MASK_VLSEG5E32V 0xfdf0707f |
#define | MATCH_VSSEG5E32V 0x80006027 |
#define | MASK_VSSEG5E32V 0xfdf0707f |
#define | MATCH_VLSEG6E32V 0xa0006007 |
#define | MASK_VLSEG6E32V 0xfdf0707f |
#define | MATCH_VSSEG6E32V 0xa0006027 |
#define | MASK_VSSEG6E32V 0xfdf0707f |
#define | MATCH_VLSEG7E32V 0xc0006007 |
#define | MASK_VLSEG7E32V 0xfdf0707f |
#define | MATCH_VSSEG7E32V 0xc0006027 |
#define | MASK_VSSEG7E32V 0xfdf0707f |
#define | MATCH_VLSEG8E32V 0xe0006007 |
#define | MASK_VLSEG8E32V 0xfdf0707f |
#define | MATCH_VSSEG8E32V 0xe0006027 |
#define | MASK_VSSEG8E32V 0xfdf0707f |
#define | MATCH_VLSEG2E64V 0x20007007 |
#define | MASK_VLSEG2E64V 0xfdf0707f |
#define | MATCH_VSSEG2E64V 0x20007027 |
#define | MASK_VSSEG2E64V 0xfdf0707f |
#define | MATCH_VLSEG3E64V 0x40007007 |
#define | MASK_VLSEG3E64V 0xfdf0707f |
#define | MATCH_VSSEG3E64V 0x40007027 |
#define | MASK_VSSEG3E64V 0xfdf0707f |
#define | MATCH_VLSEG4E64V 0x60007007 |
#define | MASK_VLSEG4E64V 0xfdf0707f |
#define | MATCH_VSSEG4E64V 0x60007027 |
#define | MASK_VSSEG4E64V 0xfdf0707f |
#define | MATCH_VLSEG5E64V 0x80007007 |
#define | MASK_VLSEG5E64V 0xfdf0707f |
#define | MATCH_VSSEG5E64V 0x80007027 |
#define | MASK_VSSEG5E64V 0xfdf0707f |
#define | MATCH_VLSEG6E64V 0xa0007007 |
#define | MASK_VLSEG6E64V 0xfdf0707f |
#define | MATCH_VSSEG6E64V 0xa0007027 |
#define | MASK_VSSEG6E64V 0xfdf0707f |
#define | MATCH_VLSEG7E64V 0xc0007007 |
#define | MASK_VLSEG7E64V 0xfdf0707f |
#define | MATCH_VSSEG7E64V 0xc0007027 |
#define | MASK_VSSEG7E64V 0xfdf0707f |
#define | MATCH_VLSEG8E64V 0xe0007007 |
#define | MASK_VLSEG8E64V 0xfdf0707f |
#define | MATCH_VSSEG8E64V 0xe0007027 |
#define | MASK_VSSEG8E64V 0xfdf0707f |
#define | MATCH_VLSSEG2E8V 0x28000007 |
#define | MASK_VLSSEG2E8V 0xfc00707f |
#define | MATCH_VSSSEG2E8V 0x28000027 |
#define | MASK_VSSSEG2E8V 0xfc00707f |
#define | MATCH_VLSSEG3E8V 0x48000007 |
#define | MASK_VLSSEG3E8V 0xfc00707f |
#define | MATCH_VSSSEG3E8V 0x48000027 |
#define | MASK_VSSSEG3E8V 0xfc00707f |
#define | MATCH_VLSSEG4E8V 0x68000007 |
#define | MASK_VLSSEG4E8V 0xfc00707f |
#define | MATCH_VSSSEG4E8V 0x68000027 |
#define | MASK_VSSSEG4E8V 0xfc00707f |
#define | MATCH_VLSSEG5E8V 0x88000007 |
#define | MASK_VLSSEG5E8V 0xfc00707f |
#define | MATCH_VSSSEG5E8V 0x88000027 |
#define | MASK_VSSSEG5E8V 0xfc00707f |
#define | MATCH_VLSSEG6E8V 0xa8000007 |
#define | MASK_VLSSEG6E8V 0xfc00707f |
#define | MATCH_VSSSEG6E8V 0xa8000027 |
#define | MASK_VSSSEG6E8V 0xfc00707f |
#define | MATCH_VLSSEG7E8V 0xc8000007 |
#define | MASK_VLSSEG7E8V 0xfc00707f |
#define | MATCH_VSSSEG7E8V 0xc8000027 |
#define | MASK_VSSSEG7E8V 0xfc00707f |
#define | MATCH_VLSSEG8E8V 0xe8000007 |
#define | MASK_VLSSEG8E8V 0xfc00707f |
#define | MATCH_VSSSEG8E8V 0xe8000027 |
#define | MASK_VSSSEG8E8V 0xfc00707f |
#define | MATCH_VLSSEG2E16V 0x28005007 |
#define | MASK_VLSSEG2E16V 0xfc00707f |
#define | MATCH_VSSSEG2E16V 0x28005027 |
#define | MASK_VSSSEG2E16V 0xfc00707f |
#define | MATCH_VLSSEG3E16V 0x48005007 |
#define | MASK_VLSSEG3E16V 0xfc00707f |
#define | MATCH_VSSSEG3E16V 0x48005027 |
#define | MASK_VSSSEG3E16V 0xfc00707f |
#define | MATCH_VLSSEG4E16V 0x68005007 |
#define | MASK_VLSSEG4E16V 0xfc00707f |
#define | MATCH_VSSSEG4E16V 0x68005027 |
#define | MASK_VSSSEG4E16V 0xfc00707f |
#define | MATCH_VLSSEG5E16V 0x88005007 |
#define | MASK_VLSSEG5E16V 0xfc00707f |
#define | MATCH_VSSSEG5E16V 0x88005027 |
#define | MASK_VSSSEG5E16V 0xfc00707f |
#define | MATCH_VLSSEG6E16V 0xa8005007 |
#define | MASK_VLSSEG6E16V 0xfc00707f |
#define | MATCH_VSSSEG6E16V 0xa8005027 |
#define | MASK_VSSSEG6E16V 0xfc00707f |
#define | MATCH_VLSSEG7E16V 0xc8005007 |
#define | MASK_VLSSEG7E16V 0xfc00707f |
#define | MATCH_VSSSEG7E16V 0xc8005027 |
#define | MASK_VSSSEG7E16V 0xfc00707f |
#define | MATCH_VLSSEG8E16V 0xe8005007 |
#define | MASK_VLSSEG8E16V 0xfc00707f |
#define | MATCH_VSSSEG8E16V 0xe8005027 |
#define | MASK_VSSSEG8E16V 0xfc00707f |
#define | MATCH_VLSSEG2E32V 0x28006007 |
#define | MASK_VLSSEG2E32V 0xfc00707f |
#define | MATCH_VSSSEG2E32V 0x28006027 |
#define | MASK_VSSSEG2E32V 0xfc00707f |
#define | MATCH_VLSSEG3E32V 0x48006007 |
#define | MASK_VLSSEG3E32V 0xfc00707f |
#define | MATCH_VSSSEG3E32V 0x48006027 |
#define | MASK_VSSSEG3E32V 0xfc00707f |
#define | MATCH_VLSSEG4E32V 0x68006007 |
#define | MASK_VLSSEG4E32V 0xfc00707f |
#define | MATCH_VSSSEG4E32V 0x68006027 |
#define | MASK_VSSSEG4E32V 0xfc00707f |
#define | MATCH_VLSSEG5E32V 0x88006007 |
#define | MASK_VLSSEG5E32V 0xfc00707f |
#define | MATCH_VSSSEG5E32V 0x88006027 |
#define | MASK_VSSSEG5E32V 0xfc00707f |
#define | MATCH_VLSSEG6E32V 0xa8006007 |
#define | MASK_VLSSEG6E32V 0xfc00707f |
#define | MATCH_VSSSEG6E32V 0xa8006027 |
#define | MASK_VSSSEG6E32V 0xfc00707f |
#define | MATCH_VLSSEG7E32V 0xc8006007 |
#define | MASK_VLSSEG7E32V 0xfc00707f |
#define | MATCH_VSSSEG7E32V 0xc8006027 |
#define | MASK_VSSSEG7E32V 0xfc00707f |
#define | MATCH_VLSSEG8E32V 0xe8006007 |
#define | MASK_VLSSEG8E32V 0xfc00707f |
#define | MATCH_VSSSEG8E32V 0xe8006027 |
#define | MASK_VSSSEG8E32V 0xfc00707f |
#define | MATCH_VLSSEG2E64V 0x28007007 |
#define | MASK_VLSSEG2E64V 0xfc00707f |
#define | MATCH_VSSSEG2E64V 0x28007027 |
#define | MASK_VSSSEG2E64V 0xfc00707f |
#define | MATCH_VLSSEG3E64V 0x48007007 |
#define | MASK_VLSSEG3E64V 0xfc00707f |
#define | MATCH_VSSSEG3E64V 0x48007027 |
#define | MASK_VSSSEG3E64V 0xfc00707f |
#define | MATCH_VLSSEG4E64V 0x68007007 |
#define | MASK_VLSSEG4E64V 0xfc00707f |
#define | MATCH_VSSSEG4E64V 0x68007027 |
#define | MASK_VSSSEG4E64V 0xfc00707f |
#define | MATCH_VLSSEG5E64V 0x88007007 |
#define | MASK_VLSSEG5E64V 0xfc00707f |
#define | MATCH_VSSSEG5E64V 0x88007027 |
#define | MASK_VSSSEG5E64V 0xfc00707f |
#define | MATCH_VLSSEG6E64V 0xa8007007 |
#define | MASK_VLSSEG6E64V 0xfc00707f |
#define | MATCH_VSSSEG6E64V 0xa8007027 |
#define | MASK_VSSSEG6E64V 0xfc00707f |
#define | MATCH_VLSSEG7E64V 0xc8007007 |
#define | MASK_VLSSEG7E64V 0xfc00707f |
#define | MATCH_VSSSEG7E64V 0xc8007027 |
#define | MASK_VSSSEG7E64V 0xfc00707f |
#define | MATCH_VLSSEG8E64V 0xe8007007 |
#define | MASK_VLSSEG8E64V 0xfc00707f |
#define | MATCH_VSSSEG8E64V 0xe8007027 |
#define | MASK_VSSSEG8E64V 0xfc00707f |
#define | MATCH_VLOXSEG2EI8V 0x2c000007 |
#define | MASK_VLOXSEG2EI8V 0xfc00707f |
#define | MATCH_VSOXSEG2EI8V 0x2c000027 |
#define | MASK_VSOXSEG2EI8V 0xfc00707f |
#define | MATCH_VLOXSEG3EI8V 0x4c000007 |
#define | MASK_VLOXSEG3EI8V 0xfc00707f |
#define | MATCH_VSOXSEG3EI8V 0x4c000027 |
#define | MASK_VSOXSEG3EI8V 0xfc00707f |
#define | MATCH_VLOXSEG4EI8V 0x6c000007 |
#define | MASK_VLOXSEG4EI8V 0xfc00707f |
#define | MATCH_VSOXSEG4EI8V 0x6c000027 |
#define | MASK_VSOXSEG4EI8V 0xfc00707f |
#define | MATCH_VLOXSEG5EI8V 0x8c000007 |
#define | MASK_VLOXSEG5EI8V 0xfc00707f |
#define | MATCH_VSOXSEG5EI8V 0x8c000027 |
#define | MASK_VSOXSEG5EI8V 0xfc00707f |
#define | MATCH_VLOXSEG6EI8V 0xac000007 |
#define | MASK_VLOXSEG6EI8V 0xfc00707f |
#define | MATCH_VSOXSEG6EI8V 0xac000027 |
#define | MASK_VSOXSEG6EI8V 0xfc00707f |
#define | MATCH_VLOXSEG7EI8V 0xcc000007 |
#define | MASK_VLOXSEG7EI8V 0xfc00707f |
#define | MATCH_VSOXSEG7EI8V 0xcc000027 |
#define | MASK_VSOXSEG7EI8V 0xfc00707f |
#define | MATCH_VLOXSEG8EI8V 0xec000007 |
#define | MASK_VLOXSEG8EI8V 0xfc00707f |
#define | MATCH_VSOXSEG8EI8V 0xec000027 |
#define | MASK_VSOXSEG8EI8V 0xfc00707f |
#define | MATCH_VLUXSEG2EI8V 0x24000007 |
#define | MASK_VLUXSEG2EI8V 0xfc00707f |
#define | MATCH_VSUXSEG2EI8V 0x24000027 |
#define | MASK_VSUXSEG2EI8V 0xfc00707f |
#define | MATCH_VLUXSEG3EI8V 0x44000007 |
#define | MASK_VLUXSEG3EI8V 0xfc00707f |
#define | MATCH_VSUXSEG3EI8V 0x44000027 |
#define | MASK_VSUXSEG3EI8V 0xfc00707f |
#define | MATCH_VLUXSEG4EI8V 0x64000007 |
#define | MASK_VLUXSEG4EI8V 0xfc00707f |
#define | MATCH_VSUXSEG4EI8V 0x64000027 |
#define | MASK_VSUXSEG4EI8V 0xfc00707f |
#define | MATCH_VLUXSEG5EI8V 0x84000007 |
#define | MASK_VLUXSEG5EI8V 0xfc00707f |
#define | MATCH_VSUXSEG5EI8V 0x84000027 |
#define | MASK_VSUXSEG5EI8V 0xfc00707f |
#define | MATCH_VLUXSEG6EI8V 0xa4000007 |
#define | MASK_VLUXSEG6EI8V 0xfc00707f |
#define | MATCH_VSUXSEG6EI8V 0xa4000027 |
#define | MASK_VSUXSEG6EI8V 0xfc00707f |
#define | MATCH_VLUXSEG7EI8V 0xc4000007 |
#define | MASK_VLUXSEG7EI8V 0xfc00707f |
#define | MATCH_VSUXSEG7EI8V 0xc4000027 |
#define | MASK_VSUXSEG7EI8V 0xfc00707f |
#define | MATCH_VLUXSEG8EI8V 0xe4000007 |
#define | MASK_VLUXSEG8EI8V 0xfc00707f |
#define | MATCH_VSUXSEG8EI8V 0xe4000027 |
#define | MASK_VSUXSEG8EI8V 0xfc00707f |
#define | MATCH_VLOXSEG2EI16V 0x2c005007 |
#define | MASK_VLOXSEG2EI16V 0xfc00707f |
#define | MATCH_VSOXSEG2EI16V 0x2c005027 |
#define | MASK_VSOXSEG2EI16V 0xfc00707f |
#define | MATCH_VLOXSEG3EI16V 0x4c005007 |
#define | MASK_VLOXSEG3EI16V 0xfc00707f |
#define | MATCH_VSOXSEG3EI16V 0x4c005027 |
#define | MASK_VSOXSEG3EI16V 0xfc00707f |
#define | MATCH_VLOXSEG4EI16V 0x6c005007 |
#define | MASK_VLOXSEG4EI16V 0xfc00707f |
#define | MATCH_VSOXSEG4EI16V 0x6c005027 |
#define | MASK_VSOXSEG4EI16V 0xfc00707f |
#define | MATCH_VLOXSEG5EI16V 0x8c005007 |
#define | MASK_VLOXSEG5EI16V 0xfc00707f |
#define | MATCH_VSOXSEG5EI16V 0x8c005027 |
#define | MASK_VSOXSEG5EI16V 0xfc00707f |
#define | MATCH_VLOXSEG6EI16V 0xac005007 |
#define | MASK_VLOXSEG6EI16V 0xfc00707f |
#define | MATCH_VSOXSEG6EI16V 0xac005027 |
#define | MASK_VSOXSEG6EI16V 0xfc00707f |
#define | MATCH_VLOXSEG7EI16V 0xcc005007 |
#define | MASK_VLOXSEG7EI16V 0xfc00707f |
#define | MATCH_VSOXSEG7EI16V 0xcc005027 |
#define | MASK_VSOXSEG7EI16V 0xfc00707f |
#define | MATCH_VLOXSEG8EI16V 0xec005007 |
#define | MASK_VLOXSEG8EI16V 0xfc00707f |
#define | MATCH_VSOXSEG8EI16V 0xec005027 |
#define | MASK_VSOXSEG8EI16V 0xfc00707f |
#define | MATCH_VLUXSEG2EI16V 0x24005007 |
#define | MASK_VLUXSEG2EI16V 0xfc00707f |
#define | MATCH_VSUXSEG2EI16V 0x24005027 |
#define | MASK_VSUXSEG2EI16V 0xfc00707f |
#define | MATCH_VLUXSEG3EI16V 0x44005007 |
#define | MASK_VLUXSEG3EI16V 0xfc00707f |
#define | MATCH_VSUXSEG3EI16V 0x44005027 |
#define | MASK_VSUXSEG3EI16V 0xfc00707f |
#define | MATCH_VLUXSEG4EI16V 0x64005007 |
#define | MASK_VLUXSEG4EI16V 0xfc00707f |
#define | MATCH_VSUXSEG4EI16V 0x64005027 |
#define | MASK_VSUXSEG4EI16V 0xfc00707f |
#define | MATCH_VLUXSEG5EI16V 0x84005007 |
#define | MASK_VLUXSEG5EI16V 0xfc00707f |
#define | MATCH_VSUXSEG5EI16V 0x84005027 |
#define | MASK_VSUXSEG5EI16V 0xfc00707f |
#define | MATCH_VLUXSEG6EI16V 0xa4005007 |
#define | MASK_VLUXSEG6EI16V 0xfc00707f |
#define | MATCH_VSUXSEG6EI16V 0xa4005027 |
#define | MASK_VSUXSEG6EI16V 0xfc00707f |
#define | MATCH_VLUXSEG7EI16V 0xc4005007 |
#define | MASK_VLUXSEG7EI16V 0xfc00707f |
#define | MATCH_VSUXSEG7EI16V 0xc4005027 |
#define | MASK_VSUXSEG7EI16V 0xfc00707f |
#define | MATCH_VLUXSEG8EI16V 0xe4005007 |
#define | MASK_VLUXSEG8EI16V 0xfc00707f |
#define | MATCH_VSUXSEG8EI16V 0xe4005027 |
#define | MASK_VSUXSEG8EI16V 0xfc00707f |
#define | MATCH_VLOXSEG2EI32V 0x2c006007 |
#define | MASK_VLOXSEG2EI32V 0xfc00707f |
#define | MATCH_VSOXSEG2EI32V 0x2c006027 |
#define | MASK_VSOXSEG2EI32V 0xfc00707f |
#define | MATCH_VLOXSEG3EI32V 0x4c006007 |
#define | MASK_VLOXSEG3EI32V 0xfc00707f |
#define | MATCH_VSOXSEG3EI32V 0x4c006027 |
#define | MASK_VSOXSEG3EI32V 0xfc00707f |
#define | MATCH_VLOXSEG4EI32V 0x6c006007 |
#define | MASK_VLOXSEG4EI32V 0xfc00707f |
#define | MATCH_VSOXSEG4EI32V 0x6c006027 |
#define | MASK_VSOXSEG4EI32V 0xfc00707f |
#define | MATCH_VLOXSEG5EI32V 0x8c006007 |
#define | MASK_VLOXSEG5EI32V 0xfc00707f |
#define | MATCH_VSOXSEG5EI32V 0x8c006027 |
#define | MASK_VSOXSEG5EI32V 0xfc00707f |
#define | MATCH_VLOXSEG6EI32V 0xac006007 |
#define | MASK_VLOXSEG6EI32V 0xfc00707f |
#define | MATCH_VSOXSEG6EI32V 0xac006027 |
#define | MASK_VSOXSEG6EI32V 0xfc00707f |
#define | MATCH_VLOXSEG7EI32V 0xcc006007 |
#define | MASK_VLOXSEG7EI32V 0xfc00707f |
#define | MATCH_VSOXSEG7EI32V 0xcc006027 |
#define | MASK_VSOXSEG7EI32V 0xfc00707f |
#define | MATCH_VLOXSEG8EI32V 0xec006007 |
#define | MASK_VLOXSEG8EI32V 0xfc00707f |
#define | MATCH_VSOXSEG8EI32V 0xec006027 |
#define | MASK_VSOXSEG8EI32V 0xfc00707f |
#define | MATCH_VLUXSEG2EI32V 0x24006007 |
#define | MASK_VLUXSEG2EI32V 0xfc00707f |
#define | MATCH_VSUXSEG2EI32V 0x24006027 |
#define | MASK_VSUXSEG2EI32V 0xfc00707f |
#define | MATCH_VLUXSEG3EI32V 0x44006007 |
#define | MASK_VLUXSEG3EI32V 0xfc00707f |
#define | MATCH_VSUXSEG3EI32V 0x44006027 |
#define | MASK_VSUXSEG3EI32V 0xfc00707f |
#define | MATCH_VLUXSEG4EI32V 0x64006007 |
#define | MASK_VLUXSEG4EI32V 0xfc00707f |
#define | MATCH_VSUXSEG4EI32V 0x64006027 |
#define | MASK_VSUXSEG4EI32V 0xfc00707f |
#define | MATCH_VLUXSEG5EI32V 0x84006007 |
#define | MASK_VLUXSEG5EI32V 0xfc00707f |
#define | MATCH_VSUXSEG5EI32V 0x84006027 |
#define | MASK_VSUXSEG5EI32V 0xfc00707f |
#define | MATCH_VLUXSEG6EI32V 0xa4006007 |
#define | MASK_VLUXSEG6EI32V 0xfc00707f |
#define | MATCH_VSUXSEG6EI32V 0xa4006027 |
#define | MASK_VSUXSEG6EI32V 0xfc00707f |
#define | MATCH_VLUXSEG7EI32V 0xc4006007 |
#define | MASK_VLUXSEG7EI32V 0xfc00707f |
#define | MATCH_VSUXSEG7EI32V 0xc4006027 |
#define | MASK_VSUXSEG7EI32V 0xfc00707f |
#define | MATCH_VLUXSEG8EI32V 0xe4006007 |
#define | MASK_VLUXSEG8EI32V 0xfc00707f |
#define | MATCH_VSUXSEG8EI32V 0xe4006027 |
#define | MASK_VSUXSEG8EI32V 0xfc00707f |
#define | MATCH_VLOXSEG2EI64V 0x2c007007 |
#define | MASK_VLOXSEG2EI64V 0xfc00707f |
#define | MATCH_VSOXSEG2EI64V 0x2c007027 |
#define | MASK_VSOXSEG2EI64V 0xfc00707f |
#define | MATCH_VLOXSEG3EI64V 0x4c007007 |
#define | MASK_VLOXSEG3EI64V 0xfc00707f |
#define | MATCH_VSOXSEG3EI64V 0x4c007027 |
#define | MASK_VSOXSEG3EI64V 0xfc00707f |
#define | MATCH_VLOXSEG4EI64V 0x6c007007 |
#define | MASK_VLOXSEG4EI64V 0xfc00707f |
#define | MATCH_VSOXSEG4EI64V 0x6c007027 |
#define | MASK_VSOXSEG4EI64V 0xfc00707f |
#define | MATCH_VLOXSEG5EI64V 0x8c007007 |
#define | MASK_VLOXSEG5EI64V 0xfc00707f |
#define | MATCH_VSOXSEG5EI64V 0x8c007027 |
#define | MASK_VSOXSEG5EI64V 0xfc00707f |
#define | MATCH_VLOXSEG6EI64V 0xac007007 |
#define | MASK_VLOXSEG6EI64V 0xfc00707f |
#define | MATCH_VSOXSEG6EI64V 0xac007027 |
#define | MASK_VSOXSEG6EI64V 0xfc00707f |
#define | MATCH_VLOXSEG7EI64V 0xcc007007 |
#define | MASK_VLOXSEG7EI64V 0xfc00707f |
#define | MATCH_VSOXSEG7EI64V 0xcc007027 |
#define | MASK_VSOXSEG7EI64V 0xfc00707f |
#define | MATCH_VLOXSEG8EI64V 0xec007007 |
#define | MASK_VLOXSEG8EI64V 0xfc00707f |
#define | MATCH_VSOXSEG8EI64V 0xec007027 |
#define | MASK_VSOXSEG8EI64V 0xfc00707f |
#define | MATCH_VLUXSEG2EI64V 0x24007007 |
#define | MASK_VLUXSEG2EI64V 0xfc00707f |
#define | MATCH_VSUXSEG2EI64V 0x24007027 |
#define | MASK_VSUXSEG2EI64V 0xfc00707f |
#define | MATCH_VLUXSEG3EI64V 0x44007007 |
#define | MASK_VLUXSEG3EI64V 0xfc00707f |
#define | MATCH_VSUXSEG3EI64V 0x44007027 |
#define | MASK_VSUXSEG3EI64V 0xfc00707f |
#define | MATCH_VLUXSEG4EI64V 0x64007007 |
#define | MASK_VLUXSEG4EI64V 0xfc00707f |
#define | MATCH_VSUXSEG4EI64V 0x64007027 |
#define | MASK_VSUXSEG4EI64V 0xfc00707f |
#define | MATCH_VLUXSEG5EI64V 0x84007007 |
#define | MASK_VLUXSEG5EI64V 0xfc00707f |
#define | MATCH_VSUXSEG5EI64V 0x84007027 |
#define | MASK_VSUXSEG5EI64V 0xfc00707f |
#define | MATCH_VLUXSEG6EI64V 0xa4007007 |
#define | MASK_VLUXSEG6EI64V 0xfc00707f |
#define | MATCH_VSUXSEG6EI64V 0xa4007027 |
#define | MASK_VSUXSEG6EI64V 0xfc00707f |
#define | MATCH_VLUXSEG7EI64V 0xc4007007 |
#define | MASK_VLUXSEG7EI64V 0xfc00707f |
#define | MATCH_VSUXSEG7EI64V 0xc4007027 |
#define | MASK_VSUXSEG7EI64V 0xfc00707f |
#define | MATCH_VLUXSEG8EI64V 0xe4007007 |
#define | MASK_VLUXSEG8EI64V 0xfc00707f |
#define | MATCH_VSUXSEG8EI64V 0xe4007027 |
#define | MASK_VSUXSEG8EI64V 0xfc00707f |
#define | MATCH_VLSEG2E8FFV 0x21000007 |
#define | MASK_VLSEG2E8FFV 0xfdf0707f |
#define | MATCH_VLSEG3E8FFV 0x41000007 |
#define | MASK_VLSEG3E8FFV 0xfdf0707f |
#define | MATCH_VLSEG4E8FFV 0x61000007 |
#define | MASK_VLSEG4E8FFV 0xfdf0707f |
#define | MATCH_VLSEG5E8FFV 0x81000007 |
#define | MASK_VLSEG5E8FFV 0xfdf0707f |
#define | MATCH_VLSEG6E8FFV 0xa1000007 |
#define | MASK_VLSEG6E8FFV 0xfdf0707f |
#define | MATCH_VLSEG7E8FFV 0xc1000007 |
#define | MASK_VLSEG7E8FFV 0xfdf0707f |
#define | MATCH_VLSEG8E8FFV 0xe1000007 |
#define | MASK_VLSEG8E8FFV 0xfdf0707f |
#define | MATCH_VLSEG2E16FFV 0x21005007 |
#define | MASK_VLSEG2E16FFV 0xfdf0707f |
#define | MATCH_VLSEG3E16FFV 0x41005007 |
#define | MASK_VLSEG3E16FFV 0xfdf0707f |
#define | MATCH_VLSEG4E16FFV 0x61005007 |
#define | MASK_VLSEG4E16FFV 0xfdf0707f |
#define | MATCH_VLSEG5E16FFV 0x81005007 |
#define | MASK_VLSEG5E16FFV 0xfdf0707f |
#define | MATCH_VLSEG6E16FFV 0xa1005007 |
#define | MASK_VLSEG6E16FFV 0xfdf0707f |
#define | MATCH_VLSEG7E16FFV 0xc1005007 |
#define | MASK_VLSEG7E16FFV 0xfdf0707f |
#define | MATCH_VLSEG8E16FFV 0xe1005007 |
#define | MASK_VLSEG8E16FFV 0xfdf0707f |
#define | MATCH_VLSEG2E32FFV 0x21006007 |
#define | MASK_VLSEG2E32FFV 0xfdf0707f |
#define | MATCH_VLSEG3E32FFV 0x41006007 |
#define | MASK_VLSEG3E32FFV 0xfdf0707f |
#define | MATCH_VLSEG4E32FFV 0x61006007 |
#define | MASK_VLSEG4E32FFV 0xfdf0707f |
#define | MATCH_VLSEG5E32FFV 0x81006007 |
#define | MASK_VLSEG5E32FFV 0xfdf0707f |
#define | MATCH_VLSEG6E32FFV 0xa1006007 |
#define | MASK_VLSEG6E32FFV 0xfdf0707f |
#define | MATCH_VLSEG7E32FFV 0xc1006007 |
#define | MASK_VLSEG7E32FFV 0xfdf0707f |
#define | MATCH_VLSEG8E32FFV 0xe1006007 |
#define | MASK_VLSEG8E32FFV 0xfdf0707f |
#define | MATCH_VLSEG2E64FFV 0x21007007 |
#define | MASK_VLSEG2E64FFV 0xfdf0707f |
#define | MATCH_VLSEG3E64FFV 0x41007007 |
#define | MASK_VLSEG3E64FFV 0xfdf0707f |
#define | MATCH_VLSEG4E64FFV 0x61007007 |
#define | MASK_VLSEG4E64FFV 0xfdf0707f |
#define | MATCH_VLSEG5E64FFV 0x81007007 |
#define | MASK_VLSEG5E64FFV 0xfdf0707f |
#define | MATCH_VLSEG6E64FFV 0xa1007007 |
#define | MASK_VLSEG6E64FFV 0xfdf0707f |
#define | MATCH_VLSEG7E64FFV 0xc1007007 |
#define | MASK_VLSEG7E64FFV 0xfdf0707f |
#define | MATCH_VLSEG8E64FFV 0xe1007007 |
#define | MASK_VLSEG8E64FFV 0xfdf0707f |
#define | MATCH_VL1RE8V 0x02800007 |
#define | MASK_VL1RE8V 0xfff0707f |
#define | MATCH_VL1RE16V 0x02805007 |
#define | MASK_VL1RE16V 0xfff0707f |
#define | MATCH_VL1RE32V 0x02806007 |
#define | MASK_VL1RE32V 0xfff0707f |
#define | MATCH_VL1RE64V 0x02807007 |
#define | MASK_VL1RE64V 0xfff0707f |
#define | MATCH_VL2RE8V 0x22800007 |
#define | MASK_VL2RE8V 0xfff0707f |
#define | MATCH_VL2RE16V 0x22805007 |
#define | MASK_VL2RE16V 0xfff0707f |
#define | MATCH_VL2RE32V 0x22806007 |
#define | MASK_VL2RE32V 0xfff0707f |
#define | MATCH_VL2RE64V 0x22807007 |
#define | MASK_VL2RE64V 0xfff0707f |
#define | MATCH_VL4RE8V 0x62800007 |
#define | MASK_VL4RE8V 0xfff0707f |
#define | MATCH_VL4RE16V 0x62805007 |
#define | MASK_VL4RE16V 0xfff0707f |
#define | MATCH_VL4RE32V 0x62806007 |
#define | MASK_VL4RE32V 0xfff0707f |
#define | MATCH_VL4RE64V 0x62807007 |
#define | MASK_VL4RE64V 0xfff0707f |
#define | MATCH_VL8RE8V 0xe2800007 |
#define | MASK_VL8RE8V 0xfff0707f |
#define | MATCH_VL8RE16V 0xe2805007 |
#define | MASK_VL8RE16V 0xfff0707f |
#define | MATCH_VL8RE32V 0xe2806007 |
#define | MASK_VL8RE32V 0xfff0707f |
#define | MATCH_VL8RE64V 0xe2807007 |
#define | MASK_VL8RE64V 0xfff0707f |
#define | MATCH_VS1RV 0x02800027 |
#define | MASK_VS1RV 0xfff0707f |
#define | MATCH_VS2RV 0x22800027 |
#define | MASK_VS2RV 0xfff0707f |
#define | MATCH_VS4RV 0x62800027 |
#define | MASK_VS4RV 0xfff0707f |
#define | MATCH_VS8RV 0xe2800027 |
#define | MASK_VS8RV 0xfff0707f |
#define | MATCH_VADDVV 0x00000057 |
#define | MASK_VADDVV 0xfc00707f |
#define | MATCH_VADDVX 0x00004057 |
#define | MASK_VADDVX 0xfc00707f |
#define | MATCH_VADDVI 0x00003057 |
#define | MASK_VADDVI 0xfc00707f |
#define | MATCH_VSUBVV 0x08000057 |
#define | MASK_VSUBVV 0xfc00707f |
#define | MATCH_VSUBVX 0x08004057 |
#define | MASK_VSUBVX 0xfc00707f |
#define | MATCH_VRSUBVX 0x0c004057 |
#define | MASK_VRSUBVX 0xfc00707f |
#define | MATCH_VRSUBVI 0x0c003057 |
#define | MASK_VRSUBVI 0xfc00707f |
#define | MATCH_VWCVTXXV 0xc4006057 |
#define | MASK_VWCVTXXV 0xfc0ff07f |
#define | MATCH_VWCVTUXXV 0xc0006057 |
#define | MASK_VWCVTUXXV 0xfc0ff07f |
#define | MATCH_VWADDVV 0xc4002057 |
#define | MASK_VWADDVV 0xfc00707f |
#define | MATCH_VWADDVX 0xc4006057 |
#define | MASK_VWADDVX 0xfc00707f |
#define | MATCH_VWSUBVV 0xcc002057 |
#define | MASK_VWSUBVV 0xfc00707f |
#define | MATCH_VWSUBVX 0xcc006057 |
#define | MASK_VWSUBVX 0xfc00707f |
#define | MATCH_VWADDWV 0xd4002057 |
#define | MASK_VWADDWV 0xfc00707f |
#define | MATCH_VWADDWX 0xd4006057 |
#define | MASK_VWADDWX 0xfc00707f |
#define | MATCH_VWSUBWV 0xdc002057 |
#define | MASK_VWSUBWV 0xfc00707f |
#define | MATCH_VWSUBWX 0xdc006057 |
#define | MASK_VWSUBWX 0xfc00707f |
#define | MATCH_VWADDUVV 0xc0002057 |
#define | MASK_VWADDUVV 0xfc00707f |
#define | MATCH_VWADDUVX 0xc0006057 |
#define | MASK_VWADDUVX 0xfc00707f |
#define | MATCH_VWSUBUVV 0xc8002057 |
#define | MASK_VWSUBUVV 0xfc00707f |
#define | MATCH_VWSUBUVX 0xc8006057 |
#define | MASK_VWSUBUVX 0xfc00707f |
#define | MATCH_VWADDUWV 0xd0002057 |
#define | MASK_VWADDUWV 0xfc00707f |
#define | MATCH_VWADDUWX 0xd0006057 |
#define | MASK_VWADDUWX 0xfc00707f |
#define | MATCH_VWSUBUWV 0xd8002057 |
#define | MASK_VWSUBUWV 0xfc00707f |
#define | MATCH_VWSUBUWX 0xd8006057 |
#define | MASK_VWSUBUWX 0xfc00707f |
#define | MATCH_VZEXT_VF8 0x48012057 |
#define | MASK_VZEXT_VF8 0xfc0ff07f |
#define | MATCH_VSEXT_VF8 0x4801a057 |
#define | MASK_VSEXT_VF8 0xfc0ff07f |
#define | MATCH_VZEXT_VF4 0x48022057 |
#define | MASK_VZEXT_VF4 0xfc0ff07f |
#define | MATCH_VSEXT_VF4 0x4802a057 |
#define | MASK_VSEXT_VF4 0xfc0ff07f |
#define | MATCH_VZEXT_VF2 0x48032057 |
#define | MASK_VZEXT_VF2 0xfc0ff07f |
#define | MATCH_VSEXT_VF2 0x4803a057 |
#define | MASK_VSEXT_VF2 0xfc0ff07f |
#define | MATCH_VADCVVM 0x40000057 |
#define | MASK_VADCVVM 0xfe00707f |
#define | MATCH_VADCVXM 0x40004057 |
#define | MASK_VADCVXM 0xfe00707f |
#define | MATCH_VADCVIM 0x40003057 |
#define | MASK_VADCVIM 0xfe00707f |
#define | MATCH_VMADCVVM 0x44000057 |
#define | MASK_VMADCVVM 0xfe00707f |
#define | MATCH_VMADCVXM 0x44004057 |
#define | MASK_VMADCVXM 0xfe00707f |
#define | MATCH_VMADCVIM 0x44003057 |
#define | MASK_VMADCVIM 0xfe00707f |
#define | MATCH_VMADCVV 0x46000057 |
#define | MASK_VMADCVV 0xfe00707f |
#define | MATCH_VMADCVX 0x46004057 |
#define | MASK_VMADCVX 0xfe00707f |
#define | MATCH_VMADCVI 0x46003057 |
#define | MASK_VMADCVI 0xfe00707f |
#define | MATCH_VSBCVVM 0x48000057 |
#define | MASK_VSBCVVM 0xfe00707f |
#define | MATCH_VSBCVXM 0x48004057 |
#define | MASK_VSBCVXM 0xfe00707f |
#define | MATCH_VMSBCVVM 0x4c000057 |
#define | MASK_VMSBCVVM 0xfe00707f |
#define | MATCH_VMSBCVXM 0x4c004057 |
#define | MASK_VMSBCVXM 0xfe00707f |
#define | MATCH_VMSBCVV 0x4e000057 |
#define | MASK_VMSBCVV 0xfe00707f |
#define | MATCH_VMSBCVX 0x4e004057 |
#define | MASK_VMSBCVX 0xfe00707f |
#define | MATCH_VNOTV 0x2c0fb057 |
#define | MASK_VNOTV 0xfc0ff07f |
#define | MATCH_VANDVV 0x24000057 |
#define | MASK_VANDVV 0xfc00707f |
#define | MATCH_VANDVX 0x24004057 |
#define | MASK_VANDVX 0xfc00707f |
#define | MATCH_VANDVI 0x24003057 |
#define | MASK_VANDVI 0xfc00707f |
#define | MATCH_VORVV 0x28000057 |
#define | MASK_VORVV 0xfc00707f |
#define | MATCH_VORVX 0x28004057 |
#define | MASK_VORVX 0xfc00707f |
#define | MATCH_VORVI 0x28003057 |
#define | MASK_VORVI 0xfc00707f |
#define | MATCH_VXORVV 0x2c000057 |
#define | MASK_VXORVV 0xfc00707f |
#define | MATCH_VXORVX 0x2c004057 |
#define | MASK_VXORVX 0xfc00707f |
#define | MATCH_VXORVI 0x2c003057 |
#define | MASK_VXORVI 0xfc00707f |
#define | MATCH_VSLLVV 0x94000057 |
#define | MASK_VSLLVV 0xfc00707f |
#define | MATCH_VSLLVX 0x94004057 |
#define | MASK_VSLLVX 0xfc00707f |
#define | MATCH_VSLLVI 0x94003057 |
#define | MASK_VSLLVI 0xfc00707f |
#define | MATCH_VSRLVV 0xa0000057 |
#define | MASK_VSRLVV 0xfc00707f |
#define | MATCH_VSRLVX 0xa0004057 |
#define | MASK_VSRLVX 0xfc00707f |
#define | MATCH_VSRLVI 0xa0003057 |
#define | MASK_VSRLVI 0xfc00707f |
#define | MATCH_VSRAVV 0xa4000057 |
#define | MASK_VSRAVV 0xfc00707f |
#define | MATCH_VSRAVX 0xa4004057 |
#define | MASK_VSRAVX 0xfc00707f |
#define | MATCH_VSRAVI 0xa4003057 |
#define | MASK_VSRAVI 0xfc00707f |
#define | MATCH_VNCVTXXW 0xb0004057 |
#define | MASK_VNCVTXXW 0xfc0ff07f |
#define | MATCH_VNSRLWV 0xb0000057 |
#define | MASK_VNSRLWV 0xfc00707f |
#define | MATCH_VNSRLWX 0xb0004057 |
#define | MASK_VNSRLWX 0xfc00707f |
#define | MATCH_VNSRLWI 0xb0003057 |
#define | MASK_VNSRLWI 0xfc00707f |
#define | MATCH_VNSRAWV 0xb4000057 |
#define | MASK_VNSRAWV 0xfc00707f |
#define | MATCH_VNSRAWX 0xb4004057 |
#define | MASK_VNSRAWX 0xfc00707f |
#define | MATCH_VNSRAWI 0xb4003057 |
#define | MASK_VNSRAWI 0xfc00707f |
#define | MATCH_VMSEQVV 0x60000057 |
#define | MASK_VMSEQVV 0xfc00707f |
#define | MATCH_VMSEQVX 0x60004057 |
#define | MASK_VMSEQVX 0xfc00707f |
#define | MATCH_VMSEQVI 0x60003057 |
#define | MASK_VMSEQVI 0xfc00707f |
#define | MATCH_VMSNEVV 0x64000057 |
#define | MASK_VMSNEVV 0xfc00707f |
#define | MATCH_VMSNEVX 0x64004057 |
#define | MASK_VMSNEVX 0xfc00707f |
#define | MATCH_VMSNEVI 0x64003057 |
#define | MASK_VMSNEVI 0xfc00707f |
#define | MATCH_VMSLTVV 0x6c000057 |
#define | MASK_VMSLTVV 0xfc00707f |
#define | MATCH_VMSLTVX 0x6c004057 |
#define | MASK_VMSLTVX 0xfc00707f |
#define | MATCH_VMSLTUVV 0x68000057 |
#define | MASK_VMSLTUVV 0xfc00707f |
#define | MATCH_VMSLTUVX 0x68004057 |
#define | MASK_VMSLTUVX 0xfc00707f |
#define | MATCH_VMSLEVV 0x74000057 |
#define | MASK_VMSLEVV 0xfc00707f |
#define | MATCH_VMSLEVX 0x74004057 |
#define | MASK_VMSLEVX 0xfc00707f |
#define | MATCH_VMSLEVI 0x74003057 |
#define | MASK_VMSLEVI 0xfc00707f |
#define | MATCH_VMSLEUVV 0x70000057 |
#define | MASK_VMSLEUVV 0xfc00707f |
#define | MATCH_VMSLEUVX 0x70004057 |
#define | MASK_VMSLEUVX 0xfc00707f |
#define | MATCH_VMSLEUVI 0x70003057 |
#define | MASK_VMSLEUVI 0xfc00707f |
#define | MATCH_VMSGTVX 0x7c004057 |
#define | MASK_VMSGTVX 0xfc00707f |
#define | MATCH_VMSGTVI 0x7c003057 |
#define | MASK_VMSGTVI 0xfc00707f |
#define | MATCH_VMSGTUVX 0x78004057 |
#define | MASK_VMSGTUVX 0xfc00707f |
#define | MATCH_VMSGTUVI 0x78003057 |
#define | MASK_VMSGTUVI 0xfc00707f |
#define | MATCH_VMINVV 0x14000057 |
#define | MASK_VMINVV 0xfc00707f |
#define | MATCH_VMINVX 0x14004057 |
#define | MASK_VMINVX 0xfc00707f |
#define | MATCH_VMAXVV 0x1c000057 |
#define | MASK_VMAXVV 0xfc00707f |
#define | MATCH_VMAXVX 0x1c004057 |
#define | MASK_VMAXVX 0xfc00707f |
#define | MATCH_VMINUVV 0x10000057 |
#define | MASK_VMINUVV 0xfc00707f |
#define | MATCH_VMINUVX 0x10004057 |
#define | MASK_VMINUVX 0xfc00707f |
#define | MATCH_VMAXUVV 0x18000057 |
#define | MASK_VMAXUVV 0xfc00707f |
#define | MATCH_VMAXUVX 0x18004057 |
#define | MASK_VMAXUVX 0xfc00707f |
#define | MATCH_VMULVV 0x94002057 |
#define | MASK_VMULVV 0xfc00707f |
#define | MATCH_VMULVX 0x94006057 |
#define | MASK_VMULVX 0xfc00707f |
#define | MATCH_VMULHVV 0x9c002057 |
#define | MASK_VMULHVV 0xfc00707f |
#define | MATCH_VMULHVX 0x9c006057 |
#define | MASK_VMULHVX 0xfc00707f |
#define | MATCH_VMULHUVV 0x90002057 |
#define | MASK_VMULHUVV 0xfc00707f |
#define | MATCH_VMULHUVX 0x90006057 |
#define | MASK_VMULHUVX 0xfc00707f |
#define | MATCH_VMULHSUVV 0x98002057 |
#define | MASK_VMULHSUVV 0xfc00707f |
#define | MATCH_VMULHSUVX 0x98006057 |
#define | MASK_VMULHSUVX 0xfc00707f |
#define | MATCH_VWMULVV 0xec002057 |
#define | MASK_VWMULVV 0xfc00707f |
#define | MATCH_VWMULVX 0xec006057 |
#define | MASK_VWMULVX 0xfc00707f |
#define | MATCH_VWMULUVV 0xe0002057 |
#define | MASK_VWMULUVV 0xfc00707f |
#define | MATCH_VWMULUVX 0xe0006057 |
#define | MASK_VWMULUVX 0xfc00707f |
#define | MATCH_VWMULSUVV 0xe8002057 |
#define | MASK_VWMULSUVV 0xfc00707f |
#define | MATCH_VWMULSUVX 0xe8006057 |
#define | MASK_VWMULSUVX 0xfc00707f |
#define | MATCH_VMACCVV 0xb4002057 |
#define | MASK_VMACCVV 0xfc00707f |
#define | MATCH_VMACCVX 0xb4006057 |
#define | MASK_VMACCVX 0xfc00707f |
#define | MATCH_VNMSACVV 0xbc002057 |
#define | MASK_VNMSACVV 0xfc00707f |
#define | MATCH_VNMSACVX 0xbc006057 |
#define | MASK_VNMSACVX 0xfc00707f |
#define | MATCH_VMADDVV 0xa4002057 |
#define | MASK_VMADDVV 0xfc00707f |
#define | MATCH_VMADDVX 0xa4006057 |
#define | MASK_VMADDVX 0xfc00707f |
#define | MATCH_VNMSUBVV 0xac002057 |
#define | MASK_VNMSUBVV 0xfc00707f |
#define | MATCH_VNMSUBVX 0xac006057 |
#define | MASK_VNMSUBVX 0xfc00707f |
#define | MATCH_VWMACCUVV 0xf0002057 |
#define | MASK_VWMACCUVV 0xfc00707f |
#define | MATCH_VWMACCUVX 0xf0006057 |
#define | MASK_VWMACCUVX 0xfc00707f |
#define | MATCH_VWMACCVV 0xf4002057 |
#define | MASK_VWMACCVV 0xfc00707f |
#define | MATCH_VWMACCVX 0xf4006057 |
#define | MASK_VWMACCVX 0xfc00707f |
#define | MATCH_VWMACCSUVV 0xfc002057 |
#define | MASK_VWMACCSUVV 0xfc00707f |
#define | MATCH_VWMACCSUVX 0xfc006057 |
#define | MASK_VWMACCSUVX 0xfc00707f |
#define | MATCH_VWMACCUSVX 0xf8006057 |
#define | MASK_VWMACCUSVX 0xfc00707f |
#define | MATCH_VQMACCUVV 0xf0000057 |
#define | MASK_VQMACCUVV 0xfc00707f |
#define | MATCH_VQMACCUVX 0xf0004057 |
#define | MASK_VQMACCUVX 0xfc00707f |
#define | MATCH_VQMACCVV 0xf4000057 |
#define | MASK_VQMACCVV 0xfc00707f |
#define | MATCH_VQMACCVX 0xf4004057 |
#define | MASK_VQMACCVX 0xfc00707f |
#define | MATCH_VQMACCSUVV 0xfc000057 |
#define | MASK_VQMACCSUVV 0xfc00707f |
#define | MATCH_VQMACCSUVX 0xfc004057 |
#define | MASK_VQMACCSUVX 0xfc00707f |
#define | MATCH_VQMACCUSVX 0xf8004057 |
#define | MASK_VQMACCUSVX 0xfc00707f |
#define | MATCH_VDIVVV 0x84002057 |
#define | MASK_VDIVVV 0xfc00707f |
#define | MATCH_VDIVVX 0x84006057 |
#define | MASK_VDIVVX 0xfc00707f |
#define | MATCH_VDIVUVV 0x80002057 |
#define | MASK_VDIVUVV 0xfc00707f |
#define | MATCH_VDIVUVX 0x80006057 |
#define | MASK_VDIVUVX 0xfc00707f |
#define | MATCH_VREMVV 0x8c002057 |
#define | MASK_VREMVV 0xfc00707f |
#define | MATCH_VREMVX 0x8c006057 |
#define | MASK_VREMVX 0xfc00707f |
#define | MATCH_VREMUVV 0x88002057 |
#define | MASK_VREMUVV 0xfc00707f |
#define | MATCH_VREMUVX 0x88006057 |
#define | MASK_VREMUVX 0xfc00707f |
#define | MATCH_VMERGEVVM 0x5c000057 |
#define | MASK_VMERGEVVM 0xfe00707f |
#define | MATCH_VMERGEVXM 0x5c004057 |
#define | MASK_VMERGEVXM 0xfe00707f |
#define | MATCH_VMERGEVIM 0x5c003057 |
#define | MASK_VMERGEVIM 0xfe00707f |
#define | MATCH_VMVVV 0x5e000057 |
#define | MASK_VMVVV 0xfff0707f |
#define | MATCH_VMVVX 0x5e004057 |
#define | MASK_VMVVX 0xfff0707f |
#define | MATCH_VMVVI 0x5e003057 |
#define | MASK_VMVVI 0xfff0707f |
#define | MATCH_VSADDUVV 0x80000057 |
#define | MASK_VSADDUVV 0xfc00707f |
#define | MATCH_VSADDUVX 0x80004057 |
#define | MASK_VSADDUVX 0xfc00707f |
#define | MATCH_VSADDUVI 0x80003057 |
#define | MASK_VSADDUVI 0xfc00707f |
#define | MATCH_VSADDVV 0x84000057 |
#define | MASK_VSADDVV 0xfc00707f |
#define | MATCH_VSADDVX 0x84004057 |
#define | MASK_VSADDVX 0xfc00707f |
#define | MATCH_VSADDVI 0x84003057 |
#define | MASK_VSADDVI 0xfc00707f |
#define | MATCH_VSSUBUVV 0x88000057 |
#define | MASK_VSSUBUVV 0xfc00707f |
#define | MATCH_VSSUBUVX 0x88004057 |
#define | MASK_VSSUBUVX 0xfc00707f |
#define | MATCH_VSSUBVV 0x8c000057 |
#define | MASK_VSSUBVV 0xfc00707f |
#define | MATCH_VSSUBVX 0x8c004057 |
#define | MASK_VSSUBVX 0xfc00707f |
#define | MATCH_VAADDUVV 0x20002057 |
#define | MASK_VAADDUVV 0xfc00707f |
#define | MATCH_VAADDUVX 0x20006057 |
#define | MASK_VAADDUVX 0xfc00707f |
#define | MATCH_VAADDVV 0x24002057 |
#define | MASK_VAADDVV 0xfc00707f |
#define | MATCH_VAADDVX 0x24006057 |
#define | MASK_VAADDVX 0xfc00707f |
#define | MATCH_VASUBUVV 0x28002057 |
#define | MASK_VASUBUVV 0xfc00707f |
#define | MATCH_VASUBUVX 0x28006057 |
#define | MASK_VASUBUVX 0xfc00707f |
#define | MATCH_VASUBVV 0x2c002057 |
#define | MASK_VASUBVV 0xfc00707f |
#define | MATCH_VASUBVX 0x2c006057 |
#define | MASK_VASUBVX 0xfc00707f |
#define | MATCH_VSMULVV 0x9c000057 |
#define | MASK_VSMULVV 0xfc00707f |
#define | MATCH_VSMULVX 0x9c004057 |
#define | MASK_VSMULVX 0xfc00707f |
#define | MATCH_VSSRLVV 0xa8000057 |
#define | MASK_VSSRLVV 0xfc00707f |
#define | MATCH_VSSRLVX 0xa8004057 |
#define | MASK_VSSRLVX 0xfc00707f |
#define | MATCH_VSSRLVI 0xa8003057 |
#define | MASK_VSSRLVI 0xfc00707f |
#define | MATCH_VSSRAVV 0xac000057 |
#define | MASK_VSSRAVV 0xfc00707f |
#define | MATCH_VSSRAVX 0xac004057 |
#define | MASK_VSSRAVX 0xfc00707f |
#define | MATCH_VSSRAVI 0xac003057 |
#define | MASK_VSSRAVI 0xfc00707f |
#define | MATCH_VNCLIPUWV 0xb8000057 |
#define | MASK_VNCLIPUWV 0xfc00707f |
#define | MATCH_VNCLIPUWX 0xb8004057 |
#define | MASK_VNCLIPUWX 0xfc00707f |
#define | MATCH_VNCLIPUWI 0xb8003057 |
#define | MASK_VNCLIPUWI 0xfc00707f |
#define | MATCH_VNCLIPWV 0xbc000057 |
#define | MASK_VNCLIPWV 0xfc00707f |
#define | MATCH_VNCLIPWX 0xbc004057 |
#define | MASK_VNCLIPWX 0xfc00707f |
#define | MATCH_VNCLIPWI 0xbc003057 |
#define | MASK_VNCLIPWI 0xfc00707f |
#define | MATCH_VFADDVV 0x00001057 |
#define | MASK_VFADDVV 0xfc00707f |
#define | MATCH_VFADDVF 0x00005057 |
#define | MASK_VFADDVF 0xfc00707f |
#define | MATCH_VFSUBVV 0x08001057 |
#define | MASK_VFSUBVV 0xfc00707f |
#define | MATCH_VFSUBVF 0x08005057 |
#define | MASK_VFSUBVF 0xfc00707f |
#define | MATCH_VFRSUBVF 0x9c005057 |
#define | MASK_VFRSUBVF 0xfc00707f |
#define | MATCH_VFWADDVV 0xc0001057 |
#define | MASK_VFWADDVV 0xfc00707f |
#define | MATCH_VFWADDVF 0xc0005057 |
#define | MASK_VFWADDVF 0xfc00707f |
#define | MATCH_VFWSUBVV 0xc8001057 |
#define | MASK_VFWSUBVV 0xfc00707f |
#define | MATCH_VFWSUBVF 0xc8005057 |
#define | MASK_VFWSUBVF 0xfc00707f |
#define | MATCH_VFWADDWV 0xd0001057 |
#define | MASK_VFWADDWV 0xfc00707f |
#define | MATCH_VFWADDWF 0xd0005057 |
#define | MASK_VFWADDWF 0xfc00707f |
#define | MATCH_VFWSUBWV 0xd8001057 |
#define | MASK_VFWSUBWV 0xfc00707f |
#define | MATCH_VFWSUBWF 0xd8005057 |
#define | MASK_VFWSUBWF 0xfc00707f |
#define | MATCH_VFMULVV 0x90001057 |
#define | MASK_VFMULVV 0xfc00707f |
#define | MATCH_VFMULVF 0x90005057 |
#define | MASK_VFMULVF 0xfc00707f |
#define | MATCH_VFDIVVV 0x80001057 |
#define | MASK_VFDIVVV 0xfc00707f |
#define | MATCH_VFDIVVF 0x80005057 |
#define | MASK_VFDIVVF 0xfc00707f |
#define | MATCH_VFRDIVVF 0x84005057 |
#define | MASK_VFRDIVVF 0xfc00707f |
#define | MATCH_VFWMULVV 0xe0001057 |
#define | MASK_VFWMULVV 0xfc00707f |
#define | MATCH_VFWMULVF 0xe0005057 |
#define | MASK_VFWMULVF 0xfc00707f |
#define | MATCH_VFMADDVV 0xa0001057 |
#define | MASK_VFMADDVV 0xfc00707f |
#define | MATCH_VFMADDVF 0xa0005057 |
#define | MASK_VFMADDVF 0xfc00707f |
#define | MATCH_VFNMADDVV 0xa4001057 |
#define | MASK_VFNMADDVV 0xfc00707f |
#define | MATCH_VFNMADDVF 0xa4005057 |
#define | MASK_VFNMADDVF 0xfc00707f |
#define | MATCH_VFMSUBVV 0xa8001057 |
#define | MASK_VFMSUBVV 0xfc00707f |
#define | MATCH_VFMSUBVF 0xa8005057 |
#define | MASK_VFMSUBVF 0xfc00707f |
#define | MATCH_VFNMSUBVV 0xac001057 |
#define | MASK_VFNMSUBVV 0xfc00707f |
#define | MATCH_VFNMSUBVF 0xac005057 |
#define | MASK_VFNMSUBVF 0xfc00707f |
#define | MATCH_VFMACCVV 0xb0001057 |
#define | MASK_VFMACCVV 0xfc00707f |
#define | MATCH_VFMACCVF 0xb0005057 |
#define | MASK_VFMACCVF 0xfc00707f |
#define | MATCH_VFNMACCVV 0xb4001057 |
#define | MASK_VFNMACCVV 0xfc00707f |
#define | MATCH_VFNMACCVF 0xb4005057 |
#define | MASK_VFNMACCVF 0xfc00707f |
#define | MATCH_VFMSACVV 0xb8001057 |
#define | MASK_VFMSACVV 0xfc00707f |
#define | MATCH_VFMSACVF 0xb8005057 |
#define | MASK_VFMSACVF 0xfc00707f |
#define | MATCH_VFNMSACVV 0xbc001057 |
#define | MASK_VFNMSACVV 0xfc00707f |
#define | MATCH_VFNMSACVF 0xbc005057 |
#define | MASK_VFNMSACVF 0xfc00707f |
#define | MATCH_VFWMACCVV 0xf0001057 |
#define | MASK_VFWMACCVV 0xfc00707f |
#define | MATCH_VFWMACCVF 0xf0005057 |
#define | MASK_VFWMACCVF 0xfc00707f |
#define | MATCH_VFWNMACCVV 0xf4001057 |
#define | MASK_VFWNMACCVV 0xfc00707f |
#define | MATCH_VFWNMACCVF 0xf4005057 |
#define | MASK_VFWNMACCVF 0xfc00707f |
#define | MATCH_VFWMSACVV 0xf8001057 |
#define | MASK_VFWMSACVV 0xfc00707f |
#define | MATCH_VFWMSACVF 0xf8005057 |
#define | MASK_VFWMSACVF 0xfc00707f |
#define | MATCH_VFWNMSACVV 0xfc001057 |
#define | MASK_VFWNMSACVV 0xfc00707f |
#define | MATCH_VFWNMSACVF 0xfc005057 |
#define | MASK_VFWNMSACVF 0xfc00707f |
#define | MATCH_VFSQRTV 0x4c001057 |
#define | MASK_VFSQRTV 0xfc0ff07f |
#define | MATCH_VFRSQRT7V 0x4c021057 |
#define | MASK_VFRSQRT7V 0xfc0ff07f |
#define | MATCH_VFREC7V 0x4c029057 |
#define | MASK_VFREC7V 0xfc0ff07f |
#define | MATCH_VFCLASSV 0x4c081057 |
#define | MASK_VFCLASSV 0xfc0ff07f |
#define | MATCH_VFMINVV 0x10001057 |
#define | MASK_VFMINVV 0xfc00707f |
#define | MATCH_VFMINVF 0x10005057 |
#define | MASK_VFMINVF 0xfc00707f |
#define | MATCH_VFMAXVV 0x18001057 |
#define | MASK_VFMAXVV 0xfc00707f |
#define | MATCH_VFMAXVF 0x18005057 |
#define | MASK_VFMAXVF 0xfc00707f |
#define | MATCH_VFSGNJVV 0x20001057 |
#define | MASK_VFSGNJVV 0xfc00707f |
#define | MATCH_VFSGNJVF 0x20005057 |
#define | MASK_VFSGNJVF 0xfc00707f |
#define | MATCH_VFSGNJNVV 0x24001057 |
#define | MASK_VFSGNJNVV 0xfc00707f |
#define | MATCH_VFSGNJNVF 0x24005057 |
#define | MASK_VFSGNJNVF 0xfc00707f |
#define | MATCH_VFSGNJXVV 0x28001057 |
#define | MASK_VFSGNJXVV 0xfc00707f |
#define | MATCH_VFSGNJXVF 0x28005057 |
#define | MASK_VFSGNJXVF 0xfc00707f |
#define | MATCH_VMFEQVV 0x60001057 |
#define | MASK_VMFEQVV 0xfc00707f |
#define | MATCH_VMFEQVF 0x60005057 |
#define | MASK_VMFEQVF 0xfc00707f |
#define | MATCH_VMFNEVV 0x70001057 |
#define | MASK_VMFNEVV 0xfc00707f |
#define | MATCH_VMFNEVF 0x70005057 |
#define | MASK_VMFNEVF 0xfc00707f |
#define | MATCH_VMFLTVV 0x6c001057 |
#define | MASK_VMFLTVV 0xfc00707f |
#define | MATCH_VMFLTVF 0x6c005057 |
#define | MASK_VMFLTVF 0xfc00707f |
#define | MATCH_VMFLEVV 0x64001057 |
#define | MASK_VMFLEVV 0xfc00707f |
#define | MATCH_VMFLEVF 0x64005057 |
#define | MASK_VMFLEVF 0xfc00707f |
#define | MATCH_VMFGTVF 0x74005057 |
#define | MASK_VMFGTVF 0xfc00707f |
#define | MATCH_VMFGEVF 0x7c005057 |
#define | MASK_VMFGEVF 0xfc00707f |
#define | MATCH_VFMERGEVFM 0x5c005057 |
#define | MASK_VFMERGEVFM 0xfe00707f |
#define | MATCH_VFMVVF 0x5e005057 |
#define | MASK_VFMVVF 0xfff0707f |
#define | MATCH_VFCVTXUFV 0x48001057 |
#define | MASK_VFCVTXUFV 0xfc0ff07f |
#define | MATCH_VFCVTXFV 0x48009057 |
#define | MASK_VFCVTXFV 0xfc0ff07f |
#define | MATCH_VFCVTFXUV 0x48011057 |
#define | MASK_VFCVTFXUV 0xfc0ff07f |
#define | MATCH_VFCVTFXV 0x48019057 |
#define | MASK_VFCVTFXV 0xfc0ff07f |
#define | MATCH_VFCVTRTZXUFV 0x48031057 |
#define | MASK_VFCVTRTZXUFV 0xfc0ff07f |
#define | MATCH_VFCVTRTZXFV 0x48039057 |
#define | MASK_VFCVTRTZXFV 0xfc0ff07f |
#define | MATCH_VFWCVTXUFV 0x48041057 |
#define | MASK_VFWCVTXUFV 0xfc0ff07f |
#define | MATCH_VFWCVTXFV 0x48049057 |
#define | MASK_VFWCVTXFV 0xfc0ff07f |
#define | MATCH_VFWCVTFXUV 0x48051057 |
#define | MASK_VFWCVTFXUV 0xfc0ff07f |
#define | MATCH_VFWCVTFXV 0x48059057 |
#define | MASK_VFWCVTFXV 0xfc0ff07f |
#define | MATCH_VFWCVTFFV 0x48061057 |
#define | MASK_VFWCVTFFV 0xfc0ff07f |
#define | MATCH_VFWCVTRTZXUFV 0x48071057 |
#define | MASK_VFWCVTRTZXUFV 0xfc0ff07f |
#define | MATCH_VFWCVTRTZXFV 0x48079057 |
#define | MASK_VFWCVTRTZXFV 0xfc0ff07f |
#define | MATCH_VFNCVTXUFW 0x48081057 |
#define | MASK_VFNCVTXUFW 0xfc0ff07f |
#define | MATCH_VFNCVTXFW 0x48089057 |
#define | MASK_VFNCVTXFW 0xfc0ff07f |
#define | MATCH_VFNCVTFXUW 0x48091057 |
#define | MASK_VFNCVTFXUW 0xfc0ff07f |
#define | MATCH_VFNCVTFXW 0x48099057 |
#define | MASK_VFNCVTFXW 0xfc0ff07f |
#define | MATCH_VFNCVTFFW 0x480a1057 |
#define | MASK_VFNCVTFFW 0xfc0ff07f |
#define | MATCH_VFNCVTRODFFW 0x480a9057 |
#define | MASK_VFNCVTRODFFW 0xfc0ff07f |
#define | MATCH_VFNCVTRTZXUFW 0x480b1057 |
#define | MASK_VFNCVTRTZXUFW 0xfc0ff07f |
#define | MATCH_VFNCVTRTZXFW 0x480b9057 |
#define | MASK_VFNCVTRTZXFW 0xfc0ff07f |
#define | MATCH_VREDSUMVS 0x00002057 |
#define | MASK_VREDSUMVS 0xfc00707f |
#define | MATCH_VREDMAXVS 0x1c002057 |
#define | MASK_VREDMAXVS 0xfc00707f |
#define | MATCH_VREDMAXUVS 0x18002057 |
#define | MASK_VREDMAXUVS 0xfc00707f |
#define | MATCH_VREDMINVS 0x14002057 |
#define | MASK_VREDMINVS 0xfc00707f |
#define | MATCH_VREDMINUVS 0x10002057 |
#define | MASK_VREDMINUVS 0xfc00707f |
#define | MATCH_VREDANDVS 0x04002057 |
#define | MASK_VREDANDVS 0xfc00707f |
#define | MATCH_VREDORVS 0x08002057 |
#define | MASK_VREDORVS 0xfc00707f |
#define | MATCH_VREDXORVS 0x0c002057 |
#define | MASK_VREDXORVS 0xfc00707f |
#define | MATCH_VWREDSUMUVS 0xc0000057 |
#define | MASK_VWREDSUMUVS 0xfc00707f |
#define | MATCH_VWREDSUMVS 0xc4000057 |
#define | MASK_VWREDSUMVS 0xfc00707f |
#define | MATCH_VFREDOSUMVS 0x0c001057 |
#define | MASK_VFREDOSUMVS 0xfc00707f |
#define | MATCH_VFREDUSUMVS 0x04001057 |
#define | MASK_VFREDUSUMVS 0xfc00707f |
#define | MATCH_VFREDMAXVS 0x1c001057 |
#define | MASK_VFREDMAXVS 0xfc00707f |
#define | MATCH_VFREDMINVS 0x14001057 |
#define | MASK_VFREDMINVS 0xfc00707f |
#define | MATCH_VFWREDOSUMVS 0xcc001057 |
#define | MASK_VFWREDOSUMVS 0xfc00707f |
#define | MATCH_VFWREDUSUMVS 0xc4001057 |
#define | MASK_VFWREDUSUMVS 0xfc00707f |
#define | MATCH_VMANDMM 0x66002057 |
#define | MASK_VMANDMM 0xfe00707f |
#define | MATCH_VMNANDMM 0x76002057 |
#define | MASK_VMNANDMM 0xfe00707f |
#define | MATCH_VMANDNMM 0x62002057 |
#define | MASK_VMANDNMM 0xfe00707f |
#define | MATCH_VMXORMM 0x6e002057 |
#define | MASK_VMXORMM 0xfe00707f |
#define | MATCH_VMORMM 0x6a002057 |
#define | MASK_VMORMM 0xfe00707f |
#define | MATCH_VMNORMM 0x7a002057 |
#define | MASK_VMNORMM 0xfe00707f |
#define | MATCH_VMORNMM 0x72002057 |
#define | MASK_VMORNMM 0xfe00707f |
#define | MATCH_VMXNORMM 0x7e002057 |
#define | MASK_VMXNORMM 0xfe00707f |
#define | MATCH_VCPOPM 0x40082057 |
#define | MASK_VCPOPM 0xfc0ff07f |
#define | MATCH_VFIRSTM 0x4008a057 |
#define | MASK_VFIRSTM 0xfc0ff07f |
#define | MATCH_VMSBFM 0x5000a057 |
#define | MASK_VMSBFM 0xfc0ff07f |
#define | MATCH_VMSIFM 0x5001a057 |
#define | MASK_VMSIFM 0xfc0ff07f |
#define | MATCH_VMSOFM 0x50012057 |
#define | MASK_VMSOFM 0xfc0ff07f |
#define | MATCH_VIOTAM 0x50082057 |
#define | MASK_VIOTAM 0xfc0ff07f |
#define | MATCH_VIDV 0x5008a057 |
#define | MASK_VIDV 0xfdfff07f |
#define | MATCH_VMVXS 0x42002057 |
#define | MASK_VMVXS 0xfe0ff07f |
#define | MATCH_VMVSX 0x42006057 |
#define | MASK_VMVSX 0xfff0707f |
#define | MATCH_VFMVFS 0x42001057 |
#define | MASK_VFMVFS 0xfe0ff07f |
#define | MATCH_VFMVSF 0x42005057 |
#define | MASK_VFMVSF 0xfff0707f |
#define | MATCH_VSLIDEUPVX 0x38004057 |
#define | MASK_VSLIDEUPVX 0xfc00707f |
#define | MATCH_VSLIDEUPVI 0x38003057 |
#define | MASK_VSLIDEUPVI 0xfc00707f |
#define | MATCH_VSLIDEDOWNVX 0x3c004057 |
#define | MASK_VSLIDEDOWNVX 0xfc00707f |
#define | MATCH_VSLIDEDOWNVI 0x3c003057 |
#define | MASK_VSLIDEDOWNVI 0xfc00707f |
#define | MATCH_VSLIDE1UPVX 0x38006057 |
#define | MASK_VSLIDE1UPVX 0xfc00707f |
#define | MATCH_VSLIDE1DOWNVX 0x3c006057 |
#define | MASK_VSLIDE1DOWNVX 0xfc00707f |
#define | MATCH_VFSLIDE1UPVF 0x38005057 |
#define | MASK_VFSLIDE1UPVF 0xfc00707f |
#define | MATCH_VFSLIDE1DOWNVF 0x3c005057 |
#define | MASK_VFSLIDE1DOWNVF 0xfc00707f |
#define | MATCH_VRGATHERVV 0x30000057 |
#define | MASK_VRGATHERVV 0xfc00707f |
#define | MATCH_VRGATHERVX 0x30004057 |
#define | MASK_VRGATHERVX 0xfc00707f |
#define | MATCH_VRGATHERVI 0x30003057 |
#define | MASK_VRGATHERVI 0xfc00707f |
#define | MATCH_VRGATHEREI16VV 0x38000057 |
#define | MASK_VRGATHEREI16VV 0xfc00707f |
#define | MATCH_VCOMPRESSVM 0x5e002057 |
#define | MASK_VCOMPRESSVM 0xfe00707f |
#define | MATCH_VMV1RV 0x9e003057 |
#define | MASK_VMV1RV 0xfe0ff07f |
#define | MATCH_VMV2RV 0x9e00b057 |
#define | MASK_VMV2RV 0xfe0ff07f |
#define | MATCH_VMV4RV 0x9e01b057 |
#define | MASK_VMV4RV 0xfe0ff07f |
#define | MATCH_VMV8RV 0x9e03b057 |
#define | MASK_VMV8RV 0xfe0ff07f |
#define | MATCH_VDOTVV 0xe4000057 |
#define | MASK_VDOTVV 0xfc00707f |
#define | MATCH_VDOTUVV 0xe0000057 |
#define | MASK_VDOTUVV 0xfc00707f |
#define | MATCH_VFDOTVV 0xe4001057 |
#define | MASK_VFDOTVV 0xfc00707f |
#define | MATCH_VANDN_VV 0x4000057 |
#define | MASK_VANDN_VV 0xfc00707f |
#define | MATCH_VANDN_VX 0x4004057 |
#define | MASK_VANDN_VX 0xfc00707f |
#define | MATCH_VBREV8_V 0x48042057 |
#define | MASK_VBREV8_V 0xfc0ff07f |
#define | MATCH_VBREV_V 0x48052057 |
#define | MASK_VBREV_V 0xfc0ff07f |
#define | MATCH_VCLZ_V 0x48062057 |
#define | MASK_VCLZ_V 0xfc0ff07f |
#define | MATCH_VCPOP_V 0x48072057 |
#define | MASK_VCPOP_V 0xfc0ff07f |
#define | MATCH_VCTZ_V 0x4806a057 |
#define | MASK_VCTZ_V 0xfc0ff07f |
#define | MATCH_VREV8_V 0x4804a057 |
#define | MASK_VREV8_V 0xfc0ff07f |
#define | MATCH_VROL_VV 0x54000057 |
#define | MASK_VROL_VV 0xfc00707f |
#define | MATCH_VROL_VX 0x54004057 |
#define | MASK_VROL_VX 0xfc00707f |
#define | MATCH_VROR_VI 0x50003057 |
#define | MASK_VROR_VI 0xf800707f |
#define | MATCH_VROR_VV 0x50000057 |
#define | MASK_VROR_VV 0xfc00707f |
#define | MATCH_VROR_VX 0x50004057 |
#define | MASK_VROR_VX 0xfc00707f |
#define | MATCH_VWSLL_VI 0xd4003057 |
#define | MASK_VWSLL_VI 0xfc00707f |
#define | MATCH_VWSLL_VV 0xd4000057 |
#define | MASK_VWSLL_VV 0xfc00707f |
#define | MATCH_VWSLL_VX 0xd4004057 |
#define | MASK_VWSLL_VX 0xfc00707f |
#define | MATCH_VCLMUL_VV 0x30002057 |
#define | MASK_VCLMUL_VV 0xfc00707f |
#define | MATCH_VCLMUL_VX 0x30006057 |
#define | MASK_VCLMUL_VX 0xfc00707f |
#define | MATCH_VCLMULH_VV 0x34002057 |
#define | MASK_VCLMULH_VV 0xfc00707f |
#define | MATCH_VCLMULH_VX 0x34006057 |
#define | MASK_VCLMULH_VX 0xfc00707f |
#define | MATCH_VGHSH_VV 0xb2002077 |
#define | MASK_VGHSH_VV 0xfe00707f |
#define | MATCH_VGMUL_VV 0xa208a077 |
#define | MASK_VGMUL_VV 0xfe0ff07f |
#define | MATCH_VAESDF_VS 0xa600a077 |
#define | MASK_VAESDF_VS 0xfe0ff07f |
#define | MATCH_VAESDF_VV 0xa200a077 |
#define | MASK_VAESDF_VV 0xfe0ff07f |
#define | MATCH_VAESDM_VS 0xa6002077 |
#define | MASK_VAESDM_VS 0xfe0ff07f |
#define | MATCH_VAESDM_VV 0xa2002077 |
#define | MASK_VAESDM_VV 0xfe0ff07f |
#define | MATCH_VAESEF_VS 0xa601a077 |
#define | MASK_VAESEF_VS 0xfe0ff07f |
#define | MATCH_VAESEF_VV 0xa201a077 |
#define | MASK_VAESEF_VV 0xfe0ff07f |
#define | MATCH_VAESEM_VS 0xa6012077 |
#define | MASK_VAESEM_VS 0xfe0ff07f |
#define | MATCH_VAESEM_VV 0xa2012077 |
#define | MASK_VAESEM_VV 0xfe0ff07f |
#define | MATCH_VAESKF1_VI 0x8a002077 |
#define | MASK_VAESKF1_VI 0xfe00707f |
#define | MATCH_VAESKF2_VI 0xaa002077 |
#define | MASK_VAESKF2_VI 0xfe00707f |
#define | MATCH_VAESZ_VS 0xa603a077 |
#define | MASK_VAESZ_VS 0xfe0ff07f |
#define | MATCH_VSHA2CH_VV 0xba002077 |
#define | MASK_VSHA2CH_VV 0xfe00707f |
#define | MATCH_VSHA2CL_VV 0xbe002077 |
#define | MASK_VSHA2CL_VV 0xfe00707f |
#define | MATCH_VSHA2MS_VV 0xb6002077 |
#define | MASK_VSHA2MS_VV 0xfe00707f |
#define | MATCH_VSM4K_VI 0x86002077 |
#define | MASK_VSM4K_VI 0xfe00707f |
#define | MATCH_VSM4R_VS 0xa6082077 |
#define | MASK_VSM4R_VS 0xfe0ff07f |
#define | MATCH_VSM4R_VV 0xa2082077 |
#define | MASK_VSM4R_VV 0xfe0ff07f |
#define | MATCH_VSM3C_VI 0xae002077 |
#define | MASK_VSM3C_VI 0xfe00707f |
#define | MATCH_VSM3ME_VV 0x82002077 |
#define | MASK_VSM3ME_VV 0xfe00707f |
#define | MATCH_C_LBU 0x8000 |
#define | MASK_C_LBU 0xfc03 |
#define | MATCH_C_LHU 0x8400 |
#define | MASK_C_LHU 0xfc43 |
#define | MATCH_C_LH 0x8440 |
#define | MASK_C_LH 0xfc43 |
#define | MATCH_C_SB 0x8800 |
#define | MASK_C_SB 0xfc03 |
#define | MATCH_C_SH 0x8c00 |
#define | MASK_C_SH 0xfc43 |
#define | MATCH_C_ZEXT_B 0x9c61 |
#define | MASK_C_ZEXT_B 0xfc7f |
#define | MATCH_C_SEXT_B 0x9c65 |
#define | MASK_C_SEXT_B 0xfc7f |
#define | MATCH_C_ZEXT_H 0x9c69 |
#define | MASK_C_ZEXT_H 0xfc7f |
#define | MATCH_C_SEXT_H 0x9c6d |
#define | MASK_C_SEXT_H 0xfc7f |
#define | MATCH_C_ZEXT_W 0x9c71 |
#define | MASK_C_ZEXT_W 0xfc7f |
#define | MATCH_C_NOT 0x9c75 |
#define | MASK_C_NOT 0xfc7f |
#define | MATCH_C_MUL 0x9c41 |
#define | MASK_C_MUL 0xfc63 |
#define | MATCH_SINVAL_VMA 0x16000073 |
#define | MASK_SINVAL_VMA 0xfe007fff |
#define | MATCH_SFENCE_W_INVAL 0x18000073 |
#define | MASK_SFENCE_W_INVAL 0xffffffff |
#define | MATCH_SFENCE_INVAL_IR 0x18100073 |
#define | MASK_SFENCE_INVAL_IR 0xffffffff |
#define | MATCH_HINVAL_VVMA 0x26000073 |
#define | MASK_HINVAL_VVMA 0xfe007fff |
#define | MATCH_HINVAL_GVMA 0x66000073 |
#define | MASK_HINVAL_GVMA 0xfe007fff |
#define | MATCH_HFENCE_VVMA 0x22000073 |
#define | MASK_HFENCE_VVMA 0xfe007fff |
#define | MATCH_HFENCE_GVMA 0x62000073 |
#define | MASK_HFENCE_GVMA 0xfe007fff |
#define | MATCH_HLV_B 0x60004073 |
#define | MASK_HLV_B 0xfff0707f |
#define | MATCH_HLV_H 0x64004073 |
#define | MASK_HLV_H 0xfff0707f |
#define | MATCH_HLV_W 0x68004073 |
#define | MASK_HLV_W 0xfff0707f |
#define | MATCH_HLV_D 0x6c004073 |
#define | MASK_HLV_D 0xfff0707f |
#define | MATCH_HLV_BU 0x60104073 |
#define | MASK_HLV_BU 0xfff0707f |
#define | MATCH_HLV_HU 0x64104073 |
#define | MASK_HLV_HU 0xfff0707f |
#define | MATCH_HLV_WU 0x68104073 |
#define | MASK_HLV_WU 0xfff0707f |
#define | MATCH_HLVX_HU 0x64304073 |
#define | MASK_HLVX_HU 0xfff0707f |
#define | MATCH_HLVX_WU 0x68304073 |
#define | MASK_HLVX_WU 0xfff0707f |
#define | MATCH_HSV_B 0x62004073 |
#define | MASK_HSV_B 0xfe007fff |
#define | MATCH_HSV_H 0x66004073 |
#define | MASK_HSV_H 0xfe007fff |
#define | MATCH_HSV_W 0x6a004073 |
#define | MASK_HSV_W 0xfe007fff |
#define | MATCH_HSV_D 0x6e004073 |
#define | MASK_HSV_D 0xfe007fff |
#define | MATCH_PREFETCH_I 0x6013 |
#define | MASK_PREFETCH_I 0x1f07fff |
#define | MATCH_PREFETCH_R 0x106013 |
#define | MASK_PREFETCH_R 0x1f07fff |
#define | MATCH_PREFETCH_W 0x306013 |
#define | MASK_PREFETCH_W 0x1f07fff |
#define | MATCH_CBO_CLEAN 0x10200f |
#define | MASK_CBO_CLEAN 0xfff07fff |
#define | MATCH_CBO_FLUSH 0x20200f |
#define | MASK_CBO_FLUSH 0xfff07fff |
#define | MATCH_CBO_INVAL 0x200f |
#define | MASK_CBO_INVAL 0xfff07fff |
#define | MATCH_CBO_ZERO 0x40200f |
#define | MASK_CBO_ZERO 0xfff07fff |
#define | MATCH_CZERO_EQZ 0xe005033 |
#define | MASK_CZERO_EQZ 0xfe00707f |
#define | MATCH_CZERO_NEZ 0xe007033 |
#define | MASK_CZERO_NEZ 0xfe00707f |
#define | MATCH_NTL_P1 0x200033 |
#define | MASK_NTL_P1 0xffffffff |
#define | MATCH_NTL_PALL 0x300033 |
#define | MASK_NTL_PALL 0xffffffff |
#define | MATCH_NTL_S1 0x400033 |
#define | MASK_NTL_S1 0xffffffff |
#define | MATCH_NTL_ALL 0x500033 |
#define | MASK_NTL_ALL 0xffffffff |
#define | MATCH_C_NTL_P1 0x900a |
#define | MASK_C_NTL_P1 0xffff |
#define | MATCH_C_NTL_PALL 0x900e |
#define | MASK_C_NTL_PALL 0xffff |
#define | MATCH_C_NTL_S1 0x9012 |
#define | MASK_C_NTL_S1 0xffff |
#define | MATCH_C_NTL_ALL 0x9016 |
#define | MASK_C_NTL_ALL 0xffff |
#define | MATCH_WRS_NTO 0x00d00073 |
#define | MASK_WRS_NTO 0xffffffff |
#define | MATCH_WRS_STO 0x01d00073 |
#define | MASK_WRS_STO 0xffffffff |
#define | MATCH_TH_ADDSL 0x0000100b |
#define | MASK_TH_ADDSL 0xf800707f |
#define | MATCH_TH_SRRI 0x1000100b |
#define | MASK_TH_SRRI 0xfc00707f |
#define | MATCH_TH_SRRIW 0x1400100b |
#define | MASK_TH_SRRIW 0xfe00707f |
#define | MATCH_TH_EXT 0x0000200b |
#define | MASK_TH_EXT 0x0000707f |
#define | MATCH_TH_EXTU 0x0000300b |
#define | MASK_TH_EXTU 0x0000707f |
#define | MATCH_TH_FF0 0x8400100b |
#define | MASK_TH_FF0 0xfff0707f |
#define | MATCH_TH_FF1 0x8600100b |
#define | MASK_TH_FF1 0xfff0707f |
#define | MATCH_TH_REV 0x8200100b |
#define | MASK_TH_REV 0xfff0707f |
#define | MATCH_TH_REVW 0x9000100b |
#define | MASK_TH_REVW 0xfff0707f |
#define | MATCH_TH_TSTNBZ 0x8000100b |
#define | MASK_TH_TSTNBZ 0xfff0707f |
#define | MATCH_TH_TST 0x8800100b |
#define | MASK_TH_TST 0xfc00707f |
#define | MATCH_TH_DCACHE_CALL 0x0010000b |
#define | MASK_TH_DCACHE_CALL 0xffffffff |
#define | MATCH_TH_DCACHE_CIALL 0x0030000b |
#define | MASK_TH_DCACHE_CIALL 0xffffffff |
#define | MATCH_TH_DCACHE_IALL 0x0020000b |
#define | MASK_TH_DCACHE_IALL 0xffffffff |
#define | MATCH_TH_DCACHE_CPA 0x0290000b |
#define | MASK_TH_DCACHE_CPA 0xfff07fff |
#define | MATCH_TH_DCACHE_CIPA 0x02b0000b |
#define | MASK_TH_DCACHE_CIPA 0xfff07fff |
#define | MATCH_TH_DCACHE_IPA 0x02a0000b |
#define | MASK_TH_DCACHE_IPA 0xfff07fff |
#define | MATCH_TH_DCACHE_CVA 0x0250000b |
#define | MASK_TH_DCACHE_CVA 0xfff07fff |
#define | MATCH_TH_DCACHE_CIVA 0x0270000b |
#define | MASK_TH_DCACHE_CIVA 0xfff07fff |
#define | MATCH_TH_DCACHE_IVA 0x0260000b |
#define | MASK_TH_DCACHE_IVA 0xfff07fff |
#define | MATCH_TH_DCACHE_CSW 0x0210000b |
#define | MASK_TH_DCACHE_CSW 0xfff07fff |
#define | MATCH_TH_DCACHE_CISW 0x0230000b |
#define | MASK_TH_DCACHE_CISW 0xfff07fff |
#define | MATCH_TH_DCACHE_ISW 0x0220000b |
#define | MASK_TH_DCACHE_ISW 0xfff07fff |
#define | MATCH_TH_DCACHE_CPAL1 0x0280000b |
#define | MASK_TH_DCACHE_CPAL1 0xfff07fff |
#define | MATCH_TH_DCACHE_CVAL1 0x0240000b |
#define | MASK_TH_DCACHE_CVAL1 0xfff07fff |
#define | MATCH_TH_ICACHE_IALL 0x0100000b |
#define | MASK_TH_ICACHE_IALL 0xffffffff |
#define | MATCH_TH_ICACHE_IALLS 0x0110000b |
#define | MASK_TH_ICACHE_IALLS 0xffffffff |
#define | MATCH_TH_ICACHE_IPA 0x0380000b |
#define | MASK_TH_ICACHE_IPA 0xfff07fff |
#define | MATCH_TH_ICACHE_IVA 0x0300000b |
#define | MASK_TH_ICACHE_IVA 0xfff07fff |
#define | MATCH_TH_L2CACHE_CALL 0x0150000b |
#define | MASK_TH_L2CACHE_CALL 0xffffffff |
#define | MATCH_TH_L2CACHE_CIALL 0x0170000b |
#define | MASK_TH_L2CACHE_CIALL 0xffffffff |
#define | MATCH_TH_L2CACHE_IALL 0x0160000b |
#define | MASK_TH_L2CACHE_IALL 0xffffffff |
#define | MATCH_TH_MVEQZ 0x4000100b |
#define | MASK_TH_MVEQZ 0xfe00707f |
#define | MATCH_TH_MVNEZ 0x4200100b |
#define | MASK_TH_MVNEZ 0xfe00707f |
#define | MATCH_TH_FLRD 0x6000600b |
#define | MASK_TH_FLRD 0xf800707f |
#define | MATCH_TH_FLRW 0x4000600b |
#define | MASK_TH_FLRW 0xf800707f |
#define | MATCH_TH_FLURD 0x7000600b |
#define | MASK_TH_FLURD 0xf800707f |
#define | MATCH_TH_FLURW 0x5000600b |
#define | MASK_TH_FLURW 0xf800707f |
#define | MATCH_TH_FSRD 0x6000700b |
#define | MASK_TH_FSRD 0xf800707f |
#define | MATCH_TH_FSRW 0x4000700b |
#define | MASK_TH_FSRW 0xf800707f |
#define | MATCH_TH_FSURD 0x7000700b |
#define | MASK_TH_FSURD 0xf800707f |
#define | MATCH_TH_FSURW 0x5000700b |
#define | MASK_TH_FSURW 0xf800707f |
#define | MATCH_TH_FMV_HW_X 0x5000100b |
#define | MASK_TH_FMV_HW_X 0xfff0707f |
#define | MATCH_TH_FMV_X_HW 0x6000100b |
#define | MASK_TH_FMV_X_HW 0xfff0707f |
#define | MATCH_TH_IPOP 0x0050000b |
#define | MASK_TH_IPOP 0xffffffff |
#define | MATCH_TH_IPUSH 0x0040000b |
#define | MASK_TH_IPUSH 0xffffffff |
#define | MATCH_TH_MULA 0x2000100b |
#define | MASK_TH_MULA 0xfe00707f |
#define | MATCH_TH_MULAH 0x2800100b |
#define | MASK_TH_MULAH 0xfe00707f |
#define | MATCH_TH_MULAW 0x2400100b |
#define | MASK_TH_MULAW 0xfe00707f |
#define | MATCH_TH_MULS 0x2200100b |
#define | MASK_TH_MULS 0xfe00707f |
#define | MATCH_TH_MULSH 0x2a00100b |
#define | MASK_TH_MULSH 0xfe00707f |
#define | MATCH_TH_MULSW 0x2600100b |
#define | MASK_TH_MULSW 0xfe00707f |
#define | MATCH_TH_LDD 0xf800400b |
#define | MASK_TH_LDD 0xf800707f |
#define | MATCH_TH_LWD 0xe000400b |
#define | MASK_TH_LWD 0xf800707f |
#define | MATCH_TH_LWUD 0xf000400b |
#define | MASK_TH_LWUD 0xf800707f |
#define | MATCH_TH_SDD 0xf800500b |
#define | MASK_TH_SDD 0xf800707f |
#define | MATCH_TH_SWD 0xe000500b |
#define | MASK_TH_SWD 0xf800707f |
#define | MATCH_TH_LDIA 0x7800400b |
#define | MASK_TH_LDIA 0xf800707f |
#define | MATCH_TH_LDIB 0x6800400b |
#define | MASK_TH_LDIB 0xf800707f |
#define | MATCH_TH_LWIA 0x5800400b |
#define | MASK_TH_LWIA 0xf800707f |
#define | MATCH_TH_LWIB 0x4800400b |
#define | MASK_TH_LWIB 0xf800707f |
#define | MATCH_TH_LWUIA 0xd800400b |
#define | MASK_TH_LWUIA 0xf800707f |
#define | MATCH_TH_LWUIB 0xc800400b |
#define | MASK_TH_LWUIB 0xf800707f |
#define | MATCH_TH_LHIA 0x3800400b |
#define | MASK_TH_LHIA 0xf800707f |
#define | MATCH_TH_LHIB 0x2800400b |
#define | MASK_TH_LHIB 0xf800707f |
#define | MATCH_TH_LHUIA 0xb800400b |
#define | MASK_TH_LHUIA 0xf800707f |
#define | MATCH_TH_LHUIB 0xa800400b |
#define | MASK_TH_LHUIB 0xf800707f |
#define | MATCH_TH_LBIA 0x1800400b |
#define | MASK_TH_LBIA 0xf800707f |
#define | MATCH_TH_LBIB 0x0800400b |
#define | MASK_TH_LBIB 0xf800707f |
#define | MATCH_TH_LBUIA 0x9800400b |
#define | MASK_TH_LBUIA 0xf800707f |
#define | MATCH_TH_LBUIB 0x8800400b |
#define | MASK_TH_LBUIB 0xf800707f |
#define | MATCH_TH_SDIA 0x7800500b |
#define | MASK_TH_SDIA 0xf800707f |
#define | MATCH_TH_SDIB 0x6800500b |
#define | MASK_TH_SDIB 0xf800707f |
#define | MATCH_TH_SWIA 0x5800500b |
#define | MASK_TH_SWIA 0xf800707f |
#define | MATCH_TH_SWIB 0x4800500b |
#define | MASK_TH_SWIB 0xf800707f |
#define | MATCH_TH_SHIA 0x3800500b |
#define | MASK_TH_SHIA 0xf800707f |
#define | MATCH_TH_SHIB 0x2800500b |
#define | MASK_TH_SHIB 0xf800707f |
#define | MATCH_TH_SBIA 0x1800500b |
#define | MASK_TH_SBIA 0xf800707f |
#define | MATCH_TH_SBIB 0x0800500b |
#define | MASK_TH_SBIB 0xf800707f |
#define | MATCH_TH_LRD 0x6000400b |
#define | MASK_TH_LRD 0xf800707f |
#define | MATCH_TH_LRW 0x4000400b |
#define | MASK_TH_LRW 0xf800707f |
#define | MATCH_TH_LRWU 0xc000400b |
#define | MASK_TH_LRWU 0xf800707f |
#define | MATCH_TH_LRH 0x2000400b |
#define | MASK_TH_LRH 0xf800707f |
#define | MATCH_TH_LRHU 0xa000400b |
#define | MASK_TH_LRHU 0xf800707f |
#define | MATCH_TH_LRB 0x0000400b |
#define | MASK_TH_LRB 0xf800707f |
#define | MATCH_TH_LRBU 0x8000400b |
#define | MASK_TH_LRBU 0xf800707f |
#define | MATCH_TH_SRD 0x6000500b |
#define | MASK_TH_SRD 0xf800707f |
#define | MATCH_TH_SRW 0x4000500b |
#define | MASK_TH_SRW 0xf800707f |
#define | MATCH_TH_SRH 0x2000500b |
#define | MASK_TH_SRH 0xf800707f |
#define | MATCH_TH_SRB 0x0000500b |
#define | MASK_TH_SRB 0xf800707f |
#define | MATCH_TH_LURD 0x7000400b |
#define | MASK_TH_LURD 0xf800707f |
#define | MATCH_TH_LURW 0x5000400b |
#define | MASK_TH_LURW 0xf800707f |
#define | MATCH_TH_LURWU 0xd000400b |
#define | MASK_TH_LURWU 0xf800707f |
#define | MATCH_TH_LURH 0x3000400b |
#define | MASK_TH_LURH 0xf800707f |
#define | MATCH_TH_LURHU 0xb000400b |
#define | MASK_TH_LURHU 0xf800707f |
#define | MATCH_TH_LURB 0x1000400b |
#define | MASK_TH_LURB 0xf800707f |
#define | MATCH_TH_LURBU 0x9000400b |
#define | MASK_TH_LURBU 0xf800707f |
#define | MATCH_TH_SURD 0x7000500b |
#define | MASK_TH_SURD 0xf800707f |
#define | MATCH_TH_SURW 0x5000500b |
#define | MASK_TH_SURW 0xf800707f |
#define | MATCH_TH_SURH 0x3000500b |
#define | MASK_TH_SURH 0xf800707f |
#define | MATCH_TH_SURB 0x1000500b |
#define | MASK_TH_SURB 0xf800707f |
#define | MATCH_TH_SFENCE_VMAS 0x0400000b |
#define | MASK_TH_SFENCE_VMAS 0xfe007fff |
#define | MATCH_TH_SYNC 0x0180000b |
#define | MASK_TH_SYNC 0xffffffff |
#define | MATCH_TH_SYNC_I 0x01a0000b |
#define | MASK_TH_SYNC_I 0xffffffff |
#define | MATCH_TH_SYNC_IS 0x01b0000b |
#define | MASK_TH_SYNC_IS 0xffffffff |
#define | MATCH_TH_SYNC_S 0x0190000b |
#define | MASK_TH_SYNC_S 0xffffffff |
#define | MATCH_VT_MASKC 0x607b |
#define | MASK_VT_MASKC 0xfe00707f |
#define | MATCH_VT_MASKCN 0x707b |
#define | MASK_VT_MASKCN 0xfe00707f |
#define | CSR_CYCLE 0xc00 |
#define | CSR_TIME 0xc01 |
#define | CSR_INSTRET 0xc02 |
#define | CSR_HPMCOUNTER3 0xc03 |
#define | CSR_HPMCOUNTER4 0xc04 |
#define | CSR_HPMCOUNTER5 0xc05 |
#define | CSR_HPMCOUNTER6 0xc06 |
#define | CSR_HPMCOUNTER7 0xc07 |
#define | CSR_HPMCOUNTER8 0xc08 |
#define | CSR_HPMCOUNTER9 0xc09 |
#define | CSR_HPMCOUNTER10 0xc0a |
#define | CSR_HPMCOUNTER11 0xc0b |
#define | CSR_HPMCOUNTER12 0xc0c |
#define | CSR_HPMCOUNTER13 0xc0d |
#define | CSR_HPMCOUNTER14 0xc0e |
#define | CSR_HPMCOUNTER15 0xc0f |
#define | CSR_HPMCOUNTER16 0xc10 |
#define | CSR_HPMCOUNTER17 0xc11 |
#define | CSR_HPMCOUNTER18 0xc12 |
#define | CSR_HPMCOUNTER19 0xc13 |
#define | CSR_HPMCOUNTER20 0xc14 |
#define | CSR_HPMCOUNTER21 0xc15 |
#define | CSR_HPMCOUNTER22 0xc16 |
#define | CSR_HPMCOUNTER23 0xc17 |
#define | CSR_HPMCOUNTER24 0xc18 |
#define | CSR_HPMCOUNTER25 0xc19 |
#define | CSR_HPMCOUNTER26 0xc1a |
#define | CSR_HPMCOUNTER27 0xc1b |
#define | CSR_HPMCOUNTER28 0xc1c |
#define | CSR_HPMCOUNTER29 0xc1d |
#define | CSR_HPMCOUNTER30 0xc1e |
#define | CSR_HPMCOUNTER31 0xc1f |
#define | CSR_CYCLEH 0xc80 |
#define | CSR_TIMEH 0xc81 |
#define | CSR_INSTRETH 0xc82 |
#define | CSR_HPMCOUNTER3H 0xc83 |
#define | CSR_HPMCOUNTER4H 0xc84 |
#define | CSR_HPMCOUNTER5H 0xc85 |
#define | CSR_HPMCOUNTER6H 0xc86 |
#define | CSR_HPMCOUNTER7H 0xc87 |
#define | CSR_HPMCOUNTER8H 0xc88 |
#define | CSR_HPMCOUNTER9H 0xc89 |
#define | CSR_HPMCOUNTER10H 0xc8a |
#define | CSR_HPMCOUNTER11H 0xc8b |
#define | CSR_HPMCOUNTER12H 0xc8c |
#define | CSR_HPMCOUNTER13H 0xc8d |
#define | CSR_HPMCOUNTER14H 0xc8e |
#define | CSR_HPMCOUNTER15H 0xc8f |
#define | CSR_HPMCOUNTER16H 0xc90 |
#define | CSR_HPMCOUNTER17H 0xc91 |
#define | CSR_HPMCOUNTER18H 0xc92 |
#define | CSR_HPMCOUNTER19H 0xc93 |
#define | CSR_HPMCOUNTER20H 0xc94 |
#define | CSR_HPMCOUNTER21H 0xc95 |
#define | CSR_HPMCOUNTER22H 0xc96 |
#define | CSR_HPMCOUNTER23H 0xc97 |
#define | CSR_HPMCOUNTER24H 0xc98 |
#define | CSR_HPMCOUNTER25H 0xc99 |
#define | CSR_HPMCOUNTER26H 0xc9a |
#define | CSR_HPMCOUNTER27H 0xc9b |
#define | CSR_HPMCOUNTER28H 0xc9c |
#define | CSR_HPMCOUNTER29H 0xc9d |
#define | CSR_HPMCOUNTER30H 0xc9e |
#define | CSR_HPMCOUNTER31H 0xc9f |
#define | CSR_SSTATUS 0x100 |
#define | CSR_SIE 0x104 |
#define | CSR_STVEC 0x105 |
#define | CSR_SCOUNTEREN 0x106 |
#define | CSR_SENVCFG 0x10a |
#define | CSR_SSCRATCH 0x140 |
#define | CSR_SEPC 0x141 |
#define | CSR_SCAUSE 0x142 |
#define | CSR_STVAL 0x143 |
#define | CSR_SIP 0x144 |
#define | CSR_SATP 0x180 |
#define | CSR_MVENDORID 0xf11 |
#define | CSR_MARCHID 0xf12 |
#define | CSR_MIMPID 0xf13 |
#define | CSR_MHARTID 0xf14 |
#define | CSR_MCONFIGPTR 0xf15 |
#define | CSR_MSTATUS 0x300 |
#define | CSR_MISA 0x301 |
#define | CSR_MEDELEG 0x302 |
#define | CSR_MIDELEG 0x303 |
#define | CSR_MIE 0x304 |
#define | CSR_MTVEC 0x305 |
#define | CSR_MCOUNTEREN 0x306 |
#define | CSR_MSTATUSH 0x310 |
#define | CSR_MSCRATCH 0x340 |
#define | CSR_MEPC 0x341 |
#define | CSR_MCAUSE 0x342 |
#define | CSR_MTVAL 0x343 |
#define | CSR_MIP 0x344 |
#define | CSR_MTINST 0x34a |
#define | CSR_MTVAL2 0x34b |
#define | CSR_MENVCFG 0x30a |
#define | CSR_MENVCFGH 0x31a |
#define | CSR_MSECCFG 0x747 |
#define | CSR_MSECCFGH 0x757 |
#define | CSR_PMPCFG0 0x3a0 |
#define | CSR_PMPCFG1 0x3a1 |
#define | CSR_PMPCFG2 0x3a2 |
#define | CSR_PMPCFG3 0x3a3 |
#define | CSR_PMPCFG4 0x3a4 |
#define | CSR_PMPCFG5 0x3a5 |
#define | CSR_PMPCFG6 0x3a6 |
#define | CSR_PMPCFG7 0x3a7 |
#define | CSR_PMPCFG8 0x3a8 |
#define | CSR_PMPCFG9 0x3a9 |
#define | CSR_PMPCFG10 0x3aa |
#define | CSR_PMPCFG11 0x3ab |
#define | CSR_PMPCFG12 0x3ac |
#define | CSR_PMPCFG13 0x3ad |
#define | CSR_PMPCFG14 0x3ae |
#define | CSR_PMPCFG15 0x3af |
#define | CSR_PMPADDR0 0x3b0 |
#define | CSR_PMPADDR1 0x3b1 |
#define | CSR_PMPADDR2 0x3b2 |
#define | CSR_PMPADDR3 0x3b3 |
#define | CSR_PMPADDR4 0x3b4 |
#define | CSR_PMPADDR5 0x3b5 |
#define | CSR_PMPADDR6 0x3b6 |
#define | CSR_PMPADDR7 0x3b7 |
#define | CSR_PMPADDR8 0x3b8 |
#define | CSR_PMPADDR9 0x3b9 |
#define | CSR_PMPADDR10 0x3ba |
#define | CSR_PMPADDR11 0x3bb |
#define | CSR_PMPADDR12 0x3bc |
#define | CSR_PMPADDR13 0x3bd |
#define | CSR_PMPADDR14 0x3be |
#define | CSR_PMPADDR15 0x3bf |
#define | CSR_PMPADDR16 0x3c0 |
#define | CSR_PMPADDR17 0x3c1 |
#define | CSR_PMPADDR18 0x3c2 |
#define | CSR_PMPADDR19 0x3c3 |
#define | CSR_PMPADDR20 0x3c4 |
#define | CSR_PMPADDR21 0x3c5 |
#define | CSR_PMPADDR22 0x3c6 |
#define | CSR_PMPADDR23 0x3c7 |
#define | CSR_PMPADDR24 0x3c8 |
#define | CSR_PMPADDR25 0x3c9 |
#define | CSR_PMPADDR26 0x3ca |
#define | CSR_PMPADDR27 0x3cb |
#define | CSR_PMPADDR28 0x3cc |
#define | CSR_PMPADDR29 0x3cd |
#define | CSR_PMPADDR30 0x3ce |
#define | CSR_PMPADDR31 0x3cf |
#define | CSR_PMPADDR32 0x3d0 |
#define | CSR_PMPADDR33 0x3d1 |
#define | CSR_PMPADDR34 0x3d2 |
#define | CSR_PMPADDR35 0x3d3 |
#define | CSR_PMPADDR36 0x3d4 |
#define | CSR_PMPADDR37 0x3d5 |
#define | CSR_PMPADDR38 0x3d6 |
#define | CSR_PMPADDR39 0x3d7 |
#define | CSR_PMPADDR40 0x3d8 |
#define | CSR_PMPADDR41 0x3d9 |
#define | CSR_PMPADDR42 0x3da |
#define | CSR_PMPADDR43 0x3db |
#define | CSR_PMPADDR44 0x3dc |
#define | CSR_PMPADDR45 0x3dd |
#define | CSR_PMPADDR46 0x3de |
#define | CSR_PMPADDR47 0x3df |
#define | CSR_PMPADDR48 0x3e0 |
#define | CSR_PMPADDR49 0x3e1 |
#define | CSR_PMPADDR50 0x3e2 |
#define | CSR_PMPADDR51 0x3e3 |
#define | CSR_PMPADDR52 0x3e4 |
#define | CSR_PMPADDR53 0x3e5 |
#define | CSR_PMPADDR54 0x3e6 |
#define | CSR_PMPADDR55 0x3e7 |
#define | CSR_PMPADDR56 0x3e8 |
#define | CSR_PMPADDR57 0x3e9 |
#define | CSR_PMPADDR58 0x3ea |
#define | CSR_PMPADDR59 0x3eb |
#define | CSR_PMPADDR60 0x3ec |
#define | CSR_PMPADDR61 0x3ed |
#define | CSR_PMPADDR62 0x3ee |
#define | CSR_PMPADDR63 0x3ef |
#define | CSR_MCYCLE 0xb00 |
#define | CSR_MINSTRET 0xb02 |
#define | CSR_MHPMCOUNTER3 0xb03 |
#define | CSR_MHPMCOUNTER4 0xb04 |
#define | CSR_MHPMCOUNTER5 0xb05 |
#define | CSR_MHPMCOUNTER6 0xb06 |
#define | CSR_MHPMCOUNTER7 0xb07 |
#define | CSR_MHPMCOUNTER8 0xb08 |
#define | CSR_MHPMCOUNTER9 0xb09 |
#define | CSR_MHPMCOUNTER10 0xb0a |
#define | CSR_MHPMCOUNTER11 0xb0b |
#define | CSR_MHPMCOUNTER12 0xb0c |
#define | CSR_MHPMCOUNTER13 0xb0d |
#define | CSR_MHPMCOUNTER14 0xb0e |
#define | CSR_MHPMCOUNTER15 0xb0f |
#define | CSR_MHPMCOUNTER16 0xb10 |
#define | CSR_MHPMCOUNTER17 0xb11 |
#define | CSR_MHPMCOUNTER18 0xb12 |
#define | CSR_MHPMCOUNTER19 0xb13 |
#define | CSR_MHPMCOUNTER20 0xb14 |
#define | CSR_MHPMCOUNTER21 0xb15 |
#define | CSR_MHPMCOUNTER22 0xb16 |
#define | CSR_MHPMCOUNTER23 0xb17 |
#define | CSR_MHPMCOUNTER24 0xb18 |
#define | CSR_MHPMCOUNTER25 0xb19 |
#define | CSR_MHPMCOUNTER26 0xb1a |
#define | CSR_MHPMCOUNTER27 0xb1b |
#define | CSR_MHPMCOUNTER28 0xb1c |
#define | CSR_MHPMCOUNTER29 0xb1d |
#define | CSR_MHPMCOUNTER30 0xb1e |
#define | CSR_MHPMCOUNTER31 0xb1f |
#define | CSR_MCYCLEH 0xb80 |
#define | CSR_MINSTRETH 0xb82 |
#define | CSR_MHPMCOUNTER3H 0xb83 |
#define | CSR_MHPMCOUNTER4H 0xb84 |
#define | CSR_MHPMCOUNTER5H 0xb85 |
#define | CSR_MHPMCOUNTER6H 0xb86 |
#define | CSR_MHPMCOUNTER7H 0xb87 |
#define | CSR_MHPMCOUNTER8H 0xb88 |
#define | CSR_MHPMCOUNTER9H 0xb89 |
#define | CSR_MHPMCOUNTER10H 0xb8a |
#define | CSR_MHPMCOUNTER11H 0xb8b |
#define | CSR_MHPMCOUNTER12H 0xb8c |
#define | CSR_MHPMCOUNTER13H 0xb8d |
#define | CSR_MHPMCOUNTER14H 0xb8e |
#define | CSR_MHPMCOUNTER15H 0xb8f |
#define | CSR_MHPMCOUNTER16H 0xb90 |
#define | CSR_MHPMCOUNTER17H 0xb91 |
#define | CSR_MHPMCOUNTER18H 0xb92 |
#define | CSR_MHPMCOUNTER19H 0xb93 |
#define | CSR_MHPMCOUNTER20H 0xb94 |
#define | CSR_MHPMCOUNTER21H 0xb95 |
#define | CSR_MHPMCOUNTER22H 0xb96 |
#define | CSR_MHPMCOUNTER23H 0xb97 |
#define | CSR_MHPMCOUNTER24H 0xb98 |
#define | CSR_MHPMCOUNTER25H 0xb99 |
#define | CSR_MHPMCOUNTER26H 0xb9a |
#define | CSR_MHPMCOUNTER27H 0xb9b |
#define | CSR_MHPMCOUNTER28H 0xb9c |
#define | CSR_MHPMCOUNTER29H 0xb9d |
#define | CSR_MHPMCOUNTER30H 0xb9e |
#define | CSR_MHPMCOUNTER31H 0xb9f |
#define | CSR_MCOUNTINHIBIT 0x320 |
#define | CSR_MHPMEVENT3 0x323 |
#define | CSR_MHPMEVENT4 0x324 |
#define | CSR_MHPMEVENT5 0x325 |
#define | CSR_MHPMEVENT6 0x326 |
#define | CSR_MHPMEVENT7 0x327 |
#define | CSR_MHPMEVENT8 0x328 |
#define | CSR_MHPMEVENT9 0x329 |
#define | CSR_MHPMEVENT10 0x32a |
#define | CSR_MHPMEVENT11 0x32b |
#define | CSR_MHPMEVENT12 0x32c |
#define | CSR_MHPMEVENT13 0x32d |
#define | CSR_MHPMEVENT14 0x32e |
#define | CSR_MHPMEVENT15 0x32f |
#define | CSR_MHPMEVENT16 0x330 |
#define | CSR_MHPMEVENT17 0x331 |
#define | CSR_MHPMEVENT18 0x332 |
#define | CSR_MHPMEVENT19 0x333 |
#define | CSR_MHPMEVENT20 0x334 |
#define | CSR_MHPMEVENT21 0x335 |
#define | CSR_MHPMEVENT22 0x336 |
#define | CSR_MHPMEVENT23 0x337 |
#define | CSR_MHPMEVENT24 0x338 |
#define | CSR_MHPMEVENT25 0x339 |
#define | CSR_MHPMEVENT26 0x33a |
#define | CSR_MHPMEVENT27 0x33b |
#define | CSR_MHPMEVENT28 0x33c |
#define | CSR_MHPMEVENT29 0x33d |
#define | CSR_MHPMEVENT30 0x33e |
#define | CSR_MHPMEVENT31 0x33f |
#define | CSR_HSTATUS 0x600 |
#define | CSR_HEDELEG 0x602 |
#define | CSR_HIDELEG 0x603 |
#define | CSR_HIE 0x604 |
#define | CSR_HCOUNTEREN 0x606 |
#define | CSR_HGEIE 0x607 |
#define | CSR_HTVAL 0x643 |
#define | CSR_HIP 0x644 |
#define | CSR_HVIP 0x645 |
#define | CSR_HTINST 0x64a |
#define | CSR_HGEIP 0xe12 |
#define | CSR_HENVCFG 0x60a |
#define | CSR_HENVCFGH 0x61a |
#define | CSR_HGATP 0x680 |
#define | CSR_HTIMEDELTA 0x605 |
#define | CSR_HTIMEDELTAH 0x615 |
#define | CSR_VSSTATUS 0x200 |
#define | CSR_VSIE 0x204 |
#define | CSR_VSTVEC 0x205 |
#define | CSR_VSSCRATCH 0x240 |
#define | CSR_VSEPC 0x241 |
#define | CSR_VSCAUSE 0x242 |
#define | CSR_VSTVAL 0x243 |
#define | CSR_VSIP 0x244 |
#define | CSR_VSATP 0x280 |
#define | CSR_MBASE 0x380 |
#define | CSR_MBOUND 0x381 |
#define | CSR_MIBASE 0x382 |
#define | CSR_MIBOUND 0x383 |
#define | CSR_MDBASE 0x384 |
#define | CSR_MDBOUND 0x385 |
#define | CSR_USTATUS 0x0 |
#define | CSR_UIE 0x4 |
#define | CSR_UTVEC 0x5 |
#define | CSR_USCRATCH 0x40 |
#define | CSR_UEPC 0x41 |
#define | CSR_UCAUSE 0x42 |
#define | CSR_UTVAL 0x43 |
#define | CSR_UIP 0x44 |
#define | CSR_SEDELEG 0x102 |
#define | CSR_SIDELEG 0x103 |
#define | CSR_MISELECT 0x350 |
#define | CSR_MIREG 0x351 |
#define | CSR_MTOPEI 0x35c |
#define | CSR_MTOPI 0xfb0 |
#define | CSR_MVIEN 0x308 |
#define | CSR_MVIP 0x309 |
#define | CSR_MIDELEGH 0x313 |
#define | CSR_MIEH 0x314 |
#define | CSR_MVIENH 0x318 |
#define | CSR_MVIPH 0x319 |
#define | CSR_MIPH 0x354 |
#define | CSR_MCYCLECFG 0x321 |
#define | CSR_MINSTRETCFG 0x322 |
#define | CSR_MCYCLECFGH 0x721 |
#define | CSR_MINSTRETCFGH 0x722 |
#define | CSR_MSTATEEN0 0x30c |
#define | CSR_MSTATEEN1 0x30d |
#define | CSR_MSTATEEN2 0x30e |
#define | CSR_MSTATEEN3 0x30f |
#define | CSR_SSTATEEN0 0x10c |
#define | CSR_SSTATEEN1 0x10d |
#define | CSR_SSTATEEN2 0x10e |
#define | CSR_SSTATEEN3 0x10f |
#define | CSR_HSTATEEN0 0x60c |
#define | CSR_HSTATEEN1 0x60d |
#define | CSR_HSTATEEN2 0x60e |
#define | CSR_HSTATEEN3 0x60f |
#define | CSR_MSTATEEN0H 0x31c |
#define | CSR_MSTATEEN1H 0x31d |
#define | CSR_MSTATEEN2H 0x31e |
#define | CSR_MSTATEEN3H 0x31f |
#define | CSR_HSTATEEN0H 0x61c |
#define | CSR_HSTATEEN1H 0x61d |
#define | CSR_HSTATEEN2H 0x61e |
#define | CSR_HSTATEEN3H 0x61f |
#define | CSR_SISELECT 0x150 |
#define | CSR_SIREG 0x151 |
#define | CSR_STOPEI 0x15c |
#define | CSR_STOPI 0xdb0 |
#define | CSR_SIEH 0x114 |
#define | CSR_SIPH 0x154 |
#define | CSR_HVIEN 0x608 |
#define | CSR_HVICTL 0x609 |
#define | CSR_HVIPRIO1 0x646 |
#define | CSR_HVIPRIO2 0x647 |
#define | CSR_VSISELECT 0x250 |
#define | CSR_VSIREG 0x251 |
#define | CSR_VSTOPEI 0x25c |
#define | CSR_VSTOPI 0xeb0 |
#define | CSR_HIDELEGH 0x613 |
#define | CSR_HVIENH 0x618 |
#define | CSR_HVIPH 0x655 |
#define | CSR_HVIPRIO1H 0x656 |
#define | CSR_HVIPRIO2H 0x657 |
#define | CSR_VSIEH 0x214 |
#define | CSR_VSIPH 0x254 |
#define | CSR_SCOUNTOVF 0xda0 |
#define | CSR_MHPMEVENT3H 0x723 |
#define | CSR_MHPMEVENT4H 0x724 |
#define | CSR_MHPMEVENT5H 0x725 |
#define | CSR_MHPMEVENT6H 0x726 |
#define | CSR_MHPMEVENT7H 0x727 |
#define | CSR_MHPMEVENT8H 0x728 |
#define | CSR_MHPMEVENT9H 0x729 |
#define | CSR_MHPMEVENT10H 0x72a |
#define | CSR_MHPMEVENT11H 0x72b |
#define | CSR_MHPMEVENT12H 0x72c |
#define | CSR_MHPMEVENT13H 0x72d |
#define | CSR_MHPMEVENT14H 0x72e |
#define | CSR_MHPMEVENT15H 0x72f |
#define | CSR_MHPMEVENT16H 0x730 |
#define | CSR_MHPMEVENT17H 0x731 |
#define | CSR_MHPMEVENT18H 0x732 |
#define | CSR_MHPMEVENT19H 0x733 |
#define | CSR_MHPMEVENT20H 0x734 |
#define | CSR_MHPMEVENT21H 0x735 |
#define | CSR_MHPMEVENT22H 0x736 |
#define | CSR_MHPMEVENT23H 0x737 |
#define | CSR_MHPMEVENT24H 0x738 |
#define | CSR_MHPMEVENT25H 0x739 |
#define | CSR_MHPMEVENT26H 0x73a |
#define | CSR_MHPMEVENT27H 0x73b |
#define | CSR_MHPMEVENT28H 0x73c |
#define | CSR_MHPMEVENT29H 0x73d |
#define | CSR_MHPMEVENT30H 0x73e |
#define | CSR_MHPMEVENT31H 0x73f |
#define | CSR_STIMECMP 0x14d |
#define | CSR_STIMECMPH 0x15d |
#define | CSR_VSTIMECMP 0x24d |
#define | CSR_VSTIMECMPH 0x25d |
#define | CSR_FFLAGS 0x1 |
#define | CSR_FRM 0x2 |
#define | CSR_FCSR 0x3 |
#define | CSR_DCSR 0x7b0 |
#define | CSR_DPC 0x7b1 |
#define | CSR_DSCRATCH0 0x7b2 |
#define | CSR_DSCRATCH1 0x7b3 |
#define | CSR_TSELECT 0x7a0 |
#define | CSR_TDATA1 0x7a1 |
#define | CSR_TDATA2 0x7a2 |
#define | CSR_TDATA3 0x7a3 |
#define | CSR_TINFO 0x7a4 |
#define | CSR_TCONTROL 0x7a5 |
#define | CSR_HCONTEXT 0x6a8 |
#define | CSR_SCONTEXT 0x5a8 |
#define | CSR_MCONTEXT 0x7a8 |
#define | CSR_MSCONTEXT 0x7aa |
#define | CSR_SEED 0x015 |
#define | CSR_VSTART 0x008 |
#define | CSR_VXSAT 0x009 |
#define | CSR_VXRM 0x00a |
#define | CSR_VCSR 0x00f |
#define | CSR_VL 0xc20 |
#define | CSR_VTYPE 0xc21 |
#define | CSR_VLENB 0xc22 |
#define | DECLARE_CSR(name, num, class, define_ver, abort_ver) |
Functions | |
static struct value * | value_of_riscv_user_reg (frame_info_ptr frame, const void *baton) |
static void | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value) |
static void | show_riscv_debug_variable (struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value) |
int | riscv_isa_xlen (struct gdbarch *gdbarch) |
int | riscv_abi_xlen (struct gdbarch *gdbarch) |
int | riscv_isa_flen (struct gdbarch *gdbarch) |
int | riscv_abi_flen (struct gdbarch *gdbarch) |
bool | riscv_abi_embedded (struct gdbarch *gdbarch) |
static bool | riscv_has_fp_regs (struct gdbarch *gdbarch) |
static bool | riscv_has_fp_abi (struct gdbarch *gdbarch) |
static bool | riscv_is_fp_regno_p (int regno) |
static int | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) |
static const gdb_byte * | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
static const char * | riscv_register_name (struct gdbarch *gdbarch, int regnum) |
static enum register_status | riscv_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf) |
static void | riscv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf) |
static int | riscv_cannot_store_register (struct gdbarch *gdbarch, int regnum) |
static struct type * | riscv_fpreg_d_type (struct gdbarch *gdbarch) |
static struct type * | riscv_register_type (struct gdbarch *gdbarch, int regnum) |
static void | riscv_print_one_register_info (struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, int regnum) |
static bool | riscv_is_regnum_a_named_csr (int regnum) |
static bool | riscv_is_unknown_csr (struct gdbarch *gdbarch, int regnum) |
static int | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, const struct reggroup *reggroup) |
static const char * | riscv_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
static struct type * | riscv_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
static int | riscv_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, const struct reggroup *reggroup) |
static void | riscv_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, int regnum, int print_all) |
static bool | is_insn_load_of_fp_from_sp (const struct riscv_insn &insn) |
static bool | is_insn_addi_of_sp_to_sp (const struct riscv_insn &insn) |
static bool | previous_insn_is_load_fp_from_stack (struct gdbarch *gdbarch, CORE_ADDR pc) |
static bool | previous_insn_is_add_imm_to_sp (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR *prev_pc) |
static bool | riscv_detect_end_of_function (struct gdbarch *gdbarch, CORE_ADDR pc, int *offset) |
static CORE_ADDR | riscv_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc, CORE_ADDR end_pc, struct riscv_unwind_cache *cache) |
static CORE_ADDR | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
static CORE_ADDR | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache) |
static ULONGEST | riscv_type_align (gdbarch *gdbarch, type *type) |
static int | riscv_arg_regs_available (struct riscv_arg_reg *reg) |
static bool | riscv_assign_reg_location (struct riscv_arg_info::location *loc, struct riscv_arg_reg *reg, int length, int offset) |
static void | riscv_assign_stack_location (struct riscv_arg_info::location *loc, struct riscv_memory_offsets *memory, int length, int align) |
static void | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo) |
static void | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo) |
static void | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo) |
static void | riscv_call_arg_struct (struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo) |
static void | riscv_arg_location (struct gdbarch *gdbarch, struct riscv_arg_info *ainfo, struct riscv_call_info *cinfo, struct type *type, bool is_unnamed) |
static void | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, struct riscv_arg_info *info, CORE_ADDR sp_refs, CORE_ADDR sp_args) |
static void | riscv_regcache_cooked_write (int regnum, const gdb_byte *data, int len, struct regcache *regcache, int flen) |
static CORE_ADDR | riscv_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr) |
static enum return_value_convention | riscv_return_value (struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, struct value **read_value, const gdb_byte *writebuf) |
static CORE_ADDR | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
static struct riscv_unwind_cache * | riscv_frame_cache (frame_info_ptr this_frame, void **this_cache) |
static void | riscv_frame_this_id (frame_info_ptr this_frame, void **prologue_cache, struct frame_id *this_id) |
static struct value * | riscv_frame_prev_register (frame_info_ptr this_frame, void **prologue_cache, int regnum) |
static struct riscv_gdbarch_features | riscv_features_from_bfd (const bfd *abfd) |
static const struct target_desc * | riscv_find_default_target_description (const struct gdbarch_info info) |
static void | riscv_add_reggroups (struct gdbarch *gdbarch) |
static int | riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
static std::string | riscv_gcc_target_options (struct gdbarch *gdbarch) |
static int | riscv_tdesc_unknown_reg (struct gdbarch *gdbarch, tdesc_feature *feature, const char *reg_name, int possible_regnum) |
static const char * | riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) |
static int | riscv_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) |
static struct gdbarch * | riscv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
static CORE_ADDR | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) |
static bool | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, CORE_ADDR *next_pc) |
std::vector< CORE_ADDR > | riscv_software_single_step (struct regcache *regcache) |
static void | riscv_init_reggroups () |
void | riscv_supply_regset (const struct regset *regset, struct regcache *regcache, int regnum, const void *regs, size_t len) |
void | _initialize_riscv_tdep () |
Variables | |
static bool | riscv_debug_breakpoints = false |
static bool | riscv_debug_infcall = false |
static bool | riscv_debug_unwinder = false |
static bool | riscv_debug_gdbarch = false |
const char * | riscv_feature_name_csr = "org.gnu.gdb.riscv.csr" |
static const char * | riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu" |
static const char * | riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu" |
static const char * | riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual" |
static const char * | riscv_feature_name_vector = "org.gnu.gdb.riscv.vector" |
static char * | riscv_disassembler_options |
static const reggroup * | csr_reggroup = nullptr |
static const struct riscv_xreg_feature | riscv_xreg_feature |
static const struct riscv_freg_feature | riscv_freg_feature |
static const struct riscv_virtual_feature | riscv_virtual_feature |
static const struct riscv_csr_feature | riscv_csr_feature |
static const struct riscv_vector_feature | riscv_vector_feature |
static enum auto_boolean | use_compressed_breakpoints |
static struct cmd_list_element * | setriscvcmdlist = NULL |
static struct cmd_list_element * | showriscvcmdlist = NULL |
static struct cmd_list_element * | setdebugriscvcmdlist = NULL |
static struct cmd_list_element * | showdebugriscvcmdlist = NULL |
static const struct frame_unwind | riscv_frame_unwind |
static const char *const | stap_register_indirection_prefixes [] |
static const char *const | stap_register_indirection_suffixes [] |
#define BIGGEST_ALIGNMENT 16 |
Definition at line 65 of file riscv-tdep.c.
Referenced by riscv_type_align().
#define CSR_CYCLE 0xc00 |
#define CSR_CYCLEH 0xc80 |
#define CSR_DCSR 0x7b0 |
#define CSR_DPC 0x7b1 |
#define CSR_DSCRATCH0 0x7b2 |
#define CSR_DSCRATCH1 0x7b3 |
#define CSR_FCSR 0x3 |
#define CSR_FFLAGS 0x1 |
#define CSR_FRM 0x2 |
#define CSR_HCONTEXT 0x6a8 |
#define CSR_HCOUNTEREN 0x606 |
#define CSR_HEDELEG 0x602 |
#define CSR_HENVCFG 0x60a |
#define CSR_HENVCFGH 0x61a |
#define CSR_HGATP 0x680 |
#define CSR_HGEIE 0x607 |
#define CSR_HGEIP 0xe12 |
#define CSR_HIDELEG 0x603 |
#define CSR_HIDELEGH 0x613 |
#define CSR_HIE 0x604 |
#define CSR_HIP 0x644 |
#define CSR_HPMCOUNTER10 0xc0a |
#define CSR_HPMCOUNTER10H 0xc8a |
#define CSR_HPMCOUNTER11 0xc0b |
#define CSR_HPMCOUNTER11H 0xc8b |
#define CSR_HPMCOUNTER12 0xc0c |
#define CSR_HPMCOUNTER12H 0xc8c |
#define CSR_HPMCOUNTER13 0xc0d |
#define CSR_HPMCOUNTER13H 0xc8d |
#define CSR_HPMCOUNTER14 0xc0e |
#define CSR_HPMCOUNTER14H 0xc8e |
#define CSR_HPMCOUNTER15 0xc0f |
#define CSR_HPMCOUNTER15H 0xc8f |
#define CSR_HPMCOUNTER16 0xc10 |
#define CSR_HPMCOUNTER16H 0xc90 |
#define CSR_HPMCOUNTER17 0xc11 |
#define CSR_HPMCOUNTER17H 0xc91 |
#define CSR_HPMCOUNTER18 0xc12 |
#define CSR_HPMCOUNTER18H 0xc92 |
#define CSR_HPMCOUNTER19 0xc13 |
#define CSR_HPMCOUNTER19H 0xc93 |
#define CSR_HPMCOUNTER20 0xc14 |
#define CSR_HPMCOUNTER20H 0xc94 |
#define CSR_HPMCOUNTER21 0xc15 |
#define CSR_HPMCOUNTER21H 0xc95 |
#define CSR_HPMCOUNTER22 0xc16 |
#define CSR_HPMCOUNTER22H 0xc96 |
#define CSR_HPMCOUNTER23 0xc17 |
#define CSR_HPMCOUNTER23H 0xc97 |
#define CSR_HPMCOUNTER24 0xc18 |
#define CSR_HPMCOUNTER24H 0xc98 |
#define CSR_HPMCOUNTER25 0xc19 |
#define CSR_HPMCOUNTER25H 0xc99 |
#define CSR_HPMCOUNTER26 0xc1a |
#define CSR_HPMCOUNTER26H 0xc9a |
#define CSR_HPMCOUNTER27 0xc1b |
#define CSR_HPMCOUNTER27H 0xc9b |
#define CSR_HPMCOUNTER28 0xc1c |
#define CSR_HPMCOUNTER28H 0xc9c |
#define CSR_HPMCOUNTER29 0xc1d |
#define CSR_HPMCOUNTER29H 0xc9d |
#define CSR_HPMCOUNTER3 0xc03 |
#define CSR_HPMCOUNTER30 0xc1e |
#define CSR_HPMCOUNTER30H 0xc9e |
#define CSR_HPMCOUNTER31 0xc1f |
#define CSR_HPMCOUNTER31H 0xc9f |
#define CSR_HPMCOUNTER3H 0xc83 |
#define CSR_HPMCOUNTER4 0xc04 |
#define CSR_HPMCOUNTER4H 0xc84 |
#define CSR_HPMCOUNTER5 0xc05 |
#define CSR_HPMCOUNTER5H 0xc85 |
#define CSR_HPMCOUNTER6 0xc06 |
#define CSR_HPMCOUNTER6H 0xc86 |
#define CSR_HPMCOUNTER7 0xc07 |
#define CSR_HPMCOUNTER7H 0xc87 |
#define CSR_HPMCOUNTER8 0xc08 |
#define CSR_HPMCOUNTER8H 0xc88 |
#define CSR_HPMCOUNTER9 0xc09 |
#define CSR_HPMCOUNTER9H 0xc89 |
#define CSR_HSTATEEN0 0x60c |
#define CSR_HSTATEEN0H 0x61c |
#define CSR_HSTATEEN1 0x60d |
#define CSR_HSTATEEN1H 0x61d |
#define CSR_HSTATEEN2 0x60e |
#define CSR_HSTATEEN2H 0x61e |
#define CSR_HSTATEEN3 0x60f |
#define CSR_HSTATEEN3H 0x61f |
#define CSR_HSTATUS 0x600 |
#define CSR_HTIMEDELTA 0x605 |
#define CSR_HTIMEDELTAH 0x615 |
#define CSR_HTINST 0x64a |
#define CSR_HTVAL 0x643 |
#define CSR_HVICTL 0x609 |
#define CSR_HVIEN 0x608 |
#define CSR_HVIENH 0x618 |
#define CSR_HVIP 0x645 |
#define CSR_HVIPH 0x655 |
#define CSR_HVIPRIO1 0x646 |
#define CSR_HVIPRIO1H 0x656 |
#define CSR_HVIPRIO2 0x647 |
#define CSR_HVIPRIO2H 0x657 |
#define CSR_INSTRET 0xc02 |
#define CSR_INSTRETH 0xc82 |
#define CSR_MARCHID 0xf12 |
#define CSR_MBASE 0x380 |
#define CSR_MBOUND 0x381 |
#define CSR_MCAUSE 0x342 |
#define CSR_MCONFIGPTR 0xf15 |
#define CSR_MCONTEXT 0x7a8 |
#define CSR_MCOUNTEREN 0x306 |
#define CSR_MCOUNTINHIBIT 0x320 |
#define CSR_MCYCLE 0xb00 |
#define CSR_MCYCLECFG 0x321 |
#define CSR_MCYCLECFGH 0x721 |
#define CSR_MCYCLEH 0xb80 |
#define CSR_MDBASE 0x384 |
#define CSR_MDBOUND 0x385 |
#define CSR_MEDELEG 0x302 |
#define CSR_MENVCFG 0x30a |
#define CSR_MENVCFGH 0x31a |
#define CSR_MEPC 0x341 |
#define CSR_MHARTID 0xf14 |
#define CSR_MHPMCOUNTER10 0xb0a |
#define CSR_MHPMCOUNTER10H 0xb8a |
#define CSR_MHPMCOUNTER11 0xb0b |
#define CSR_MHPMCOUNTER11H 0xb8b |
#define CSR_MHPMCOUNTER12 0xb0c |
#define CSR_MHPMCOUNTER12H 0xb8c |
#define CSR_MHPMCOUNTER13 0xb0d |
#define CSR_MHPMCOUNTER13H 0xb8d |
#define CSR_MHPMCOUNTER14 0xb0e |
#define CSR_MHPMCOUNTER14H 0xb8e |
#define CSR_MHPMCOUNTER15 0xb0f |
#define CSR_MHPMCOUNTER15H 0xb8f |
#define CSR_MHPMCOUNTER16 0xb10 |
#define CSR_MHPMCOUNTER16H 0xb90 |
#define CSR_MHPMCOUNTER17 0xb11 |
#define CSR_MHPMCOUNTER17H 0xb91 |
#define CSR_MHPMCOUNTER18 0xb12 |
#define CSR_MHPMCOUNTER18H 0xb92 |
#define CSR_MHPMCOUNTER19 0xb13 |
#define CSR_MHPMCOUNTER19H 0xb93 |
#define CSR_MHPMCOUNTER20 0xb14 |
#define CSR_MHPMCOUNTER20H 0xb94 |
#define CSR_MHPMCOUNTER21 0xb15 |
#define CSR_MHPMCOUNTER21H 0xb95 |
#define CSR_MHPMCOUNTER22 0xb16 |
#define CSR_MHPMCOUNTER22H 0xb96 |
#define CSR_MHPMCOUNTER23 0xb17 |
#define CSR_MHPMCOUNTER23H 0xb97 |
#define CSR_MHPMCOUNTER24 0xb18 |
#define CSR_MHPMCOUNTER24H 0xb98 |
#define CSR_MHPMCOUNTER25 0xb19 |
#define CSR_MHPMCOUNTER25H 0xb99 |
#define CSR_MHPMCOUNTER26 0xb1a |
#define CSR_MHPMCOUNTER26H 0xb9a |
#define CSR_MHPMCOUNTER27 0xb1b |
#define CSR_MHPMCOUNTER27H 0xb9b |
#define CSR_MHPMCOUNTER28 0xb1c |
#define CSR_MHPMCOUNTER28H 0xb9c |
#define CSR_MHPMCOUNTER29 0xb1d |
#define CSR_MHPMCOUNTER29H 0xb9d |
#define CSR_MHPMCOUNTER3 0xb03 |
#define CSR_MHPMCOUNTER30 0xb1e |
#define CSR_MHPMCOUNTER30H 0xb9e |
#define CSR_MHPMCOUNTER31 0xb1f |
#define CSR_MHPMCOUNTER31H 0xb9f |
#define CSR_MHPMCOUNTER3H 0xb83 |
#define CSR_MHPMCOUNTER4 0xb04 |
#define CSR_MHPMCOUNTER4H 0xb84 |
#define CSR_MHPMCOUNTER5 0xb05 |
#define CSR_MHPMCOUNTER5H 0xb85 |
#define CSR_MHPMCOUNTER6 0xb06 |
#define CSR_MHPMCOUNTER6H 0xb86 |
#define CSR_MHPMCOUNTER7 0xb07 |
#define CSR_MHPMCOUNTER7H 0xb87 |
#define CSR_MHPMCOUNTER8 0xb08 |
#define CSR_MHPMCOUNTER8H 0xb88 |
#define CSR_MHPMCOUNTER9 0xb09 |
#define CSR_MHPMCOUNTER9H 0xb89 |
#define CSR_MHPMEVENT10 0x32a |
#define CSR_MHPMEVENT10H 0x72a |
#define CSR_MHPMEVENT11 0x32b |
#define CSR_MHPMEVENT11H 0x72b |
#define CSR_MHPMEVENT12 0x32c |
#define CSR_MHPMEVENT12H 0x72c |
#define CSR_MHPMEVENT13 0x32d |
#define CSR_MHPMEVENT13H 0x72d |
#define CSR_MHPMEVENT14 0x32e |
#define CSR_MHPMEVENT14H 0x72e |
#define CSR_MHPMEVENT15 0x32f |
#define CSR_MHPMEVENT15H 0x72f |
#define CSR_MHPMEVENT16 0x330 |
#define CSR_MHPMEVENT16H 0x730 |
#define CSR_MHPMEVENT17 0x331 |
#define CSR_MHPMEVENT17H 0x731 |
#define CSR_MHPMEVENT18 0x332 |
#define CSR_MHPMEVENT18H 0x732 |
#define CSR_MHPMEVENT19 0x333 |
#define CSR_MHPMEVENT19H 0x733 |
#define CSR_MHPMEVENT20 0x334 |
#define CSR_MHPMEVENT20H 0x734 |
#define CSR_MHPMEVENT21 0x335 |
#define CSR_MHPMEVENT21H 0x735 |
#define CSR_MHPMEVENT22 0x336 |
#define CSR_MHPMEVENT22H 0x736 |
#define CSR_MHPMEVENT23 0x337 |
#define CSR_MHPMEVENT23H 0x737 |
#define CSR_MHPMEVENT24 0x338 |
#define CSR_MHPMEVENT24H 0x738 |
#define CSR_MHPMEVENT25 0x339 |
#define CSR_MHPMEVENT25H 0x739 |
#define CSR_MHPMEVENT26 0x33a |
#define CSR_MHPMEVENT26H 0x73a |
#define CSR_MHPMEVENT27 0x33b |
#define CSR_MHPMEVENT27H 0x73b |
#define CSR_MHPMEVENT28 0x33c |
#define CSR_MHPMEVENT28H 0x73c |
#define CSR_MHPMEVENT29 0x33d |
#define CSR_MHPMEVENT29H 0x73d |
#define CSR_MHPMEVENT3 0x323 |
#define CSR_MHPMEVENT30 0x33e |
#define CSR_MHPMEVENT30H 0x73e |
#define CSR_MHPMEVENT31 0x33f |
#define CSR_MHPMEVENT31H 0x73f |
#define CSR_MHPMEVENT3H 0x723 |
#define CSR_MHPMEVENT4 0x324 |
#define CSR_MHPMEVENT4H 0x724 |
#define CSR_MHPMEVENT5 0x325 |
#define CSR_MHPMEVENT5H 0x725 |
#define CSR_MHPMEVENT6 0x326 |
#define CSR_MHPMEVENT6H 0x726 |
#define CSR_MHPMEVENT7 0x327 |
#define CSR_MHPMEVENT7H 0x727 |
#define CSR_MHPMEVENT8 0x328 |
#define CSR_MHPMEVENT8H 0x728 |
#define CSR_MHPMEVENT9 0x329 |
#define CSR_MHPMEVENT9H 0x729 |
#define CSR_MIBASE 0x382 |
#define CSR_MIBOUND 0x383 |
#define CSR_MIDELEG 0x303 |
#define CSR_MIDELEGH 0x313 |
#define CSR_MIE 0x304 |
#define CSR_MIEH 0x314 |
#define CSR_MIMPID 0xf13 |
#define CSR_MINSTRET 0xb02 |
#define CSR_MINSTRETCFG 0x322 |
#define CSR_MINSTRETCFGH 0x722 |
#define CSR_MINSTRETH 0xb82 |
#define CSR_MIP 0x344 |
#define CSR_MIPH 0x354 |
#define CSR_MIREG 0x351 |
#define CSR_MISA 0x301 |
#define CSR_MISELECT 0x350 |
#define CSR_MSCONTEXT 0x7aa |
#define CSR_MSCRATCH 0x340 |
#define CSR_MSECCFG 0x747 |
#define CSR_MSECCFGH 0x757 |
#define CSR_MSTATEEN0 0x30c |
#define CSR_MSTATEEN0H 0x31c |
#define CSR_MSTATEEN1 0x30d |
#define CSR_MSTATEEN1H 0x31d |
#define CSR_MSTATEEN2 0x30e |
#define CSR_MSTATEEN2H 0x31e |
#define CSR_MSTATEEN3 0x30f |
#define CSR_MSTATEEN3H 0x31f |
#define CSR_MSTATUS 0x300 |
#define CSR_MSTATUSH 0x310 |
#define CSR_MTINST 0x34a |
#define CSR_MTOPEI 0x35c |
#define CSR_MTOPI 0xfb0 |
#define CSR_MTVAL 0x343 |
#define CSR_MTVAL2 0x34b |
#define CSR_MTVEC 0x305 |
#define CSR_MVENDORID 0xf11 |
#define CSR_MVIEN 0x308 |
#define CSR_MVIENH 0x318 |
#define CSR_MVIP 0x309 |
#define CSR_MVIPH 0x319 |
#define CSR_PMPADDR0 0x3b0 |
#define CSR_PMPADDR1 0x3b1 |
#define CSR_PMPADDR10 0x3ba |
#define CSR_PMPADDR11 0x3bb |
#define CSR_PMPADDR12 0x3bc |
#define CSR_PMPADDR13 0x3bd |
#define CSR_PMPADDR14 0x3be |
#define CSR_PMPADDR15 0x3bf |
#define CSR_PMPADDR16 0x3c0 |
#define CSR_PMPADDR17 0x3c1 |
#define CSR_PMPADDR18 0x3c2 |
#define CSR_PMPADDR19 0x3c3 |
#define CSR_PMPADDR2 0x3b2 |
#define CSR_PMPADDR20 0x3c4 |
#define CSR_PMPADDR21 0x3c5 |
#define CSR_PMPADDR22 0x3c6 |
#define CSR_PMPADDR23 0x3c7 |
#define CSR_PMPADDR24 0x3c8 |
#define CSR_PMPADDR25 0x3c9 |
#define CSR_PMPADDR26 0x3ca |
#define CSR_PMPADDR27 0x3cb |
#define CSR_PMPADDR28 0x3cc |
#define CSR_PMPADDR29 0x3cd |
#define CSR_PMPADDR3 0x3b3 |
#define CSR_PMPADDR30 0x3ce |
#define CSR_PMPADDR31 0x3cf |
#define CSR_PMPADDR32 0x3d0 |
#define CSR_PMPADDR33 0x3d1 |
#define CSR_PMPADDR34 0x3d2 |
#define CSR_PMPADDR35 0x3d3 |
#define CSR_PMPADDR36 0x3d4 |
#define CSR_PMPADDR37 0x3d5 |
#define CSR_PMPADDR38 0x3d6 |
#define CSR_PMPADDR39 0x3d7 |
#define CSR_PMPADDR4 0x3b4 |
#define CSR_PMPADDR40 0x3d8 |
#define CSR_PMPADDR41 0x3d9 |
#define CSR_PMPADDR42 0x3da |
#define CSR_PMPADDR43 0x3db |
#define CSR_PMPADDR44 0x3dc |
#define CSR_PMPADDR45 0x3dd |
#define CSR_PMPADDR46 0x3de |
#define CSR_PMPADDR47 0x3df |
#define CSR_PMPADDR48 0x3e0 |
#define CSR_PMPADDR49 0x3e1 |
#define CSR_PMPADDR5 0x3b5 |
#define CSR_PMPADDR50 0x3e2 |
#define CSR_PMPADDR51 0x3e3 |
#define CSR_PMPADDR52 0x3e4 |
#define CSR_PMPADDR53 0x3e5 |
#define CSR_PMPADDR54 0x3e6 |
#define CSR_PMPADDR55 0x3e7 |
#define CSR_PMPADDR56 0x3e8 |
#define CSR_PMPADDR57 0x3e9 |
#define CSR_PMPADDR58 0x3ea |
#define CSR_PMPADDR59 0x3eb |
#define CSR_PMPADDR6 0x3b6 |
#define CSR_PMPADDR60 0x3ec |
#define CSR_PMPADDR61 0x3ed |
#define CSR_PMPADDR62 0x3ee |
#define CSR_PMPADDR63 0x3ef |
#define CSR_PMPADDR7 0x3b7 |
#define CSR_PMPADDR8 0x3b8 |
#define CSR_PMPADDR9 0x3b9 |
#define CSR_PMPCFG0 0x3a0 |
#define CSR_PMPCFG1 0x3a1 |
#define CSR_PMPCFG10 0x3aa |
#define CSR_PMPCFG11 0x3ab |
#define CSR_PMPCFG12 0x3ac |
#define CSR_PMPCFG13 0x3ad |
#define CSR_PMPCFG14 0x3ae |
#define CSR_PMPCFG15 0x3af |
#define CSR_PMPCFG2 0x3a2 |
#define CSR_PMPCFG3 0x3a3 |
#define CSR_PMPCFG4 0x3a4 |
#define CSR_PMPCFG5 0x3a5 |
#define CSR_PMPCFG6 0x3a6 |
#define CSR_PMPCFG7 0x3a7 |
#define CSR_PMPCFG8 0x3a8 |
#define CSR_PMPCFG9 0x3a9 |
#define CSR_SATP 0x180 |
#define CSR_SCAUSE 0x142 |
#define CSR_SCONTEXT 0x5a8 |
#define CSR_SCOUNTEREN 0x106 |
#define CSR_SCOUNTOVF 0xda0 |
#define CSR_SEDELEG 0x102 |
#define CSR_SEED 0x015 |
#define CSR_SENVCFG 0x10a |
#define CSR_SEPC 0x141 |
#define CSR_SIDELEG 0x103 |
#define CSR_SIE 0x104 |
#define CSR_SIEH 0x114 |
#define CSR_SIP 0x144 |
#define CSR_SIPH 0x154 |
#define CSR_SIREG 0x151 |
#define CSR_SISELECT 0x150 |
#define CSR_SSCRATCH 0x140 |
#define CSR_SSTATEEN0 0x10c |
#define CSR_SSTATEEN1 0x10d |
#define CSR_SSTATEEN2 0x10e |
#define CSR_SSTATEEN3 0x10f |
#define CSR_SSTATUS 0x100 |
#define CSR_STIMECMP 0x14d |
#define CSR_STIMECMPH 0x15d |
#define CSR_STOPEI 0x15c |
#define CSR_STOPI 0xdb0 |
#define CSR_STVAL 0x143 |
#define CSR_STVEC 0x105 |
#define CSR_TCONTROL 0x7a5 |
#define CSR_TDATA1 0x7a1 |
#define CSR_TDATA2 0x7a2 |
#define CSR_TDATA3 0x7a3 |
#define CSR_TIME 0xc01 |
#define CSR_TIMEH 0xc81 |
#define CSR_TINFO 0x7a4 |
#define CSR_TSELECT 0x7a0 |
#define CSR_UCAUSE 0x42 |
#define CSR_UEPC 0x41 |
#define CSR_UIE 0x4 |
#define CSR_UIP 0x44 |
#define CSR_USCRATCH 0x40 |
#define CSR_USTATUS 0x0 |
#define CSR_UTVAL 0x43 |
#define CSR_UTVEC 0x5 |
#define CSR_VCSR 0x00f |
#define CSR_VL 0xc20 |
#define CSR_VLENB 0xc22 |
#define CSR_VSATP 0x280 |
#define CSR_VSCAUSE 0x242 |
#define CSR_VSEPC 0x241 |
#define CSR_VSIE 0x204 |
#define CSR_VSIEH 0x214 |
#define CSR_VSIP 0x244 |
#define CSR_VSIPH 0x254 |
#define CSR_VSIREG 0x251 |
#define CSR_VSISELECT 0x250 |
#define CSR_VSSCRATCH 0x240 |
#define CSR_VSSTATUS 0x200 |
#define CSR_VSTART 0x008 |
#define CSR_VSTIMECMP 0x24d |
#define CSR_VSTIMECMPH 0x25d |
#define CSR_VSTOPEI 0x25c |
#define CSR_VSTOPI 0xeb0 |
#define CSR_VSTVAL 0x243 |
#define CSR_VSTVEC 0x205 |
#define CSR_VTYPE 0xc21 |
#define CSR_VXRM 0x00a |
#define CSR_VXSAT 0x009 |
#define DECLARE_CSR | ( | name, | |
num, | |||
class, | |||
define_ver, | |||
abort_ver ) |
#define DECLARE_INSN | ( | INSN_NAME, | |
INSN_MATCH, | |||
INSN_MASK ) |
Definition at line 69 of file riscv-tdep.c.
#define MASK_ADD 0xfe00707f |
#define MASK_ADD_UW 0xfe00707f |
#define MASK_ADDI 0x707f |
#define MASK_ADDIW 0x707f |
#define MASK_ADDW 0xfe00707f |
#define MASK_AES32DSI 0x3e00707f |
#define MASK_AES32DSMI 0x3e00707f |
#define MASK_AES32ESI 0x3e00707f |
#define MASK_AES32ESMI 0x3e00707f |
#define MASK_AES64DS 0xfe00707f |
#define MASK_AES64DSM 0xfe00707f |
#define MASK_AES64ES 0xfe00707f |
#define MASK_AES64ESM 0xfe00707f |
#define MASK_AES64IM 0xfff0707f |
#define MASK_AES64KS1I 0xff00707f |
#define MASK_AES64KS2 0xfe00707f |
#define MASK_AMOADD_D 0xf800707f |
#define MASK_AMOADD_W 0xf800707f |
#define MASK_AMOAND_D 0xf800707f |
#define MASK_AMOAND_W 0xf800707f |
#define MASK_AMOMAX_D 0xf800707f |
#define MASK_AMOMAX_W 0xf800707f |
#define MASK_AMOMAXU_D 0xf800707f |
#define MASK_AMOMAXU_W 0xf800707f |
#define MASK_AMOMIN_D 0xf800707f |
#define MASK_AMOMIN_W 0xf800707f |
#define MASK_AMOMINU_D 0xf800707f |
#define MASK_AMOMINU_W 0xf800707f |
#define MASK_AMOOR_D 0xf800707f |
#define MASK_AMOOR_W 0xf800707f |
#define MASK_AMOSWAP_D 0xf800707f |
#define MASK_AMOSWAP_W 0xf800707f |
#define MASK_AMOXOR_D 0xf800707f |
#define MASK_AMOXOR_W 0xf800707f |
#define MASK_AND 0xfe00707f |
#define MASK_ANDI 0x707f |
#define MASK_ANDN 0xfe00707f |
#define MASK_AUIPC 0x7f |
#define MASK_BCLR 0xfe00707f |
#define MASK_BCLRI 0xfc00707f |
#define MASK_BEQ 0x707f |
#define MASK_BEXT 0xfe00707f |
#define MASK_BEXTI 0xfc00707f |
#define MASK_BGE 0x707f |
#define MASK_BGEU 0x707f |
#define MASK_BINV 0xfe00707f |
#define MASK_BINVI 0xfc00707f |
#define MASK_BLT 0x707f |
#define MASK_BLTU 0x707f |
#define MASK_BNE 0x707f |
#define MASK_BSET 0xfe00707f |
#define MASK_BSETI 0xfc00707f |
#define MASK_C_ADD 0xf003 |
#define MASK_C_ADDI 0xe003 |
#define MASK_C_ADDI16SP 0xef83 |
#define MASK_C_ADDI4SPN 0xe003 |
#define MASK_C_ADDIW 0xe003 |
#define MASK_C_ADDW 0xfc63 |
#define MASK_C_AND 0xfc63 |
#define MASK_C_ANDI 0xec03 |
#define MASK_C_BEQZ 0xe003 |
#define MASK_C_BNEZ 0xe003 |
#define MASK_C_EBREAK 0xffff |
#define MASK_C_FLD 0xe003 |
#define MASK_C_FLDSP 0xe003 |
#define MASK_C_FLW 0xe003 |
#define MASK_C_FLWSP 0xe003 |
#define MASK_C_FSD 0xe003 |
#define MASK_C_FSDSP 0xe003 |
#define MASK_C_FSW 0xe003 |
#define MASK_C_FSWSP 0xe003 |
#define MASK_C_J 0xe003 |
#define MASK_C_JAL 0xe003 |
#define MASK_C_JALR 0xf07f |
#define MASK_C_JR 0xf07f |
#define MASK_C_LBU 0xfc03 |
#define MASK_C_LD 0xe003 |
#define MASK_C_LDSP 0xe003 |
#define MASK_C_LH 0xfc43 |
#define MASK_C_LHU 0xfc43 |
#define MASK_C_LI 0xe003 |
#define MASK_C_LUI 0xe003 |
#define MASK_C_LW 0xe003 |
#define MASK_C_LWSP 0xe003 |
#define MASK_C_MUL 0xfc63 |
#define MASK_C_MV 0xf003 |
#define MASK_C_NOP 0xffff |
#define MASK_C_NOT 0xfc7f |
#define MASK_C_NTL_ALL 0xffff |
#define MASK_C_NTL_P1 0xffff |
#define MASK_C_NTL_PALL 0xffff |
#define MASK_C_NTL_S1 0xffff |
#define MASK_C_OR 0xfc63 |
#define MASK_C_SB 0xfc03 |
#define MASK_C_SD 0xe003 |
#define MASK_C_SDSP 0xe003 |
#define MASK_C_SEXT_B 0xfc7f |
#define MASK_C_SEXT_H 0xfc7f |
#define MASK_C_SH 0xfc43 |
#define MASK_C_SLLI 0xe003 |
#define MASK_C_SLLI64 0xf07f |
#define MASK_C_SRAI 0xec03 |
#define MASK_C_SRAI64 0xfc7f |
#define MASK_C_SRLI 0xec03 |
#define MASK_C_SRLI64 0xfc7f |
#define MASK_C_SUB 0xfc63 |
#define MASK_C_SUBW 0xfc63 |
#define MASK_C_SW 0xe003 |
#define MASK_C_SWSP 0xe003 |
#define MASK_C_XOR 0xfc63 |
#define MASK_C_ZEXT_B 0xfc7f |
#define MASK_C_ZEXT_H 0xfc7f |
#define MASK_C_ZEXT_W 0xfc7f |
#define MASK_CBO_CLEAN 0xfff07fff |
#define MASK_CBO_FLUSH 0xfff07fff |
#define MASK_CBO_INVAL 0xfff07fff |
#define MASK_CBO_ZERO 0xfff07fff |
#define MASK_CLMUL 0xfe00707f |
#define MASK_CLMULH 0xfe00707f |
#define MASK_CLMULR 0xfe00707f |
#define MASK_CLZ 0xfff0707f |
#define MASK_CLZW 0xfff0707f |
#define MASK_CPOP 0xfff0707f |
#define MASK_CPOPW 0xfff0707f |
#define MASK_CSRRC 0x707f |
#define MASK_CSRRCI 0x707f |
#define MASK_CSRRS 0x707f |
#define MASK_CSRRSI 0x707f |
#define MASK_CSRRW 0x707f |
#define MASK_CSRRWI 0x707f |
#define MASK_CTZ 0xfff0707f |
#define MASK_CTZW 0xfff0707f |
#define MASK_CZERO_EQZ 0xfe00707f |
#define MASK_CZERO_NEZ 0xfe00707f |
#define MASK_DIV 0xfe00707f |
#define MASK_DIVU 0xfe00707f |
#define MASK_DIVUW 0xfe00707f |
#define MASK_DIVW 0xfe00707f |
#define MASK_DRET 0xffffffff |
#define MASK_EBREAK 0xffffffff |
#define MASK_ECALL 0xffffffff |
#define MASK_FADD_D 0xfe00007f |
#define MASK_FADD_H 0xfe00007f |
#define MASK_FADD_Q 0xfe00007f |
#define MASK_FADD_S 0xfe00007f |
#define MASK_FCLASS_D 0xfff0707f |
#define MASK_FCLASS_H 0xfff0707f |
#define MASK_FCLASS_Q 0xfff0707f |
#define MASK_FCLASS_S 0xfff0707f |
#define MASK_FCVT_D_H 0xfff0007f |
#define MASK_FCVT_D_L 0xfff0007f |
#define MASK_FCVT_D_LU 0xfff0007f |
#define MASK_FCVT_D_Q 0xfff0007f |
#define MASK_FCVT_D_S 0xfff0007f |
#define MASK_FCVT_D_W 0xfff0007f |
#define MASK_FCVT_D_WU 0xfff0007f |
#define MASK_FCVT_H_D 0xfff0007f |
#define MASK_FCVT_H_L 0xfff0007f |
#define MASK_FCVT_H_LU 0xfff0007f |
#define MASK_FCVT_H_Q 0xfff0007f |
#define MASK_FCVT_H_S 0xfff0007f |
#define MASK_FCVT_H_W 0xfff0007f |
#define MASK_FCVT_H_WU 0xfff0007f |
#define MASK_FCVT_L_D 0xfff0007f |
#define MASK_FCVT_L_H 0xfff0007f |
#define MASK_FCVT_L_Q 0xfff0007f |
#define MASK_FCVT_L_S 0xfff0007f |
#define MASK_FCVT_LU_D 0xfff0007f |
#define MASK_FCVT_LU_H 0xfff0007f |
#define MASK_FCVT_LU_Q 0xfff0007f |
#define MASK_FCVT_LU_S 0xfff0007f |
#define MASK_FCVT_Q_D 0xfff0007f |
#define MASK_FCVT_Q_H 0xfff0007f |
#define MASK_FCVT_Q_L 0xfff0007f |
#define MASK_FCVT_Q_LU 0xfff0007f |
#define MASK_FCVT_Q_S 0xfff0007f |
#define MASK_FCVT_Q_W 0xfff0007f |
#define MASK_FCVT_Q_WU 0xfff0007f |
#define MASK_FCVT_S_D 0xfff0007f |
#define MASK_FCVT_S_H 0xfff0007f |
#define MASK_FCVT_S_L 0xfff0007f |
#define MASK_FCVT_S_LU 0xfff0007f |
#define MASK_FCVT_S_Q 0xfff0007f |
#define MASK_FCVT_S_W 0xfff0007f |
#define MASK_FCVT_S_WU 0xfff0007f |
#define MASK_FCVT_W_D 0xfff0007f |
#define MASK_FCVT_W_H 0xfff0007f |
#define MASK_FCVT_W_Q 0xfff0007f |
#define MASK_FCVT_W_S 0xfff0007f |
#define MASK_FCVT_WU_D 0xfff0007f |
#define MASK_FCVT_WU_H 0xfff0007f |
#define MASK_FCVT_WU_Q 0xfff0007f |
#define MASK_FCVT_WU_S 0xfff0007f |
#define MASK_FCVTMOD_W_D 0xfff0707f |
#define MASK_FDIV_D 0xfe00007f |
#define MASK_FDIV_H 0xfe00007f |
#define MASK_FDIV_Q 0xfe00007f |
#define MASK_FDIV_S 0xfe00007f |
#define MASK_FENCE 0x707f |
#define MASK_FENCE_I 0x707f |
#define MASK_FENCE_TSO 0xfff0707f |
#define MASK_FEQ_D 0xfe00707f |
#define MASK_FEQ_H 0xfe00707f |
#define MASK_FEQ_Q 0xfe00707f |
#define MASK_FEQ_S 0xfe00707f |
#define MASK_FLD 0x707f |
#define MASK_FLE_D 0xfe00707f |
#define MASK_FLE_H 0xfe00707f |
#define MASK_FLE_Q 0xfe00707f |
#define MASK_FLE_S 0xfe00707f |
#define MASK_FLEQ_D 0xfe00707f |
#define MASK_FLEQ_H 0xfe00707f |
#define MASK_FLEQ_Q 0xfe00707f |
#define MASK_FLEQ_S 0xfe00707f |
#define MASK_FLH 0x707f |
#define MASK_FLI_D 0xfff0707f |
#define MASK_FLI_H 0xfff0707f |
#define MASK_FLI_Q 0xfff0707f |
#define MASK_FLI_S 0xfff0707f |
#define MASK_FLQ 0x707f |
#define MASK_FLT_D 0xfe00707f |
#define MASK_FLT_H 0xfe00707f |
#define MASK_FLT_Q 0xfe00707f |
#define MASK_FLT_S 0xfe00707f |
#define MASK_FLTQ_D 0xfe00707f |
#define MASK_FLTQ_H 0xfe00707f |
#define MASK_FLTQ_Q 0xfe00707f |
#define MASK_FLTQ_S 0xfe00707f |
#define MASK_FLW 0x707f |
#define MASK_FMADD_D 0x600007f |
#define MASK_FMADD_H 0x600007f |
#define MASK_FMADD_Q 0x600007f |
#define MASK_FMADD_S 0x600007f |
#define MASK_FMAX_D 0xfe00707f |
#define MASK_FMAX_H 0xfe00707f |
#define MASK_FMAX_Q 0xfe00707f |
#define MASK_FMAX_S 0xfe00707f |
#define MASK_FMAXM_D 0xfe00707f |
#define MASK_FMAXM_H 0xfe00707f |
#define MASK_FMAXM_Q 0xfe00707f |
#define MASK_FMAXM_S 0xfe00707f |
#define MASK_FMIN_D 0xfe00707f |
#define MASK_FMIN_H 0xfe00707f |
#define MASK_FMIN_Q 0xfe00707f |
#define MASK_FMIN_S 0xfe00707f |
#define MASK_FMINM_D 0xfe00707f |
#define MASK_FMINM_H 0xfe00707f |
#define MASK_FMINM_Q 0xfe00707f |
#define MASK_FMINM_S 0xfe00707f |
#define MASK_FMSUB_D 0x600007f |
#define MASK_FMSUB_H 0x600007f |
#define MASK_FMSUB_Q 0x600007f |
#define MASK_FMSUB_S 0x600007f |
#define MASK_FMUL_D 0xfe00007f |
#define MASK_FMUL_H 0xfe00007f |
#define MASK_FMUL_Q 0xfe00007f |
#define MASK_FMUL_S 0xfe00007f |
#define MASK_FMV_D_X 0xfff0707f |
#define MASK_FMV_H_X 0xfff0707f |
#define MASK_FMV_S_X 0xfff0707f |
#define MASK_FMV_X_D 0xfff0707f |
#define MASK_FMV_X_H 0xfff0707f |
#define MASK_FMV_X_S 0xfff0707f |
#define MASK_FMVH_X_D 0xfff0707f |
#define MASK_FMVH_X_Q 0xfff0707f |
#define MASK_FMVP_D_X 0xfe00707f |
#define MASK_FMVP_Q_X 0xfe00707f |
#define MASK_FNMADD_D 0x600007f |
#define MASK_FNMADD_H 0x600007f |
#define MASK_FNMADD_Q 0x600007f |
#define MASK_FNMADD_S 0x600007f |
#define MASK_FNMSUB_D 0x600007f |
#define MASK_FNMSUB_H 0x600007f |
#define MASK_FNMSUB_Q 0x600007f |
#define MASK_FNMSUB_S 0x600007f |
#define MASK_FRCSR 0xfffff07f |
#define MASK_FRFLAGS 0xfffff07f |
#define MASK_FROUND_D 0xfff0007f |
#define MASK_FROUND_H 0xfff0007f |
#define MASK_FROUND_Q 0xfff0007f |
#define MASK_FROUND_S 0xfff0007f |
#define MASK_FROUNDNX_D 0xfff0007f |
#define MASK_FROUNDNX_H 0xfff0007f |
#define MASK_FROUNDNX_Q 0xfff0007f |
#define MASK_FROUNDNX_S 0xfff0007f |
#define MASK_FRRM 0xfffff07f |
#define MASK_FSCSR 0xfff0707f |
#define MASK_FSD 0x707f |
#define MASK_FSFLAGS 0xfff0707f |
#define MASK_FSFLAGSI 0xfff0707f |
#define MASK_FSGNJ_D 0xfe00707f |
#define MASK_FSGNJ_H 0xfe00707f |
#define MASK_FSGNJ_Q 0xfe00707f |
#define MASK_FSGNJ_S 0xfe00707f |
#define MASK_FSGNJN_D 0xfe00707f |
#define MASK_FSGNJN_H 0xfe00707f |
#define MASK_FSGNJN_Q 0xfe00707f |
#define MASK_FSGNJN_S 0xfe00707f |
#define MASK_FSGNJX_D 0xfe00707f |
#define MASK_FSGNJX_H 0xfe00707f |
#define MASK_FSGNJX_Q 0xfe00707f |
#define MASK_FSGNJX_S 0xfe00707f |
#define MASK_FSH 0x707f |
#define MASK_FSQ 0x707f |
#define MASK_FSQRT_D 0xfff0007f |
#define MASK_FSQRT_H 0xfff0007f |
#define MASK_FSQRT_Q 0xfff0007f |
#define MASK_FSQRT_S 0xfff0007f |
#define MASK_FSRM 0xfff0707f |
#define MASK_FSRMI 0xfff0707f |
#define MASK_FSUB_D 0xfe00007f |
#define MASK_FSUB_H 0xfe00007f |
#define MASK_FSUB_Q 0xfe00007f |
#define MASK_FSUB_S 0xfe00007f |
#define MASK_FSW 0x707f |
#define MASK_GORCI 0xfc00707f |
#define MASK_GREVI 0xfc00707f |
#define MASK_HFENCE_GVMA 0xfe007fff |
#define MASK_HFENCE_VVMA 0xfe007fff |
#define MASK_HINVAL_GVMA 0xfe007fff |
#define MASK_HINVAL_VVMA 0xfe007fff |
#define MASK_HLV_B 0xfff0707f |
#define MASK_HLV_BU 0xfff0707f |
#define MASK_HLV_D 0xfff0707f |
#define MASK_HLV_H 0xfff0707f |
#define MASK_HLV_HU 0xfff0707f |
#define MASK_HLV_W 0xfff0707f |
#define MASK_HLV_WU 0xfff0707f |
#define MASK_HLVX_HU 0xfff0707f |
#define MASK_HLVX_WU 0xfff0707f |
#define MASK_HRET 0xffffffff |
#define MASK_HSV_B 0xfe007fff |
#define MASK_HSV_D 0xfe007fff |
#define MASK_HSV_H 0xfe007fff |
#define MASK_HSV_W 0xfe007fff |
#define MASK_JAL 0x7f |
#define MASK_JALR 0x707f |
#define MASK_LB 0x707f |
#define MASK_LBU 0x707f |
#define MASK_LD 0x707f |
#define MASK_LH 0x707f |
#define MASK_LHU 0x707f |
#define MASK_LR_D 0xf9f0707f |
#define MASK_LR_W 0xf9f0707f |
#define MASK_LUI 0x7f |
#define MASK_LW 0x707f |
#define MASK_LWU 0x707f |
#define MASK_MAX 0xfe00707f |
#define MASK_MAXU 0xfe00707f |
#define MASK_MIN 0xfe00707f |
#define MASK_MINU 0xfe00707f |
#define MASK_MRET 0xffffffff |
#define MASK_MUL 0xfe00707f |
#define MASK_MULH 0xfe00707f |
#define MASK_MULHSU 0xfe00707f |
#define MASK_MULHU 0xfe00707f |
#define MASK_MULW 0xfe00707f |
#define MASK_NTL_ALL 0xffffffff |
#define MASK_NTL_P1 0xffffffff |
#define MASK_NTL_PALL 0xffffffff |
#define MASK_NTL_S1 0xffffffff |
#define MASK_OR 0xfe00707f |
#define MASK_ORI 0x707f |
#define MASK_ORN 0xfe00707f |
#define MASK_PACK 0xfe00707f |
#define MASK_PACKH 0xfe00707f |
#define MASK_PACKW 0xfe00707f |
#define MASK_PAUSE 0xffffffff |
#define MASK_PREFETCH_I 0x1f07fff |
#define MASK_PREFETCH_R 0x1f07fff |
#define MASK_PREFETCH_W 0x1f07fff |
#define MASK_RDCYCLE 0xfffff07f |
#define MASK_RDCYCLEH 0xfffff07f |
#define MASK_RDINSTRET 0xfffff07f |
#define MASK_RDINSTRETH 0xfffff07f |
#define MASK_RDTIME 0xfffff07f |
#define MASK_RDTIMEH 0xfffff07f |
#define MASK_REM 0xfe00707f |
#define MASK_REMU 0xfe00707f |
#define MASK_REMUW 0xfe00707f |
#define MASK_REMW 0xfe00707f |
#define MASK_ROL 0xfe00707f |
#define MASK_ROLW 0xfe00707f |
#define MASK_ROR 0xfe00707f |
#define MASK_RORI 0xfc00707f |
#define MASK_RORIW 0xfe00707f |
#define MASK_RORW 0xfe00707f |
#define MASK_SB 0x707f |
#define MASK_SBREAK 0xffffffff |
#define MASK_SC_D 0xf800707f |
#define MASK_SC_W 0xf800707f |
#define MASK_SCALL 0xffffffff |
#define MASK_SD 0x707f |
#define MASK_SEXT_B 0xfff0707f |
#define MASK_SEXT_H 0xfff0707f |
#define MASK_SFENCE_INVAL_IR 0xffffffff |
#define MASK_SFENCE_VM 0xfff07fff |
#define MASK_SFENCE_VMA 0xfe007fff |
#define MASK_SFENCE_W_INVAL 0xffffffff |
#define MASK_SH 0x707f |
#define MASK_SH1ADD 0xfe00707f |
#define MASK_SH1ADD_UW 0xfe00707f |
#define MASK_SH2ADD 0xfe00707f |
#define MASK_SH2ADD_UW 0xfe00707f |
#define MASK_SH3ADD 0xfe00707f |
#define MASK_SH3ADD_UW 0xfe00707f |
#define MASK_SHA256SIG0 0xfff0707f |
#define MASK_SHA256SIG1 0xfff0707f |
#define MASK_SHA256SUM0 0xfff0707f |
#define MASK_SHA256SUM1 0xfff0707f |
#define MASK_SHA512SIG0 0xfff0707f |
#define MASK_SHA512SIG0H 0xfe00707f |
#define MASK_SHA512SIG0L 0xfe00707f |
#define MASK_SHA512SIG1 0xfff0707f |
#define MASK_SHA512SIG1H 0xfe00707f |
#define MASK_SHA512SIG1L 0xfe00707f |
#define MASK_SHA512SUM0 0xfff0707f |
#define MASK_SHA512SUM0R 0xfe00707f |
#define MASK_SHA512SUM1 0xfff0707f |
#define MASK_SHA512SUM1R 0xfe00707f |
#define MASK_SHFLI 0xfe00707f |
#define MASK_SINVAL_VMA 0xfe007fff |
#define MASK_SLL 0xfe00707f |
#define MASK_SLLI 0xfc00707f |
#define MASK_SLLI_RV32 0xfe00707f |
#define MASK_SLLI_UW 0xfc00707f |
#define MASK_SLLIW 0xfe00707f |
#define MASK_SLLW 0xfe00707f |
#define MASK_SLT 0xfe00707f |
#define MASK_SLTI 0x707f |
#define MASK_SLTIU 0x707f |
#define MASK_SLTU 0xfe00707f |
#define MASK_SM3P0 0xfff0707f |
#define MASK_SM3P1 0xfff0707f |
#define MASK_SM4ED 0x3e00707f |
#define MASK_SM4KS 0x3e00707f |
#define MASK_SRA 0xfe00707f |
#define MASK_SRAI 0xfc00707f |
#define MASK_SRAI_RV32 0xfe00707f |
#define MASK_SRAIW 0xfe00707f |
#define MASK_SRAW 0xfe00707f |
#define MASK_SRET 0xffffffff |
#define MASK_SRL 0xfe00707f |
#define MASK_SRLI 0xfc00707f |
#define MASK_SRLI_RV32 0xfe00707f |
#define MASK_SRLIW 0xfe00707f |
#define MASK_SRLW 0xfe00707f |
#define MASK_SUB 0xfe00707f |
#define MASK_SUBW 0xfe00707f |
#define MASK_SW 0x707f |
#define MASK_TH_ADDSL 0xf800707f |
#define MASK_TH_DCACHE_CALL 0xffffffff |
#define MASK_TH_DCACHE_CIALL 0xffffffff |
#define MASK_TH_DCACHE_CIPA 0xfff07fff |
#define MASK_TH_DCACHE_CISW 0xfff07fff |
#define MASK_TH_DCACHE_CIVA 0xfff07fff |
#define MASK_TH_DCACHE_CPA 0xfff07fff |
#define MASK_TH_DCACHE_CPAL1 0xfff07fff |
#define MASK_TH_DCACHE_CSW 0xfff07fff |
#define MASK_TH_DCACHE_CVA 0xfff07fff |
#define MASK_TH_DCACHE_CVAL1 0xfff07fff |
#define MASK_TH_DCACHE_IALL 0xffffffff |
#define MASK_TH_DCACHE_IPA 0xfff07fff |
#define MASK_TH_DCACHE_ISW 0xfff07fff |
#define MASK_TH_DCACHE_IVA 0xfff07fff |
#define MASK_TH_EXT 0x0000707f |
#define MASK_TH_EXTU 0x0000707f |
#define MASK_TH_FF0 0xfff0707f |
#define MASK_TH_FF1 0xfff0707f |
#define MASK_TH_FLRD 0xf800707f |
#define MASK_TH_FLRW 0xf800707f |
#define MASK_TH_FLURD 0xf800707f |
#define MASK_TH_FLURW 0xf800707f |
#define MASK_TH_FMV_HW_X 0xfff0707f |
#define MASK_TH_FMV_X_HW 0xfff0707f |
#define MASK_TH_FSRD 0xf800707f |
#define MASK_TH_FSRW 0xf800707f |
#define MASK_TH_FSURD 0xf800707f |
#define MASK_TH_FSURW 0xf800707f |
#define MASK_TH_ICACHE_IALL 0xffffffff |
#define MASK_TH_ICACHE_IALLS 0xffffffff |
#define MASK_TH_ICACHE_IPA 0xfff07fff |
#define MASK_TH_ICACHE_IVA 0xfff07fff |
#define MASK_TH_IPOP 0xffffffff |
#define MASK_TH_IPUSH 0xffffffff |
#define MASK_TH_L2CACHE_CALL 0xffffffff |
#define MASK_TH_L2CACHE_CIALL 0xffffffff |
#define MASK_TH_L2CACHE_IALL 0xffffffff |
#define MASK_TH_LBIA 0xf800707f |
#define MASK_TH_LBIB 0xf800707f |
#define MASK_TH_LBUIA 0xf800707f |
#define MASK_TH_LBUIB 0xf800707f |
#define MASK_TH_LDD 0xf800707f |
#define MASK_TH_LDIA 0xf800707f |
#define MASK_TH_LDIB 0xf800707f |
#define MASK_TH_LHIA 0xf800707f |
#define MASK_TH_LHIB 0xf800707f |
#define MASK_TH_LHUIA 0xf800707f |
#define MASK_TH_LHUIB 0xf800707f |
#define MASK_TH_LRB 0xf800707f |
#define MASK_TH_LRBU 0xf800707f |
#define MASK_TH_LRD 0xf800707f |
#define MASK_TH_LRH 0xf800707f |
#define MASK_TH_LRHU 0xf800707f |
#define MASK_TH_LRW 0xf800707f |
#define MASK_TH_LRWU 0xf800707f |
#define MASK_TH_LURB 0xf800707f |
#define MASK_TH_LURBU 0xf800707f |
#define MASK_TH_LURD 0xf800707f |
#define MASK_TH_LURH 0xf800707f |
#define MASK_TH_LURHU 0xf800707f |
#define MASK_TH_LURW 0xf800707f |
#define MASK_TH_LURWU 0xf800707f |
#define MASK_TH_LWD 0xf800707f |
#define MASK_TH_LWIA 0xf800707f |
#define MASK_TH_LWIB 0xf800707f |
#define MASK_TH_LWUD 0xf800707f |
#define MASK_TH_LWUIA 0xf800707f |
#define MASK_TH_LWUIB 0xf800707f |
#define MASK_TH_MULA 0xfe00707f |
#define MASK_TH_MULAH 0xfe00707f |
#define MASK_TH_MULAW 0xfe00707f |
#define MASK_TH_MULS 0xfe00707f |
#define MASK_TH_MULSH 0xfe00707f |
#define MASK_TH_MULSW 0xfe00707f |
#define MASK_TH_MVEQZ 0xfe00707f |
#define MASK_TH_MVNEZ 0xfe00707f |
#define MASK_TH_REV 0xfff0707f |
#define MASK_TH_REVW 0xfff0707f |
#define MASK_TH_SBIA 0xf800707f |
#define MASK_TH_SBIB 0xf800707f |
#define MASK_TH_SDD 0xf800707f |
#define MASK_TH_SDIA 0xf800707f |
#define MASK_TH_SDIB 0xf800707f |
#define MASK_TH_SFENCE_VMAS 0xfe007fff |
#define MASK_TH_SHIA 0xf800707f |
#define MASK_TH_SHIB 0xf800707f |
#define MASK_TH_SRB 0xf800707f |
#define MASK_TH_SRD 0xf800707f |
#define MASK_TH_SRH 0xf800707f |
#define MASK_TH_SRRI 0xfc00707f |
#define MASK_TH_SRRIW 0xfe00707f |
#define MASK_TH_SRW 0xf800707f |
#define MASK_TH_SURB 0xf800707f |
#define MASK_TH_SURD 0xf800707f |
#define MASK_TH_SURH 0xf800707f |
#define MASK_TH_SURW 0xf800707f |
#define MASK_TH_SWD 0xf800707f |
#define MASK_TH_SWIA 0xf800707f |
#define MASK_TH_SWIB 0xf800707f |
#define MASK_TH_SYNC 0xffffffff |
#define MASK_TH_SYNC_I 0xffffffff |
#define MASK_TH_SYNC_IS 0xffffffff |
#define MASK_TH_SYNC_S 0xffffffff |
#define MASK_TH_TST 0xfc00707f |
#define MASK_TH_TSTNBZ 0xfff0707f |
#define MASK_UNSHFLI 0xfe00707f |
#define MASK_URET 0xffffffff |
#define MASK_VAADDUVV 0xfc00707f |
#define MASK_VAADDUVX 0xfc00707f |
#define MASK_VAADDVV 0xfc00707f |
#define MASK_VAADDVX 0xfc00707f |
#define MASK_VADCVIM 0xfe00707f |
#define MASK_VADCVVM 0xfe00707f |
#define MASK_VADCVXM 0xfe00707f |
#define MASK_VADDVI 0xfc00707f |
#define MASK_VADDVV 0xfc00707f |
#define MASK_VADDVX 0xfc00707f |
#define MASK_VAESDF_VS 0xfe0ff07f |
#define MASK_VAESDF_VV 0xfe0ff07f |
#define MASK_VAESDM_VS 0xfe0ff07f |
#define MASK_VAESDM_VV 0xfe0ff07f |
#define MASK_VAESEF_VS 0xfe0ff07f |
#define MASK_VAESEF_VV 0xfe0ff07f |
#define MASK_VAESEM_VS 0xfe0ff07f |
#define MASK_VAESEM_VV 0xfe0ff07f |
#define MASK_VAESKF1_VI 0xfe00707f |
#define MASK_VAESKF2_VI 0xfe00707f |
#define MASK_VAESZ_VS 0xfe0ff07f |
#define MASK_VANDN_VV 0xfc00707f |
#define MASK_VANDN_VX 0xfc00707f |
#define MASK_VANDVI 0xfc00707f |
#define MASK_VANDVV 0xfc00707f |
#define MASK_VANDVX 0xfc00707f |
#define MASK_VASUBUVV 0xfc00707f |
#define MASK_VASUBUVX 0xfc00707f |
#define MASK_VASUBVV 0xfc00707f |
#define MASK_VASUBVX 0xfc00707f |
#define MASK_VBREV8_V 0xfc0ff07f |
#define MASK_VBREV_V 0xfc0ff07f |
#define MASK_VCLMUL_VV 0xfc00707f |
#define MASK_VCLMUL_VX 0xfc00707f |
#define MASK_VCLMULH_VV 0xfc00707f |
#define MASK_VCLMULH_VX 0xfc00707f |
#define MASK_VCLZ_V 0xfc0ff07f |
#define MASK_VCOMPRESSVM 0xfe00707f |
#define MASK_VCPOP_V 0xfc0ff07f |
#define MASK_VCPOPM 0xfc0ff07f |
#define MASK_VCTZ_V 0xfc0ff07f |
#define MASK_VDIVUVV 0xfc00707f |
#define MASK_VDIVUVX 0xfc00707f |
#define MASK_VDIVVV 0xfc00707f |
#define MASK_VDIVVX 0xfc00707f |
#define MASK_VDOTUVV 0xfc00707f |
#define MASK_VDOTVV 0xfc00707f |
#define MASK_VFADDVF 0xfc00707f |
#define MASK_VFADDVV 0xfc00707f |
#define MASK_VFCLASSV 0xfc0ff07f |
#define MASK_VFCVTFXUV 0xfc0ff07f |
#define MASK_VFCVTFXV 0xfc0ff07f |
#define MASK_VFCVTRTZXFV 0xfc0ff07f |
#define MASK_VFCVTRTZXUFV 0xfc0ff07f |
#define MASK_VFCVTXFV 0xfc0ff07f |
#define MASK_VFCVTXUFV 0xfc0ff07f |
#define MASK_VFDIVVF 0xfc00707f |
#define MASK_VFDIVVV 0xfc00707f |
#define MASK_VFDOTVV 0xfc00707f |
#define MASK_VFIRSTM 0xfc0ff07f |
#define MASK_VFMACCVF 0xfc00707f |
#define MASK_VFMACCVV 0xfc00707f |
#define MASK_VFMADDVF 0xfc00707f |
#define MASK_VFMADDVV 0xfc00707f |
#define MASK_VFMAXVF 0xfc00707f |
#define MASK_VFMAXVV 0xfc00707f |
#define MASK_VFMERGEVFM 0xfe00707f |
#define MASK_VFMINVF 0xfc00707f |
#define MASK_VFMINVV 0xfc00707f |
#define MASK_VFMSACVF 0xfc00707f |
#define MASK_VFMSACVV 0xfc00707f |
#define MASK_VFMSUBVF 0xfc00707f |
#define MASK_VFMSUBVV 0xfc00707f |
#define MASK_VFMULVF 0xfc00707f |
#define MASK_VFMULVV 0xfc00707f |
#define MASK_VFMVFS 0xfe0ff07f |
#define MASK_VFMVSF 0xfff0707f |
#define MASK_VFMVVF 0xfff0707f |
#define MASK_VFNCVTFFW 0xfc0ff07f |
#define MASK_VFNCVTFXUW 0xfc0ff07f |
#define MASK_VFNCVTFXW 0xfc0ff07f |
#define MASK_VFNCVTRODFFW 0xfc0ff07f |
#define MASK_VFNCVTRTZXFW 0xfc0ff07f |
#define MASK_VFNCVTRTZXUFW 0xfc0ff07f |
#define MASK_VFNCVTXFW 0xfc0ff07f |
#define MASK_VFNCVTXUFW 0xfc0ff07f |
#define MASK_VFNMACCVF 0xfc00707f |
#define MASK_VFNMACCVV 0xfc00707f |
#define MASK_VFNMADDVF 0xfc00707f |
#define MASK_VFNMADDVV 0xfc00707f |
#define MASK_VFNMSACVF 0xfc00707f |
#define MASK_VFNMSACVV 0xfc00707f |
#define MASK_VFNMSUBVF 0xfc00707f |
#define MASK_VFNMSUBVV 0xfc00707f |
#define MASK_VFRDIVVF 0xfc00707f |
#define MASK_VFREC7V 0xfc0ff07f |
#define MASK_VFREDMAXVS 0xfc00707f |
#define MASK_VFREDMINVS 0xfc00707f |
#define MASK_VFREDOSUMVS 0xfc00707f |
#define MASK_VFREDUSUMVS 0xfc00707f |
#define MASK_VFRSQRT7V 0xfc0ff07f |
#define MASK_VFRSUBVF 0xfc00707f |
#define MASK_VFSGNJNVF 0xfc00707f |
#define MASK_VFSGNJNVV 0xfc00707f |
#define MASK_VFSGNJVF 0xfc00707f |
#define MASK_VFSGNJVV 0xfc00707f |
#define MASK_VFSGNJXVF 0xfc00707f |
#define MASK_VFSGNJXVV 0xfc00707f |
#define MASK_VFSLIDE1DOWNVF 0xfc00707f |
#define MASK_VFSLIDE1UPVF 0xfc00707f |
#define MASK_VFSQRTV 0xfc0ff07f |
#define MASK_VFSUBVF 0xfc00707f |
#define MASK_VFSUBVV 0xfc00707f |
#define MASK_VFWADDVF 0xfc00707f |
#define MASK_VFWADDVV 0xfc00707f |
#define MASK_VFWADDWF 0xfc00707f |
#define MASK_VFWADDWV 0xfc00707f |
#define MASK_VFWCVTFFV 0xfc0ff07f |
#define MASK_VFWCVTFXUV 0xfc0ff07f |
#define MASK_VFWCVTFXV 0xfc0ff07f |
#define MASK_VFWCVTRTZXFV 0xfc0ff07f |
#define MASK_VFWCVTRTZXUFV 0xfc0ff07f |
#define MASK_VFWCVTXFV 0xfc0ff07f |
#define MASK_VFWCVTXUFV 0xfc0ff07f |
#define MASK_VFWMACCVF 0xfc00707f |
#define MASK_VFWMACCVV 0xfc00707f |
#define MASK_VFWMSACVF 0xfc00707f |
#define MASK_VFWMSACVV 0xfc00707f |
#define MASK_VFWMULVF 0xfc00707f |
#define MASK_VFWMULVV 0xfc00707f |
#define MASK_VFWNMACCVF 0xfc00707f |
#define MASK_VFWNMACCVV 0xfc00707f |
#define MASK_VFWNMSACVF 0xfc00707f |
#define MASK_VFWNMSACVV 0xfc00707f |
#define MASK_VFWREDOSUMVS 0xfc00707f |
#define MASK_VFWREDUSUMVS 0xfc00707f |
#define MASK_VFWSUBVF 0xfc00707f |
#define MASK_VFWSUBVV 0xfc00707f |
#define MASK_VFWSUBWF 0xfc00707f |
#define MASK_VFWSUBWV 0xfc00707f |
#define MASK_VGHSH_VV 0xfe00707f |
#define MASK_VGMUL_VV 0xfe0ff07f |
#define MASK_VIDV 0xfdfff07f |
#define MASK_VIOTAM 0xfc0ff07f |
#define MASK_VL1RE16V 0xfff0707f |
#define MASK_VL1RE32V 0xfff0707f |
#define MASK_VL1RE64V 0xfff0707f |
#define MASK_VL1RE8V 0xfff0707f |
#define MASK_VL2RE16V 0xfff0707f |
#define MASK_VL2RE32V 0xfff0707f |
#define MASK_VL2RE64V 0xfff0707f |
#define MASK_VL2RE8V 0xfff0707f |
#define MASK_VL4RE16V 0xfff0707f |
#define MASK_VL4RE32V 0xfff0707f |
#define MASK_VL4RE64V 0xfff0707f |
#define MASK_VL4RE8V 0xfff0707f |
#define MASK_VL8RE16V 0xfff0707f |
#define MASK_VL8RE32V 0xfff0707f |
#define MASK_VL8RE64V 0xfff0707f |
#define MASK_VL8RE8V 0xfff0707f |
#define MASK_VLE16FFV 0xfdf0707f |
#define MASK_VLE16V 0xfdf0707f |
#define MASK_VLE32FFV 0xfdf0707f |
#define MASK_VLE32V 0xfdf0707f |
#define MASK_VLE64FFV 0xfdf0707f |
#define MASK_VLE64V 0xfdf0707f |
#define MASK_VLE8FFV 0xfdf0707f |
#define MASK_VLE8V 0xfdf0707f |
#define MASK_VLMV 0xfff0707f |
#define MASK_VLOXEI16V 0xfc00707f |
#define MASK_VLOXEI32V 0xfc00707f |
#define MASK_VLOXEI64V 0xfc00707f |
#define MASK_VLOXEI8V 0xfc00707f |
#define MASK_VLOXSEG2EI16V 0xfc00707f |
#define MASK_VLOXSEG2EI32V 0xfc00707f |
#define MASK_VLOXSEG2EI64V 0xfc00707f |
#define MASK_VLOXSEG2EI8V 0xfc00707f |
#define MASK_VLOXSEG3EI16V 0xfc00707f |
#define MASK_VLOXSEG3EI32V 0xfc00707f |
#define MASK_VLOXSEG3EI64V 0xfc00707f |
#define MASK_VLOXSEG3EI8V 0xfc00707f |
#define MASK_VLOXSEG4EI16V 0xfc00707f |
#define MASK_VLOXSEG4EI32V 0xfc00707f |
#define MASK_VLOXSEG4EI64V 0xfc00707f |
#define MASK_VLOXSEG4EI8V 0xfc00707f |
#define MASK_VLOXSEG5EI16V 0xfc00707f |
#define MASK_VLOXSEG5EI32V 0xfc00707f |
#define MASK_VLOXSEG5EI64V 0xfc00707f |
#define MASK_VLOXSEG5EI8V 0xfc00707f |
#define MASK_VLOXSEG6EI16V 0xfc00707f |
#define MASK_VLOXSEG6EI32V 0xfc00707f |
#define MASK_VLOXSEG6EI64V 0xfc00707f |
#define MASK_VLOXSEG6EI8V 0xfc00707f |
#define MASK_VLOXSEG7EI16V 0xfc00707f |
#define MASK_VLOXSEG7EI32V 0xfc00707f |
#define MASK_VLOXSEG7EI64V 0xfc00707f |
#define MASK_VLOXSEG7EI8V 0xfc00707f |
#define MASK_VLOXSEG8EI16V 0xfc00707f |
#define MASK_VLOXSEG8EI32V 0xfc00707f |
#define MASK_VLOXSEG8EI64V 0xfc00707f |
#define MASK_VLOXSEG8EI8V 0xfc00707f |
#define MASK_VLSE16V 0xfc00707f |
#define MASK_VLSE32V 0xfc00707f |
#define MASK_VLSE64V 0xfc00707f |
#define MASK_VLSE8V 0xfc00707f |
#define MASK_VLSEG2E16FFV 0xfdf0707f |
#define MASK_VLSEG2E16V 0xfdf0707f |
#define MASK_VLSEG2E32FFV 0xfdf0707f |
#define MASK_VLSEG2E32V 0xfdf0707f |
#define MASK_VLSEG2E64FFV 0xfdf0707f |
#define MASK_VLSEG2E64V 0xfdf0707f |
#define MASK_VLSEG2E8FFV 0xfdf0707f |
#define MASK_VLSEG2E8V 0xfdf0707f |
#define MASK_VLSEG3E16FFV 0xfdf0707f |
#define MASK_VLSEG3E16V 0xfdf0707f |
#define MASK_VLSEG3E32FFV 0xfdf0707f |
#define MASK_VLSEG3E32V 0xfdf0707f |
#define MASK_VLSEG3E64FFV 0xfdf0707f |
#define MASK_VLSEG3E64V 0xfdf0707f |
#define MASK_VLSEG3E8FFV 0xfdf0707f |
#define MASK_VLSEG3E8V 0xfdf0707f |
#define MASK_VLSEG4E16FFV 0xfdf0707f |
#define MASK_VLSEG4E16V 0xfdf0707f |
#define MASK_VLSEG4E32FFV 0xfdf0707f |
#define MASK_VLSEG4E32V 0xfdf0707f |
#define MASK_VLSEG4E64FFV 0xfdf0707f |
#define MASK_VLSEG4E64V 0xfdf0707f |
#define MASK_VLSEG4E8FFV 0xfdf0707f |
#define MASK_VLSEG4E8V 0xfdf0707f |
#define MASK_VLSEG5E16FFV 0xfdf0707f |
#define MASK_VLSEG5E16V 0xfdf0707f |
#define MASK_VLSEG5E32FFV 0xfdf0707f |
#define MASK_VLSEG5E32V 0xfdf0707f |
#define MASK_VLSEG5E64FFV 0xfdf0707f |
#define MASK_VLSEG5E64V 0xfdf0707f |
#define MASK_VLSEG5E8FFV 0xfdf0707f |
#define MASK_VLSEG5E8V 0xfdf0707f |
#define MASK_VLSEG6E16FFV 0xfdf0707f |
#define MASK_VLSEG6E16V 0xfdf0707f |
#define MASK_VLSEG6E32FFV 0xfdf0707f |
#define MASK_VLSEG6E32V 0xfdf0707f |
#define MASK_VLSEG6E64FFV 0xfdf0707f |
#define MASK_VLSEG6E64V 0xfdf0707f |
#define MASK_VLSEG6E8FFV 0xfdf0707f |
#define MASK_VLSEG6E8V 0xfdf0707f |
#define MASK_VLSEG7E16FFV 0xfdf0707f |
#define MASK_VLSEG7E16V 0xfdf0707f |
#define MASK_VLSEG7E32FFV 0xfdf0707f |
#define MASK_VLSEG7E32V 0xfdf0707f |
#define MASK_VLSEG7E64FFV 0xfdf0707f |
#define MASK_VLSEG7E64V 0xfdf0707f |
#define MASK_VLSEG7E8FFV 0xfdf0707f |
#define MASK_VLSEG7E8V 0xfdf0707f |
#define MASK_VLSEG8E16FFV 0xfdf0707f |
#define MASK_VLSEG8E16V 0xfdf0707f |
#define MASK_VLSEG8E32FFV 0xfdf0707f |
#define MASK_VLSEG8E32V 0xfdf0707f |
#define MASK_VLSEG8E64FFV 0xfdf0707f |
#define MASK_VLSEG8E64V 0xfdf0707f |
#define MASK_VLSEG8E8FFV 0xfdf0707f |
#define MASK_VLSEG8E8V 0xfdf0707f |
#define MASK_VLSSEG2E16V 0xfc00707f |
#define MASK_VLSSEG2E32V 0xfc00707f |
#define MASK_VLSSEG2E64V 0xfc00707f |
#define MASK_VLSSEG2E8V 0xfc00707f |
#define MASK_VLSSEG3E16V 0xfc00707f |
#define MASK_VLSSEG3E32V 0xfc00707f |
#define MASK_VLSSEG3E64V 0xfc00707f |
#define MASK_VLSSEG3E8V 0xfc00707f |
#define MASK_VLSSEG4E16V 0xfc00707f |
#define MASK_VLSSEG4E32V 0xfc00707f |
#define MASK_VLSSEG4E64V 0xfc00707f |
#define MASK_VLSSEG4E8V 0xfc00707f |
#define MASK_VLSSEG5E16V 0xfc00707f |
#define MASK_VLSSEG5E32V 0xfc00707f |
#define MASK_VLSSEG5E64V 0xfc00707f |
#define MASK_VLSSEG5E8V 0xfc00707f |
#define MASK_VLSSEG6E16V 0xfc00707f |
#define MASK_VLSSEG6E32V 0xfc00707f |
#define MASK_VLSSEG6E64V 0xfc00707f |
#define MASK_VLSSEG6E8V 0xfc00707f |
#define MASK_VLSSEG7E16V 0xfc00707f |
#define MASK_VLSSEG7E32V 0xfc00707f |
#define MASK_VLSSEG7E64V 0xfc00707f |
#define MASK_VLSSEG7E8V 0xfc00707f |
#define MASK_VLSSEG8E16V 0xfc00707f |
#define MASK_VLSSEG8E32V 0xfc00707f |
#define MASK_VLSSEG8E64V 0xfc00707f |
#define MASK_VLSSEG8E8V 0xfc00707f |
#define MASK_VLUXEI16V 0xfc00707f |
#define MASK_VLUXEI32V 0xfc00707f |
#define MASK_VLUXEI64V 0xfc00707f |
#define MASK_VLUXEI8V 0xfc00707f |
#define MASK_VLUXSEG2EI16V 0xfc00707f |
#define MASK_VLUXSEG2EI32V 0xfc00707f |
#define MASK_VLUXSEG2EI64V 0xfc00707f |
#define MASK_VLUXSEG2EI8V 0xfc00707f |
#define MASK_VLUXSEG3EI16V 0xfc00707f |
#define MASK_VLUXSEG3EI32V 0xfc00707f |
#define MASK_VLUXSEG3EI64V 0xfc00707f |
#define MASK_VLUXSEG3EI8V 0xfc00707f |
#define MASK_VLUXSEG4EI16V 0xfc00707f |
#define MASK_VLUXSEG4EI32V 0xfc00707f |
#define MASK_VLUXSEG4EI64V 0xfc00707f |
#define MASK_VLUXSEG4EI8V 0xfc00707f |
#define MASK_VLUXSEG5EI16V 0xfc00707f |
#define MASK_VLUXSEG5EI32V 0xfc00707f |
#define MASK_VLUXSEG5EI64V 0xfc00707f |
#define MASK_VLUXSEG5EI8V 0xfc00707f |
#define MASK_VLUXSEG6EI16V 0xfc00707f |
#define MASK_VLUXSEG6EI32V 0xfc00707f |
#define MASK_VLUXSEG6EI64V 0xfc00707f |
#define MASK_VLUXSEG6EI8V 0xfc00707f |
#define MASK_VLUXSEG7EI16V 0xfc00707f |
#define MASK_VLUXSEG7EI32V 0xfc00707f |
#define MASK_VLUXSEG7EI64V 0xfc00707f |
#define MASK_VLUXSEG7EI8V 0xfc00707f |
#define MASK_VLUXSEG8EI16V 0xfc00707f |
#define MASK_VLUXSEG8EI32V 0xfc00707f |
#define MASK_VLUXSEG8EI64V 0xfc00707f |
#define MASK_VLUXSEG8EI8V 0xfc00707f |
#define MASK_VMACCVV 0xfc00707f |
#define MASK_VMACCVX 0xfc00707f |
#define MASK_VMADCVI 0xfe00707f |
#define MASK_VMADCVIM 0xfe00707f |
#define MASK_VMADCVV 0xfe00707f |
#define MASK_VMADCVVM 0xfe00707f |
#define MASK_VMADCVX 0xfe00707f |
#define MASK_VMADCVXM 0xfe00707f |
#define MASK_VMADDVV 0xfc00707f |
#define MASK_VMADDVX 0xfc00707f |
#define MASK_VMANDMM 0xfe00707f |
#define MASK_VMANDNMM 0xfe00707f |
#define MASK_VMAXUVV 0xfc00707f |
#define MASK_VMAXUVX 0xfc00707f |
#define MASK_VMAXVV 0xfc00707f |
#define MASK_VMAXVX 0xfc00707f |
#define MASK_VMERGEVIM 0xfe00707f |
#define MASK_VMERGEVVM 0xfe00707f |
#define MASK_VMERGEVXM 0xfe00707f |
#define MASK_VMFEQVF 0xfc00707f |
#define MASK_VMFEQVV 0xfc00707f |
#define MASK_VMFGEVF 0xfc00707f |
#define MASK_VMFGTVF 0xfc00707f |
#define MASK_VMFLEVF 0xfc00707f |
#define MASK_VMFLEVV 0xfc00707f |
#define MASK_VMFLTVF 0xfc00707f |
#define MASK_VMFLTVV 0xfc00707f |
#define MASK_VMFNEVF 0xfc00707f |
#define MASK_VMFNEVV 0xfc00707f |
#define MASK_VMINUVV 0xfc00707f |
#define MASK_VMINUVX 0xfc00707f |
#define MASK_VMINVV 0xfc00707f |
#define MASK_VMINVX 0xfc00707f |
#define MASK_VMNANDMM 0xfe00707f |
#define MASK_VMNORMM 0xfe00707f |
#define MASK_VMORMM 0xfe00707f |
#define MASK_VMORNMM 0xfe00707f |
#define MASK_VMSBCVV 0xfe00707f |
#define MASK_VMSBCVVM 0xfe00707f |
#define MASK_VMSBCVX 0xfe00707f |
#define MASK_VMSBCVXM 0xfe00707f |
#define MASK_VMSBFM 0xfc0ff07f |
#define MASK_VMSEQVI 0xfc00707f |
#define MASK_VMSEQVV 0xfc00707f |
#define MASK_VMSEQVX 0xfc00707f |
#define MASK_VMSGTUVI 0xfc00707f |
#define MASK_VMSGTUVX 0xfc00707f |
#define MASK_VMSGTVI 0xfc00707f |
#define MASK_VMSGTVX 0xfc00707f |
#define MASK_VMSIFM 0xfc0ff07f |
#define MASK_VMSLEUVI 0xfc00707f |
#define MASK_VMSLEUVV 0xfc00707f |
#define MASK_VMSLEUVX 0xfc00707f |
#define MASK_VMSLEVI 0xfc00707f |
#define MASK_VMSLEVV 0xfc00707f |
#define MASK_VMSLEVX 0xfc00707f |
#define MASK_VMSLTUVV 0xfc00707f |
#define MASK_VMSLTUVX 0xfc00707f |
#define MASK_VMSLTVV 0xfc00707f |
#define MASK_VMSLTVX 0xfc00707f |
#define MASK_VMSNEVI 0xfc00707f |
#define MASK_VMSNEVV 0xfc00707f |
#define MASK_VMSNEVX 0xfc00707f |
#define MASK_VMSOFM 0xfc0ff07f |
#define MASK_VMULHSUVV 0xfc00707f |
#define MASK_VMULHSUVX 0xfc00707f |
#define MASK_VMULHUVV 0xfc00707f |
#define MASK_VMULHUVX 0xfc00707f |
#define MASK_VMULHVV 0xfc00707f |
#define MASK_VMULHVX 0xfc00707f |
#define MASK_VMULVV 0xfc00707f |
#define MASK_VMULVX 0xfc00707f |
#define MASK_VMV1RV 0xfe0ff07f |
#define MASK_VMV2RV 0xfe0ff07f |
#define MASK_VMV4RV 0xfe0ff07f |
#define MASK_VMV8RV 0xfe0ff07f |
#define MASK_VMVSX 0xfff0707f |
#define MASK_VMVVI 0xfff0707f |
#define MASK_VMVVV 0xfff0707f |
#define MASK_VMVVX 0xfff0707f |
#define MASK_VMVXS 0xfe0ff07f |
#define MASK_VMXNORMM 0xfe00707f |
#define MASK_VMXORMM 0xfe00707f |
#define MASK_VNCLIPUWI 0xfc00707f |
#define MASK_VNCLIPUWV 0xfc00707f |
#define MASK_VNCLIPUWX 0xfc00707f |
#define MASK_VNCLIPWI 0xfc00707f |
#define MASK_VNCLIPWV 0xfc00707f |
#define MASK_VNCLIPWX 0xfc00707f |
#define MASK_VNCVTXXW 0xfc0ff07f |
#define MASK_VNMSACVV 0xfc00707f |
#define MASK_VNMSACVX 0xfc00707f |
#define MASK_VNMSUBVV 0xfc00707f |
#define MASK_VNMSUBVX 0xfc00707f |
#define MASK_VNOTV 0xfc0ff07f |
#define MASK_VNSRAWI 0xfc00707f |
#define MASK_VNSRAWV 0xfc00707f |
#define MASK_VNSRAWX 0xfc00707f |
#define MASK_VNSRLWI 0xfc00707f |
#define MASK_VNSRLWV 0xfc00707f |
#define MASK_VNSRLWX 0xfc00707f |
#define MASK_VORVI 0xfc00707f |
#define MASK_VORVV 0xfc00707f |
#define MASK_VORVX 0xfc00707f |
#define MASK_VQMACCSUVV 0xfc00707f |
#define MASK_VQMACCSUVX 0xfc00707f |
#define MASK_VQMACCUSVX 0xfc00707f |
#define MASK_VQMACCUVV 0xfc00707f |
#define MASK_VQMACCUVX 0xfc00707f |
#define MASK_VQMACCVV 0xfc00707f |
#define MASK_VQMACCVX 0xfc00707f |
#define MASK_VREDANDVS 0xfc00707f |
#define MASK_VREDMAXUVS 0xfc00707f |
#define MASK_VREDMAXVS 0xfc00707f |
#define MASK_VREDMINUVS 0xfc00707f |
#define MASK_VREDMINVS 0xfc00707f |
#define MASK_VREDORVS 0xfc00707f |
#define MASK_VREDSUMVS 0xfc00707f |
#define MASK_VREDXORVS 0xfc00707f |
#define MASK_VREMUVV 0xfc00707f |
#define MASK_VREMUVX 0xfc00707f |
#define MASK_VREMVV 0xfc00707f |
#define MASK_VREMVX 0xfc00707f |
#define MASK_VREV8_V 0xfc0ff07f |
#define MASK_VRGATHEREI16VV 0xfc00707f |
#define MASK_VRGATHERVI 0xfc00707f |
#define MASK_VRGATHERVV 0xfc00707f |
#define MASK_VRGATHERVX 0xfc00707f |
#define MASK_VROL_VV 0xfc00707f |
#define MASK_VROL_VX 0xfc00707f |
#define MASK_VROR_VI 0xf800707f |
#define MASK_VROR_VV 0xfc00707f |
#define MASK_VROR_VX 0xfc00707f |
#define MASK_VRSUBVI 0xfc00707f |
#define MASK_VRSUBVX 0xfc00707f |
#define MASK_VS1RV 0xfff0707f |
#define MASK_VS2RV 0xfff0707f |
#define MASK_VS4RV 0xfff0707f |
#define MASK_VS8RV 0xfff0707f |
#define MASK_VSADDUVI 0xfc00707f |
#define MASK_VSADDUVV 0xfc00707f |
#define MASK_VSADDUVX 0xfc00707f |
#define MASK_VSADDVI 0xfc00707f |
#define MASK_VSADDVV 0xfc00707f |
#define MASK_VSADDVX 0xfc00707f |
#define MASK_VSBCVVM 0xfe00707f |
#define MASK_VSBCVXM 0xfe00707f |
#define MASK_VSE16V 0xfdf0707f |
#define MASK_VSE32V 0xfdf0707f |
#define MASK_VSE64V 0xfdf0707f |
#define MASK_VSE8V 0xfdf0707f |
#define MASK_VSETIVLI 0xc000707f |
#define MASK_VSETVL 0xfe00707f |
#define MASK_VSETVLI 0x8000707f |
#define MASK_VSEXT_VF2 0xfc0ff07f |
#define MASK_VSEXT_VF4 0xfc0ff07f |
#define MASK_VSEXT_VF8 0xfc0ff07f |
#define MASK_VSHA2CH_VV 0xfe00707f |
#define MASK_VSHA2CL_VV 0xfe00707f |
#define MASK_VSHA2MS_VV 0xfe00707f |
#define MASK_VSLIDE1DOWNVX 0xfc00707f |
#define MASK_VSLIDE1UPVX 0xfc00707f |
#define MASK_VSLIDEDOWNVI 0xfc00707f |
#define MASK_VSLIDEDOWNVX 0xfc00707f |
#define MASK_VSLIDEUPVI 0xfc00707f |
#define MASK_VSLIDEUPVX 0xfc00707f |
#define MASK_VSLLVI 0xfc00707f |
#define MASK_VSLLVV 0xfc00707f |
#define MASK_VSLLVX 0xfc00707f |
#define MASK_VSM3C_VI 0xfe00707f |
#define MASK_VSM3ME_VV 0xfe00707f |
#define MASK_VSM4K_VI 0xfe00707f |
#define MASK_VSM4R_VS 0xfe0ff07f |
#define MASK_VSM4R_VV 0xfe0ff07f |
#define MASK_VSMULVV 0xfc00707f |
#define MASK_VSMULVX 0xfc00707f |
#define MASK_VSMV 0xfff0707f |
#define MASK_VSOXEI16V 0xfc00707f |
#define MASK_VSOXEI32V 0xfc00707f |
#define MASK_VSOXEI64V 0xfc00707f |
#define MASK_VSOXEI8V 0xfc00707f |
#define MASK_VSOXSEG2EI16V 0xfc00707f |
#define MASK_VSOXSEG2EI32V 0xfc00707f |
#define MASK_VSOXSEG2EI64V 0xfc00707f |
#define MASK_VSOXSEG2EI8V 0xfc00707f |
#define MASK_VSOXSEG3EI16V 0xfc00707f |
#define MASK_VSOXSEG3EI32V 0xfc00707f |
#define MASK_VSOXSEG3EI64V 0xfc00707f |
#define MASK_VSOXSEG3EI8V 0xfc00707f |
#define MASK_VSOXSEG4EI16V 0xfc00707f |
#define MASK_VSOXSEG4EI32V 0xfc00707f |
#define MASK_VSOXSEG4EI64V 0xfc00707f |
#define MASK_VSOXSEG4EI8V 0xfc00707f |
#define MASK_VSOXSEG5EI16V 0xfc00707f |
#define MASK_VSOXSEG5EI32V 0xfc00707f |
#define MASK_VSOXSEG5EI64V 0xfc00707f |
#define MASK_VSOXSEG5EI8V 0xfc00707f |
#define MASK_VSOXSEG6EI16V 0xfc00707f |
#define MASK_VSOXSEG6EI32V 0xfc00707f |
#define MASK_VSOXSEG6EI64V 0xfc00707f |
#define MASK_VSOXSEG6EI8V 0xfc00707f |
#define MASK_VSOXSEG7EI16V 0xfc00707f |
#define MASK_VSOXSEG7EI32V 0xfc00707f |
#define MASK_VSOXSEG7EI64V 0xfc00707f |
#define MASK_VSOXSEG7EI8V 0xfc00707f |
#define MASK_VSOXSEG8EI16V 0xfc00707f |
#define MASK_VSOXSEG8EI32V 0xfc00707f |
#define MASK_VSOXSEG8EI64V 0xfc00707f |
#define MASK_VSOXSEG8EI8V 0xfc00707f |
#define MASK_VSRAVI 0xfc00707f |
#define MASK_VSRAVV 0xfc00707f |
#define MASK_VSRAVX 0xfc00707f |
#define MASK_VSRLVI 0xfc00707f |
#define MASK_VSRLVV 0xfc00707f |
#define MASK_VSRLVX 0xfc00707f |
#define MASK_VSSE16V 0xfc00707f |
#define MASK_VSSE32V 0xfc00707f |
#define MASK_VSSE64V 0xfc00707f |
#define MASK_VSSE8V 0xfc00707f |
#define MASK_VSSEG2E16V 0xfdf0707f |
#define MASK_VSSEG2E32V 0xfdf0707f |
#define MASK_VSSEG2E64V 0xfdf0707f |
#define MASK_VSSEG2E8V 0xfdf0707f |
#define MASK_VSSEG3E16V 0xfdf0707f |
#define MASK_VSSEG3E32V 0xfdf0707f |
#define MASK_VSSEG3E64V 0xfdf0707f |
#define MASK_VSSEG3E8V 0xfdf0707f |
#define MASK_VSSEG4E16V 0xfdf0707f |
#define MASK_VSSEG4E32V 0xfdf0707f |
#define MASK_VSSEG4E64V 0xfdf0707f |
#define MASK_VSSEG4E8V 0xfdf0707f |
#define MASK_VSSEG5E16V 0xfdf0707f |
#define MASK_VSSEG5E32V 0xfdf0707f |
#define MASK_VSSEG5E64V 0xfdf0707f |
#define MASK_VSSEG5E8V 0xfdf0707f |
#define MASK_VSSEG6E16V 0xfdf0707f |
#define MASK_VSSEG6E32V 0xfdf0707f |
#define MASK_VSSEG6E64V 0xfdf0707f |
#define MASK_VSSEG6E8V 0xfdf0707f |
#define MASK_VSSEG7E16V 0xfdf0707f |
#define MASK_VSSEG7E32V 0xfdf0707f |
#define MASK_VSSEG7E64V 0xfdf0707f |
#define MASK_VSSEG7E8V 0xfdf0707f |
#define MASK_VSSEG8E16V 0xfdf0707f |
#define MASK_VSSEG8E32V 0xfdf0707f |
#define MASK_VSSEG8E64V 0xfdf0707f |
#define MASK_VSSEG8E8V 0xfdf0707f |
#define MASK_VSSRAVI 0xfc00707f |
#define MASK_VSSRAVV 0xfc00707f |
#define MASK_VSSRAVX 0xfc00707f |
#define MASK_VSSRLVI 0xfc00707f |
#define MASK_VSSRLVV 0xfc00707f |
#define MASK_VSSRLVX 0xfc00707f |
#define MASK_VSSSEG2E16V 0xfc00707f |
#define MASK_VSSSEG2E32V 0xfc00707f |
#define MASK_VSSSEG2E64V 0xfc00707f |
#define MASK_VSSSEG2E8V 0xfc00707f |
#define MASK_VSSSEG3E16V 0xfc00707f |
#define MASK_VSSSEG3E32V 0xfc00707f |
#define MASK_VSSSEG3E64V 0xfc00707f |
#define MASK_VSSSEG3E8V 0xfc00707f |
#define MASK_VSSSEG4E16V 0xfc00707f |
#define MASK_VSSSEG4E32V 0xfc00707f |
#define MASK_VSSSEG4E64V 0xfc00707f |
#define MASK_VSSSEG4E8V 0xfc00707f |
#define MASK_VSSSEG5E16V 0xfc00707f |
#define MASK_VSSSEG5E32V 0xfc00707f |
#define MASK_VSSSEG5E64V 0xfc00707f |
#define MASK_VSSSEG5E8V 0xfc00707f |
#define MASK_VSSSEG6E16V 0xfc00707f |
#define MASK_VSSSEG6E32V 0xfc00707f |
#define MASK_VSSSEG6E64V 0xfc00707f |
#define MASK_VSSSEG6E8V 0xfc00707f |
#define MASK_VSSSEG7E16V 0xfc00707f |
#define MASK_VSSSEG7E32V 0xfc00707f |
#define MASK_VSSSEG7E64V 0xfc00707f |
#define MASK_VSSSEG7E8V 0xfc00707f |
#define MASK_VSSSEG8E16V 0xfc00707f |
#define MASK_VSSSEG8E32V 0xfc00707f |
#define MASK_VSSSEG8E64V 0xfc00707f |
#define MASK_VSSSEG8E8V 0xfc00707f |
#define MASK_VSSUBUVV 0xfc00707f |
#define MASK_VSSUBUVX 0xfc00707f |
#define MASK_VSSUBVV 0xfc00707f |
#define MASK_VSSUBVX 0xfc00707f |
#define MASK_VSUBVV 0xfc00707f |
#define MASK_VSUBVX 0xfc00707f |
#define MASK_VSUXEI16V 0xfc00707f |
#define MASK_VSUXEI32V 0xfc00707f |
#define MASK_VSUXEI64V 0xfc00707f |
#define MASK_VSUXEI8V 0xfc00707f |
#define MASK_VSUXSEG2EI16V 0xfc00707f |
#define MASK_VSUXSEG2EI32V 0xfc00707f |
#define MASK_VSUXSEG2EI64V 0xfc00707f |
#define MASK_VSUXSEG2EI8V 0xfc00707f |
#define MASK_VSUXSEG3EI16V 0xfc00707f |
#define MASK_VSUXSEG3EI32V 0xfc00707f |
#define MASK_VSUXSEG3EI64V 0xfc00707f |
#define MASK_VSUXSEG3EI8V 0xfc00707f |
#define MASK_VSUXSEG4EI16V 0xfc00707f |
#define MASK_VSUXSEG4EI32V 0xfc00707f |
#define MASK_VSUXSEG4EI64V 0xfc00707f |
#define MASK_VSUXSEG4EI8V 0xfc00707f |
#define MASK_VSUXSEG5EI16V 0xfc00707f |
#define MASK_VSUXSEG5EI32V 0xfc00707f |
#define MASK_VSUXSEG5EI64V 0xfc00707f |
#define MASK_VSUXSEG5EI8V 0xfc00707f |
#define MASK_VSUXSEG6EI16V 0xfc00707f |
#define MASK_VSUXSEG6EI32V 0xfc00707f |
#define MASK_VSUXSEG6EI64V 0xfc00707f |
#define MASK_VSUXSEG6EI8V 0xfc00707f |
#define MASK_VSUXSEG7EI16V 0xfc00707f |
#define MASK_VSUXSEG7EI32V 0xfc00707f |
#define MASK_VSUXSEG7EI64V 0xfc00707f |
#define MASK_VSUXSEG7EI8V 0xfc00707f |
#define MASK_VSUXSEG8EI16V 0xfc00707f |
#define MASK_VSUXSEG8EI32V 0xfc00707f |
#define MASK_VSUXSEG8EI64V 0xfc00707f |
#define MASK_VSUXSEG8EI8V 0xfc00707f |
#define MASK_VT_MASKC 0xfe00707f |
#define MASK_VT_MASKCN 0xfe00707f |
#define MASK_VWADDUVV 0xfc00707f |
#define MASK_VWADDUVX 0xfc00707f |
#define MASK_VWADDUWV 0xfc00707f |
#define MASK_VWADDUWX 0xfc00707f |
#define MASK_VWADDVV 0xfc00707f |
#define MASK_VWADDVX 0xfc00707f |
#define MASK_VWADDWV 0xfc00707f |
#define MASK_VWADDWX 0xfc00707f |
#define MASK_VWCVTUXXV 0xfc0ff07f |
#define MASK_VWCVTXXV 0xfc0ff07f |
#define MASK_VWMACCSUVV 0xfc00707f |
#define MASK_VWMACCSUVX 0xfc00707f |
#define MASK_VWMACCUSVX 0xfc00707f |
#define MASK_VWMACCUVV 0xfc00707f |
#define MASK_VWMACCUVX 0xfc00707f |
#define MASK_VWMACCVV 0xfc00707f |
#define MASK_VWMACCVX 0xfc00707f |
#define MASK_VWMULSUVV 0xfc00707f |
#define MASK_VWMULSUVX 0xfc00707f |
#define MASK_VWMULUVV 0xfc00707f |
#define MASK_VWMULUVX 0xfc00707f |
#define MASK_VWMULVV 0xfc00707f |
#define MASK_VWMULVX 0xfc00707f |
#define MASK_VWREDSUMUVS 0xfc00707f |
#define MASK_VWREDSUMVS 0xfc00707f |
#define MASK_VWSLL_VI 0xfc00707f |
#define MASK_VWSLL_VV 0xfc00707f |
#define MASK_VWSLL_VX 0xfc00707f |
#define MASK_VWSUBUVV 0xfc00707f |
#define MASK_VWSUBUVX 0xfc00707f |
#define MASK_VWSUBUWV 0xfc00707f |
#define MASK_VWSUBUWX 0xfc00707f |
#define MASK_VWSUBVV 0xfc00707f |
#define MASK_VWSUBVX 0xfc00707f |
#define MASK_VWSUBWV 0xfc00707f |
#define MASK_VWSUBWX 0xfc00707f |
#define MASK_VXORVI 0xfc00707f |
#define MASK_VXORVV 0xfc00707f |
#define MASK_VXORVX 0xfc00707f |
#define MASK_VZEXT_VF2 0xfc0ff07f |
#define MASK_VZEXT_VF4 0xfc0ff07f |
#define MASK_VZEXT_VF8 0xfc0ff07f |
#define MASK_WFI 0xffffffff |
#define MASK_WRS_NTO 0xffffffff |
#define MASK_WRS_STO 0xffffffff |
#define MASK_XNOR 0xfe00707f |
#define MASK_XOR 0xfe00707f |
#define MASK_XORI 0x707f |
#define MASK_XPERM4 0xfe00707f |
#define MASK_XPERM8 0xfe00707f |
#define MATCH_ADD 0x33 |
#define MATCH_ADD_UW 0x800003b |
#define MATCH_ADDI 0x13 |
#define MATCH_ADDIW 0x1b |
#define MATCH_ADDW 0x3b |
#define MATCH_AES32DSI 0x2a000033 |
#define MATCH_AES32DSMI 0x2e000033 |
#define MATCH_AES32ESI 0x22000033 |
#define MATCH_AES32ESMI 0x26000033 |
#define MATCH_AES64DS 0x3a000033 |
#define MATCH_AES64DSM 0x3e000033 |
#define MATCH_AES64ES 0x32000033 |
#define MATCH_AES64ESM 0x36000033 |
#define MATCH_AES64IM 0x30001013 |
#define MATCH_AES64KS1I 0x31001013 |
#define MATCH_AES64KS2 0x7e000033 |
#define MATCH_AMOADD_D 0x302f |
#define MATCH_AMOADD_W 0x202f |
#define MATCH_AMOAND_D 0x6000302f |
#define MATCH_AMOAND_W 0x6000202f |
#define MATCH_AMOMAX_D 0xa000302f |
#define MATCH_AMOMAX_W 0xa000202f |
#define MATCH_AMOMAXU_D 0xe000302f |
#define MATCH_AMOMAXU_W 0xe000202f |
#define MATCH_AMOMIN_D 0x8000302f |
#define MATCH_AMOMIN_W 0x8000202f |
#define MATCH_AMOMINU_D 0xc000302f |
#define MATCH_AMOMINU_W 0xc000202f |
#define MATCH_AMOOR_D 0x4000302f |
#define MATCH_AMOOR_W 0x4000202f |
#define MATCH_AMOSWAP_D 0x800302f |
#define MATCH_AMOSWAP_W 0x800202f |
#define MATCH_AMOXOR_D 0x2000302f |
#define MATCH_AMOXOR_W 0x2000202f |
#define MATCH_AND 0x7033 |
#define MATCH_ANDI 0x7013 |
#define MATCH_ANDN 0x40007033 |
#define MATCH_AUIPC 0x17 |
#define MATCH_BCLR 0x48001033 |
#define MATCH_BCLRI 0x48001013 |
#define MATCH_BEQ 0x63 |
#define MATCH_BEXT 0x48005033 |
#define MATCH_BEXTI 0x48005013 |
#define MATCH_BGE 0x5063 |
#define MATCH_BGEU 0x7063 |
#define MATCH_BINV 0x68001033 |
#define MATCH_BINVI 0x68001013 |
#define MATCH_BLT 0x4063 |
#define MATCH_BLTU 0x6063 |
#define MATCH_BNE 0x1063 |
#define MATCH_BSET 0x28001033 |
#define MATCH_BSETI 0x28001013 |
#define MATCH_C_ADD 0x9002 |
#define MATCH_C_ADDI 0x1 |
#define MATCH_C_ADDI16SP 0x6101 |
#define MATCH_C_ADDI4SPN 0x0 |
#define MATCH_C_ADDIW 0x2001 |
#define MATCH_C_ADDW 0x9c21 |
#define MATCH_C_AND 0x8c61 |
#define MATCH_C_ANDI 0x8801 |
#define MATCH_C_BEQZ 0xc001 |
#define MATCH_C_BNEZ 0xe001 |
#define MATCH_C_EBREAK 0x9002 |
#define MATCH_C_FLD 0x2000 |
#define MATCH_C_FLDSP 0x2002 |
#define MATCH_C_FLW 0x6000 |
#define MATCH_C_FLWSP 0x6002 |
#define MATCH_C_FSD 0xa000 |
#define MATCH_C_FSDSP 0xa002 |
#define MATCH_C_FSW 0xe000 |
#define MATCH_C_FSWSP 0xe002 |
#define MATCH_C_J 0xa001 |
#define MATCH_C_JAL 0x2001 |
#define MATCH_C_JALR 0x9002 |
#define MATCH_C_JR 0x8002 |
#define MATCH_C_LBU 0x8000 |
#define MATCH_C_LD 0x6000 |
#define MATCH_C_LDSP 0x6002 |
#define MATCH_C_LH 0x8440 |
#define MATCH_C_LHU 0x8400 |
#define MATCH_C_LI 0x4001 |
#define MATCH_C_LUI 0x6001 |
#define MATCH_C_LW 0x4000 |
#define MATCH_C_LWSP 0x4002 |
#define MATCH_C_MUL 0x9c41 |
#define MATCH_C_MV 0x8002 |
#define MATCH_C_NOP 0x1 |
#define MATCH_C_NOT 0x9c75 |
#define MATCH_C_NTL_ALL 0x9016 |
#define MATCH_C_NTL_P1 0x900a |
#define MATCH_C_NTL_PALL 0x900e |
#define MATCH_C_NTL_S1 0x9012 |
#define MATCH_C_OR 0x8c41 |
#define MATCH_C_SB 0x8800 |
#define MATCH_C_SD 0xe000 |
#define MATCH_C_SDSP 0xe002 |
#define MATCH_C_SEXT_B 0x9c65 |
#define MATCH_C_SEXT_H 0x9c6d |
#define MATCH_C_SH 0x8c00 |
#define MATCH_C_SLLI 0x2 |
#define MATCH_C_SLLI64 0x2 |
#define MATCH_C_SRAI 0x8401 |
#define MATCH_C_SRAI64 0x8401 |
#define MATCH_C_SRLI 0x8001 |
#define MATCH_C_SRLI64 0x8001 |
#define MATCH_C_SUB 0x8c01 |
#define MATCH_C_SUBW 0x9c01 |
#define MATCH_C_SW 0xc000 |
#define MATCH_C_SWSP 0xc002 |
#define MATCH_C_XOR 0x8c21 |
#define MATCH_C_ZEXT_B 0x9c61 |
#define MATCH_C_ZEXT_H 0x9c69 |
#define MATCH_C_ZEXT_W 0x9c71 |
#define MATCH_CBO_CLEAN 0x10200f |
#define MATCH_CBO_FLUSH 0x20200f |
#define MATCH_CBO_INVAL 0x200f |
#define MATCH_CBO_ZERO 0x40200f |
#define MATCH_CLMUL 0xa001033 |
#define MATCH_CLMULH 0xa003033 |
#define MATCH_CLMULR 0xa002033 |
#define MATCH_CLZ 0x60001013 |
#define MATCH_CLZW 0x6000101b |
#define MATCH_CPOP 0x60201013 |
#define MATCH_CPOPW 0x6020101b |
#define MATCH_CSRRC 0x3073 |
#define MATCH_CSRRCI 0x7073 |
#define MATCH_CSRRS 0x2073 |
#define MATCH_CSRRSI 0x6073 |
#define MATCH_CSRRW 0x1073 |
#define MATCH_CSRRWI 0x5073 |
#define MATCH_CTZ 0x60101013 |
#define MATCH_CTZW 0x6010101b |
#define MATCH_CZERO_EQZ 0xe005033 |
#define MATCH_CZERO_NEZ 0xe007033 |
#define MATCH_DIV 0x2004033 |
#define MATCH_DIVU 0x2005033 |
#define MATCH_DIVUW 0x200503b |
#define MATCH_DIVW 0x200403b |
#define MATCH_DRET 0x7b200073 |
#define MATCH_EBREAK 0x100073 |
#define MATCH_ECALL 0x73 |
#define MATCH_FADD_D 0x2000053 |
#define MATCH_FADD_H 0x4000053 |
#define MATCH_FADD_Q 0x6000053 |
#define MATCH_FADD_S 0x53 |
#define MATCH_FCLASS_D 0xe2001053 |
#define MATCH_FCLASS_H 0xe4001053 |
#define MATCH_FCLASS_Q 0xe6001053 |
#define MATCH_FCLASS_S 0xe0001053 |
#define MATCH_FCVT_D_H 0x42200053 |
#define MATCH_FCVT_D_L 0xd2200053 |
#define MATCH_FCVT_D_LU 0xd2300053 |
#define MATCH_FCVT_D_Q 0x42300053 |
#define MATCH_FCVT_D_S 0x42000053 |
#define MATCH_FCVT_D_W 0xd2000053 |
#define MATCH_FCVT_D_WU 0xd2100053 |
#define MATCH_FCVT_H_D 0x44100053 |
#define MATCH_FCVT_H_L 0xd4200053 |
#define MATCH_FCVT_H_LU 0xd4300053 |
#define MATCH_FCVT_H_Q 0x44300053 |
#define MATCH_FCVT_H_S 0x44000053 |
#define MATCH_FCVT_H_W 0xd4000053 |
#define MATCH_FCVT_H_WU 0xd4100053 |
#define MATCH_FCVT_L_D 0xc2200053 |
#define MATCH_FCVT_L_H 0xc4200053 |
#define MATCH_FCVT_L_Q 0xc6200053 |
#define MATCH_FCVT_L_S 0xc0200053 |
#define MATCH_FCVT_LU_D 0xc2300053 |
#define MATCH_FCVT_LU_H 0xc4300053 |
#define MATCH_FCVT_LU_Q 0xc6300053 |
#define MATCH_FCVT_LU_S 0xc0300053 |
#define MATCH_FCVT_Q_D 0x46100053 |
#define MATCH_FCVT_Q_H 0x46200053 |
#define MATCH_FCVT_Q_L 0xd6200053 |
#define MATCH_FCVT_Q_LU 0xd6300053 |
#define MATCH_FCVT_Q_S 0x46000053 |
#define MATCH_FCVT_Q_W 0xd6000053 |
#define MATCH_FCVT_Q_WU 0xd6100053 |
#define MATCH_FCVT_S_D 0x40100053 |
#define MATCH_FCVT_S_H 0x40200053 |
#define MATCH_FCVT_S_L 0xd0200053 |
#define MATCH_FCVT_S_LU 0xd0300053 |
#define MATCH_FCVT_S_Q 0x40300053 |
#define MATCH_FCVT_S_W 0xd0000053 |
#define MATCH_FCVT_S_WU 0xd0100053 |
#define MATCH_FCVT_W_D 0xc2000053 |
#define MATCH_FCVT_W_H 0xc4000053 |
#define MATCH_FCVT_W_Q 0xc6000053 |
#define MATCH_FCVT_W_S 0xc0000053 |
#define MATCH_FCVT_WU_D 0xc2100053 |
#define MATCH_FCVT_WU_H 0xc4100053 |
#define MATCH_FCVT_WU_Q 0xc6100053 |
#define MATCH_FCVT_WU_S 0xc0100053 |
#define MATCH_FCVTMOD_W_D 0xc2801053 |
#define MATCH_FDIV_D 0x1a000053 |
#define MATCH_FDIV_H 0x1c000053 |
#define MATCH_FDIV_Q 0x1e000053 |
#define MATCH_FDIV_S 0x18000053 |
#define MATCH_FENCE 0xf |
#define MATCH_FENCE_I 0x100f |
#define MATCH_FENCE_TSO 0x8330000f |
#define MATCH_FEQ_D 0xa2002053 |
#define MATCH_FEQ_H 0xa4002053 |
#define MATCH_FEQ_Q 0xa6002053 |
#define MATCH_FEQ_S 0xa0002053 |
#define MATCH_FLD 0x3007 |
#define MATCH_FLE_D 0xa2000053 |
#define MATCH_FLE_H 0xa4000053 |
#define MATCH_FLE_Q 0xa6000053 |
#define MATCH_FLE_S 0xa0000053 |
#define MATCH_FLEQ_D 0xa2004053 |
#define MATCH_FLEQ_H 0xa4004053 |
#define MATCH_FLEQ_Q 0xa6004053 |
#define MATCH_FLEQ_S 0xa0004053 |
#define MATCH_FLH 0x1007 |
#define MATCH_FLI_D 0xf2100053 |
#define MATCH_FLI_H 0xf4100053 |
#define MATCH_FLI_Q 0xf6100053 |
#define MATCH_FLI_S 0xf0100053 |
#define MATCH_FLQ 0x4007 |
#define MATCH_FLT_D 0xa2001053 |
#define MATCH_FLT_H 0xa4001053 |
#define MATCH_FLT_Q 0xa6001053 |
#define MATCH_FLT_S 0xa0001053 |
#define MATCH_FLTQ_D 0xa2005053 |
#define MATCH_FLTQ_H 0xa4005053 |
#define MATCH_FLTQ_Q 0xa6005053 |
#define MATCH_FLTQ_S 0xa0005053 |
#define MATCH_FLW 0x2007 |
#define MATCH_FMADD_D 0x2000043 |
#define MATCH_FMADD_H 0x4000043 |
#define MATCH_FMADD_Q 0x6000043 |
#define MATCH_FMADD_S 0x43 |
#define MATCH_FMAX_D 0x2a001053 |
#define MATCH_FMAX_H 0x2c001053 |
#define MATCH_FMAX_Q 0x2e001053 |
#define MATCH_FMAX_S 0x28001053 |
#define MATCH_FMAXM_D 0x2a003053 |
#define MATCH_FMAXM_H 0x2c003053 |
#define MATCH_FMAXM_Q 0x2e003053 |
#define MATCH_FMAXM_S 0x28003053 |
#define MATCH_FMIN_D 0x2a000053 |
#define MATCH_FMIN_H 0x2c000053 |
#define MATCH_FMIN_Q 0x2e000053 |
#define MATCH_FMIN_S 0x28000053 |
#define MATCH_FMINM_D 0x2a002053 |
#define MATCH_FMINM_H 0x2c002053 |
#define MATCH_FMINM_Q 0x2e002053 |
#define MATCH_FMINM_S 0x28002053 |
#define MATCH_FMSUB_D 0x2000047 |
#define MATCH_FMSUB_H 0x4000047 |
#define MATCH_FMSUB_Q 0x6000047 |
#define MATCH_FMSUB_S 0x47 |
#define MATCH_FMUL_D 0x12000053 |
#define MATCH_FMUL_H 0x14000053 |
#define MATCH_FMUL_Q 0x16000053 |
#define MATCH_FMUL_S 0x10000053 |
#define MATCH_FMV_D_X 0xf2000053 |
#define MATCH_FMV_H_X 0xf4000053 |
#define MATCH_FMV_S_X 0xf0000053 |
#define MATCH_FMV_X_D 0xe2000053 |
#define MATCH_FMV_X_H 0xe4000053 |
#define MATCH_FMV_X_S 0xe0000053 |
#define MATCH_FMVH_X_D 0xe2100053 |
#define MATCH_FMVH_X_Q 0xe6100053 |
#define MATCH_FMVP_D_X 0xb2000053 |
#define MATCH_FMVP_Q_X 0xb6000053 |
#define MATCH_FNMADD_D 0x200004f |
#define MATCH_FNMADD_H 0x400004f |
#define MATCH_FNMADD_Q 0x600004f |
#define MATCH_FNMADD_S 0x4f |
#define MATCH_FNMSUB_D 0x200004b |
#define MATCH_FNMSUB_H 0x400004b |
#define MATCH_FNMSUB_Q 0x600004b |
#define MATCH_FNMSUB_S 0x4b |
#define MATCH_FRCSR 0x302073 |
#define MATCH_FRFLAGS 0x102073 |
#define MATCH_FROUND_D 0x42400053 |
#define MATCH_FROUND_H 0x44400053 |
#define MATCH_FROUND_Q 0x46400053 |
#define MATCH_FROUND_S 0x40400053 |
#define MATCH_FROUNDNX_D 0x42500053 |
#define MATCH_FROUNDNX_H 0x44500053 |
#define MATCH_FROUNDNX_Q 0x46500053 |
#define MATCH_FROUNDNX_S 0x40500053 |
#define MATCH_FRRM 0x202073 |
#define MATCH_FSCSR 0x301073 |
#define MATCH_FSD 0x3027 |
#define MATCH_FSFLAGS 0x101073 |
#define MATCH_FSFLAGSI 0x105073 |
#define MATCH_FSGNJ_D 0x22000053 |
#define MATCH_FSGNJ_H 0x24000053 |
#define MATCH_FSGNJ_Q 0x26000053 |
#define MATCH_FSGNJ_S 0x20000053 |
#define MATCH_FSGNJN_D 0x22001053 |
#define MATCH_FSGNJN_H 0x24001053 |
#define MATCH_FSGNJN_Q 0x26001053 |
#define MATCH_FSGNJN_S 0x20001053 |
#define MATCH_FSGNJX_D 0x22002053 |
#define MATCH_FSGNJX_H 0x24002053 |
#define MATCH_FSGNJX_Q 0x26002053 |
#define MATCH_FSGNJX_S 0x20002053 |
#define MATCH_FSH 0x1027 |
#define MATCH_FSQ 0x4027 |
#define MATCH_FSQRT_D 0x5a000053 |
#define MATCH_FSQRT_H 0x5c000053 |
#define MATCH_FSQRT_Q 0x5e000053 |
#define MATCH_FSQRT_S 0x58000053 |
#define MATCH_FSRM 0x201073 |
#define MATCH_FSRMI 0x205073 |
#define MATCH_FSUB_D 0xa000053 |
#define MATCH_FSUB_H 0xc000053 |
#define MATCH_FSUB_Q 0xe000053 |
#define MATCH_FSUB_S 0x8000053 |
#define MATCH_FSW 0x2027 |
#define MATCH_GORCI 0x28005013 |
#define MATCH_GREVI 0x68005013 |
#define MATCH_HFENCE_GVMA 0x62000073 |
#define MATCH_HFENCE_VVMA 0x22000073 |
#define MATCH_HINVAL_GVMA 0x66000073 |
#define MATCH_HINVAL_VVMA 0x26000073 |
#define MATCH_HLV_B 0x60004073 |
#define MATCH_HLV_BU 0x60104073 |
#define MATCH_HLV_D 0x6c004073 |
#define MATCH_HLV_H 0x64004073 |
#define MATCH_HLV_HU 0x64104073 |
#define MATCH_HLV_W 0x68004073 |
#define MATCH_HLV_WU 0x68104073 |
#define MATCH_HLVX_HU 0x64304073 |
#define MATCH_HLVX_WU 0x68304073 |
#define MATCH_HRET 0x20200073 |
#define MATCH_HSV_B 0x62004073 |
#define MATCH_HSV_D 0x6e004073 |
#define MATCH_HSV_H 0x66004073 |
#define MATCH_HSV_W 0x6a004073 |
#define MATCH_JAL 0x6f |
#define MATCH_JALR 0x67 |
#define MATCH_LB 0x3 |
#define MATCH_LBU 0x4003 |
#define MATCH_LD 0x3003 |
#define MATCH_LH 0x1003 |
#define MATCH_LHU 0x5003 |
#define MATCH_LR_D 0x1000302f |
#define MATCH_LR_W 0x1000202f |
#define MATCH_LUI 0x37 |
#define MATCH_LW 0x2003 |
#define MATCH_LWU 0x6003 |
#define MATCH_MAX 0xa006033 |
#define MATCH_MAXU 0xa007033 |
#define MATCH_MIN 0xa004033 |
#define MATCH_MINU 0xa005033 |
#define MATCH_MRET 0x30200073 |
#define MATCH_MUL 0x2000033 |
#define MATCH_MULH 0x2001033 |
#define MATCH_MULHSU 0x2002033 |
#define MATCH_MULHU 0x2003033 |
#define MATCH_MULW 0x200003b |
#define MATCH_NTL_ALL 0x500033 |
#define MATCH_NTL_P1 0x200033 |
#define MATCH_NTL_PALL 0x300033 |
#define MATCH_NTL_S1 0x400033 |
#define MATCH_OR 0x6033 |
#define MATCH_ORI 0x6013 |
#define MATCH_ORN 0x40006033 |
#define MATCH_PACK 0x8004033 |
#define MATCH_PACKH 0x8007033 |
#define MATCH_PACKW 0x800403b |
#define MATCH_PAUSE 0x0100000f |
#define MATCH_PREFETCH_I 0x6013 |
#define MATCH_PREFETCH_R 0x106013 |
#define MATCH_PREFETCH_W 0x306013 |
#define MATCH_RDCYCLE 0xc0002073 |
#define MATCH_RDCYCLEH 0xc8002073 |
#define MATCH_RDINSTRET 0xc0202073 |
#define MATCH_RDINSTRETH 0xc8202073 |
#define MATCH_RDTIME 0xc0102073 |
#define MATCH_RDTIMEH 0xc8102073 |
#define MATCH_REM 0x2006033 |
#define MATCH_REMU 0x2007033 |
#define MATCH_REMUW 0x200703b |
#define MATCH_REMW 0x200603b |
#define MATCH_ROL 0x60001033 |
#define MATCH_ROLW 0x6000103b |
#define MATCH_ROR 0x60005033 |
#define MATCH_RORI 0x60005013 |
#define MATCH_RORIW 0x6000501b |
#define MATCH_RORW 0x6000503b |
#define MATCH_SB 0x23 |
#define MATCH_SBREAK 0x100073 |
#define MATCH_SC_D 0x1800302f |
#define MATCH_SC_W 0x1800202f |
#define MATCH_SCALL 0x73 |
#define MATCH_SD 0x3023 |
#define MATCH_SEXT_B 0x60401013 |
#define MATCH_SEXT_H 0x60501013 |
#define MATCH_SFENCE_INVAL_IR 0x18100073 |
#define MATCH_SFENCE_VM 0x10400073 |
#define MATCH_SFENCE_VMA 0x12000073 |
#define MATCH_SFENCE_W_INVAL 0x18000073 |
#define MATCH_SH 0x1023 |
#define MATCH_SH1ADD 0x20002033 |
#define MATCH_SH1ADD_UW 0x2000203b |
#define MATCH_SH2ADD 0x20004033 |
#define MATCH_SH2ADD_UW 0x2000403b |
#define MATCH_SH3ADD 0x20006033 |
#define MATCH_SH3ADD_UW 0x2000603b |
#define MATCH_SHA256SIG0 0x10201013 |
#define MATCH_SHA256SIG1 0x10301013 |
#define MATCH_SHA256SUM0 0x10001013 |
#define MATCH_SHA256SUM1 0x10101013 |
#define MATCH_SHA512SIG0 0x10601013 |
#define MATCH_SHA512SIG0H 0x5c000033 |
#define MATCH_SHA512SIG0L 0x54000033 |
#define MATCH_SHA512SIG1 0x10701013 |
#define MATCH_SHA512SIG1H 0x5e000033 |
#define MATCH_SHA512SIG1L 0x56000033 |
#define MATCH_SHA512SUM0 0x10401013 |
#define MATCH_SHA512SUM0R 0x50000033 |
#define MATCH_SHA512SUM1 0x10501013 |
#define MATCH_SHA512SUM1R 0x52000033 |
#define MATCH_SHFLI 0x8001013 |
#define MATCH_SINVAL_VMA 0x16000073 |
#define MATCH_SLL 0x1033 |
#define MATCH_SLLI 0x1013 |
#define MATCH_SLLI_RV32 0x1013 |
#define MATCH_SLLI_UW 0x800101b |
#define MATCH_SLLIW 0x101b |
#define MATCH_SLLW 0x103b |
#define MATCH_SLT 0x2033 |
#define MATCH_SLTI 0x2013 |
#define MATCH_SLTIU 0x3013 |
#define MATCH_SLTU 0x3033 |
#define MATCH_SM3P0 0x10801013 |
#define MATCH_SM3P1 0x10901013 |
#define MATCH_SM4ED 0x30000033 |
#define MATCH_SM4KS 0x34000033 |
#define MATCH_SRA 0x40005033 |
#define MATCH_SRAI 0x40005013 |
#define MATCH_SRAI_RV32 0x40005013 |
#define MATCH_SRAIW 0x4000501b |
#define MATCH_SRAW 0x4000503b |
#define MATCH_SRET 0x10200073 |
#define MATCH_SRL 0x5033 |
#define MATCH_SRLI 0x5013 |
#define MATCH_SRLI_RV32 0x5013 |
#define MATCH_SRLIW 0x501b |
#define MATCH_SRLW 0x503b |
#define MATCH_SUB 0x40000033 |
#define MATCH_SUBW 0x4000003b |
#define MATCH_SW 0x2023 |
#define MATCH_TH_ADDSL 0x0000100b |
#define MATCH_TH_DCACHE_CALL 0x0010000b |
#define MATCH_TH_DCACHE_CIALL 0x0030000b |
#define MATCH_TH_DCACHE_CIPA 0x02b0000b |
#define MATCH_TH_DCACHE_CISW 0x0230000b |
#define MATCH_TH_DCACHE_CIVA 0x0270000b |
#define MATCH_TH_DCACHE_CPA 0x0290000b |
#define MATCH_TH_DCACHE_CPAL1 0x0280000b |
#define MATCH_TH_DCACHE_CSW 0x0210000b |
#define MATCH_TH_DCACHE_CVA 0x0250000b |
#define MATCH_TH_DCACHE_CVAL1 0x0240000b |
#define MATCH_TH_DCACHE_IALL 0x0020000b |
#define MATCH_TH_DCACHE_IPA 0x02a0000b |
#define MATCH_TH_DCACHE_ISW 0x0220000b |
#define MATCH_TH_DCACHE_IVA 0x0260000b |
#define MATCH_TH_EXT 0x0000200b |
#define MATCH_TH_EXTU 0x0000300b |
#define MATCH_TH_FF0 0x8400100b |
#define MATCH_TH_FF1 0x8600100b |
#define MATCH_TH_FLRD 0x6000600b |
#define MATCH_TH_FLRW 0x4000600b |
#define MATCH_TH_FLURD 0x7000600b |
#define MATCH_TH_FLURW 0x5000600b |
#define MATCH_TH_FMV_HW_X 0x5000100b |
#define MATCH_TH_FMV_X_HW 0x6000100b |
#define MATCH_TH_FSRD 0x6000700b |
#define MATCH_TH_FSRW 0x4000700b |
#define MATCH_TH_FSURD 0x7000700b |
#define MATCH_TH_FSURW 0x5000700b |
#define MATCH_TH_ICACHE_IALL 0x0100000b |
#define MATCH_TH_ICACHE_IALLS 0x0110000b |
#define MATCH_TH_ICACHE_IPA 0x0380000b |
#define MATCH_TH_ICACHE_IVA 0x0300000b |
#define MATCH_TH_IPOP 0x0050000b |
#define MATCH_TH_IPUSH 0x0040000b |
#define MATCH_TH_L2CACHE_CALL 0x0150000b |
#define MATCH_TH_L2CACHE_CIALL 0x0170000b |
#define MATCH_TH_L2CACHE_IALL 0x0160000b |
#define MATCH_TH_LBIA 0x1800400b |
#define MATCH_TH_LBIB 0x0800400b |
#define MATCH_TH_LBUIA 0x9800400b |
#define MATCH_TH_LBUIB 0x8800400b |
#define MATCH_TH_LDD 0xf800400b |
#define MATCH_TH_LDIA 0x7800400b |
#define MATCH_TH_LDIB 0x6800400b |
#define MATCH_TH_LHIA 0x3800400b |
#define MATCH_TH_LHIB 0x2800400b |
#define MATCH_TH_LHUIA 0xb800400b |
#define MATCH_TH_LHUIB 0xa800400b |
#define MATCH_TH_LRB 0x0000400b |
#define MATCH_TH_LRBU 0x8000400b |
#define MATCH_TH_LRD 0x6000400b |
#define MATCH_TH_LRH 0x2000400b |
#define MATCH_TH_LRHU 0xa000400b |
#define MATCH_TH_LRW 0x4000400b |
#define MATCH_TH_LRWU 0xc000400b |
#define MATCH_TH_LURB 0x1000400b |
#define MATCH_TH_LURBU 0x9000400b |
#define MATCH_TH_LURD 0x7000400b |
#define MATCH_TH_LURH 0x3000400b |
#define MATCH_TH_LURHU 0xb000400b |
#define MATCH_TH_LURW 0x5000400b |
#define MATCH_TH_LURWU 0xd000400b |
#define MATCH_TH_LWD 0xe000400b |
#define MATCH_TH_LWIA 0x5800400b |
#define MATCH_TH_LWIB 0x4800400b |
#define MATCH_TH_LWUD 0xf000400b |
#define MATCH_TH_LWUIA 0xd800400b |
#define MATCH_TH_LWUIB 0xc800400b |
#define MATCH_TH_MULA 0x2000100b |
#define MATCH_TH_MULAH 0x2800100b |
#define MATCH_TH_MULAW 0x2400100b |
#define MATCH_TH_MULS 0x2200100b |
#define MATCH_TH_MULSH 0x2a00100b |
#define MATCH_TH_MULSW 0x2600100b |
#define MATCH_TH_MVEQZ 0x4000100b |
#define MATCH_TH_MVNEZ 0x4200100b |
#define MATCH_TH_REV 0x8200100b |
#define MATCH_TH_REVW 0x9000100b |
#define MATCH_TH_SBIA 0x1800500b |
#define MATCH_TH_SBIB 0x0800500b |
#define MATCH_TH_SDD 0xf800500b |
#define MATCH_TH_SDIA 0x7800500b |
#define MATCH_TH_SDIB 0x6800500b |
#define MATCH_TH_SFENCE_VMAS 0x0400000b |
#define MATCH_TH_SHIA 0x3800500b |
#define MATCH_TH_SHIB 0x2800500b |
#define MATCH_TH_SRB 0x0000500b |
#define MATCH_TH_SRD 0x6000500b |
#define MATCH_TH_SRH 0x2000500b |
#define MATCH_TH_SRRI 0x1000100b |
#define MATCH_TH_SRRIW 0x1400100b |
#define MATCH_TH_SRW 0x4000500b |
#define MATCH_TH_SURB 0x1000500b |
#define MATCH_TH_SURD 0x7000500b |
#define MATCH_TH_SURH 0x3000500b |
#define MATCH_TH_SURW 0x5000500b |
#define MATCH_TH_SWD 0xe000500b |
#define MATCH_TH_SWIA 0x5800500b |
#define MATCH_TH_SWIB 0x4800500b |
#define MATCH_TH_SYNC 0x0180000b |
#define MATCH_TH_SYNC_I 0x01a0000b |
#define MATCH_TH_SYNC_IS 0x01b0000b |
#define MATCH_TH_SYNC_S 0x0190000b |
#define MATCH_TH_TST 0x8800100b |
#define MATCH_TH_TSTNBZ 0x8000100b |
#define MATCH_UNSHFLI 0x8005013 |
#define MATCH_URET 0x200073 |
#define MATCH_VAADDUVV 0x20002057 |
#define MATCH_VAADDUVX 0x20006057 |
#define MATCH_VAADDVV 0x24002057 |
#define MATCH_VAADDVX 0x24006057 |
#define MATCH_VADCVIM 0x40003057 |
#define MATCH_VADCVVM 0x40000057 |
#define MATCH_VADCVXM 0x40004057 |
#define MATCH_VADDVI 0x00003057 |
#define MATCH_VADDVV 0x00000057 |
#define MATCH_VADDVX 0x00004057 |
#define MATCH_VAESDF_VS 0xa600a077 |
#define MATCH_VAESDF_VV 0xa200a077 |
#define MATCH_VAESDM_VS 0xa6002077 |
#define MATCH_VAESDM_VV 0xa2002077 |
#define MATCH_VAESEF_VS 0xa601a077 |
#define MATCH_VAESEF_VV 0xa201a077 |
#define MATCH_VAESEM_VS 0xa6012077 |
#define MATCH_VAESEM_VV 0xa2012077 |
#define MATCH_VAESKF1_VI 0x8a002077 |
#define MATCH_VAESKF2_VI 0xaa002077 |
#define MATCH_VAESZ_VS 0xa603a077 |
#define MATCH_VANDN_VV 0x4000057 |
#define MATCH_VANDN_VX 0x4004057 |
#define MATCH_VANDVI 0x24003057 |
#define MATCH_VANDVV 0x24000057 |
#define MATCH_VANDVX 0x24004057 |
#define MATCH_VASUBUVV 0x28002057 |
#define MATCH_VASUBUVX 0x28006057 |
#define MATCH_VASUBVV 0x2c002057 |
#define MATCH_VASUBVX 0x2c006057 |
#define MATCH_VBREV8_V 0x48042057 |
#define MATCH_VBREV_V 0x48052057 |
#define MATCH_VCLMUL_VV 0x30002057 |
#define MATCH_VCLMUL_VX 0x30006057 |
#define MATCH_VCLMULH_VV 0x34002057 |
#define MATCH_VCLMULH_VX 0x34006057 |
#define MATCH_VCLZ_V 0x48062057 |
#define MATCH_VCOMPRESSVM 0x5e002057 |
#define MATCH_VCPOP_V 0x48072057 |
#define MATCH_VCPOPM 0x40082057 |
#define MATCH_VCTZ_V 0x4806a057 |
#define MATCH_VDIVUVV 0x80002057 |
#define MATCH_VDIVUVX 0x80006057 |
#define MATCH_VDIVVV 0x84002057 |
#define MATCH_VDIVVX 0x84006057 |
#define MATCH_VDOTUVV 0xe0000057 |
#define MATCH_VDOTVV 0xe4000057 |
#define MATCH_VFADDVF 0x00005057 |
#define MATCH_VFADDVV 0x00001057 |
#define MATCH_VFCLASSV 0x4c081057 |
#define MATCH_VFCVTFXUV 0x48011057 |
#define MATCH_VFCVTFXV 0x48019057 |
#define MATCH_VFCVTRTZXFV 0x48039057 |
#define MATCH_VFCVTRTZXUFV 0x48031057 |
#define MATCH_VFCVTXFV 0x48009057 |
#define MATCH_VFCVTXUFV 0x48001057 |
#define MATCH_VFDIVVF 0x80005057 |
#define MATCH_VFDIVVV 0x80001057 |
#define MATCH_VFDOTVV 0xe4001057 |
#define MATCH_VFIRSTM 0x4008a057 |
#define MATCH_VFMACCVF 0xb0005057 |
#define MATCH_VFMACCVV 0xb0001057 |
#define MATCH_VFMADDVF 0xa0005057 |
#define MATCH_VFMADDVV 0xa0001057 |
#define MATCH_VFMAXVF 0x18005057 |
#define MATCH_VFMAXVV 0x18001057 |
#define MATCH_VFMERGEVFM 0x5c005057 |
#define MATCH_VFMINVF 0x10005057 |
#define MATCH_VFMINVV 0x10001057 |
#define MATCH_VFMSACVF 0xb8005057 |
#define MATCH_VFMSACVV 0xb8001057 |
#define MATCH_VFMSUBVF 0xa8005057 |
#define MATCH_VFMSUBVV 0xa8001057 |
#define MATCH_VFMULVF 0x90005057 |
#define MATCH_VFMULVV 0x90001057 |
#define MATCH_VFMVFS 0x42001057 |
#define MATCH_VFMVSF 0x42005057 |
#define MATCH_VFMVVF 0x5e005057 |
#define MATCH_VFNCVTFFW 0x480a1057 |
#define MATCH_VFNCVTFXUW 0x48091057 |
#define MATCH_VFNCVTFXW 0x48099057 |
#define MATCH_VFNCVTRODFFW 0x480a9057 |
#define MATCH_VFNCVTRTZXFW 0x480b9057 |
#define MATCH_VFNCVTRTZXUFW 0x480b1057 |
#define MATCH_VFNCVTXFW 0x48089057 |
#define MATCH_VFNCVTXUFW 0x48081057 |
#define MATCH_VFNMACCVF 0xb4005057 |
#define MATCH_VFNMACCVV 0xb4001057 |
#define MATCH_VFNMADDVF 0xa4005057 |
#define MATCH_VFNMADDVV 0xa4001057 |
#define MATCH_VFNMSACVF 0xbc005057 |
#define MATCH_VFNMSACVV 0xbc001057 |
#define MATCH_VFNMSUBVF 0xac005057 |
#define MATCH_VFNMSUBVV 0xac001057 |
#define MATCH_VFRDIVVF 0x84005057 |
#define MATCH_VFREC7V 0x4c029057 |
#define MATCH_VFREDMAXVS 0x1c001057 |
#define MATCH_VFREDMINVS 0x14001057 |
#define MATCH_VFREDOSUMVS 0x0c001057 |
#define MATCH_VFREDUSUMVS 0x04001057 |
#define MATCH_VFRSQRT7V 0x4c021057 |
#define MATCH_VFRSUBVF 0x9c005057 |
#define MATCH_VFSGNJNVF 0x24005057 |
#define MATCH_VFSGNJNVV 0x24001057 |
#define MATCH_VFSGNJVF 0x20005057 |
#define MATCH_VFSGNJVV 0x20001057 |
#define MATCH_VFSGNJXVF 0x28005057 |
#define MATCH_VFSGNJXVV 0x28001057 |
#define MATCH_VFSLIDE1DOWNVF 0x3c005057 |
#define MATCH_VFSLIDE1UPVF 0x38005057 |
#define MATCH_VFSQRTV 0x4c001057 |
#define MATCH_VFSUBVF 0x08005057 |
#define MATCH_VFSUBVV 0x08001057 |
#define MATCH_VFWADDVF 0xc0005057 |
#define MATCH_VFWADDVV 0xc0001057 |
#define MATCH_VFWADDWF 0xd0005057 |
#define MATCH_VFWADDWV 0xd0001057 |
#define MATCH_VFWCVTFFV 0x48061057 |
#define MATCH_VFWCVTFXUV 0x48051057 |
#define MATCH_VFWCVTFXV 0x48059057 |
#define MATCH_VFWCVTRTZXFV 0x48079057 |
#define MATCH_VFWCVTRTZXUFV 0x48071057 |
#define MATCH_VFWCVTXFV 0x48049057 |
#define MATCH_VFWCVTXUFV 0x48041057 |
#define MATCH_VFWMACCVF 0xf0005057 |
#define MATCH_VFWMACCVV 0xf0001057 |
#define MATCH_VFWMSACVF 0xf8005057 |
#define MATCH_VFWMSACVV 0xf8001057 |
#define MATCH_VFWMULVF 0xe0005057 |
#define MATCH_VFWMULVV 0xe0001057 |
#define MATCH_VFWNMACCVF 0xf4005057 |
#define MATCH_VFWNMACCVV 0xf4001057 |
#define MATCH_VFWNMSACVF 0xfc005057 |
#define MATCH_VFWNMSACVV 0xfc001057 |
#define MATCH_VFWREDOSUMVS 0xcc001057 |
#define MATCH_VFWREDUSUMVS 0xc4001057 |
#define MATCH_VFWSUBVF 0xc8005057 |
#define MATCH_VFWSUBVV 0xc8001057 |
#define MATCH_VFWSUBWF 0xd8005057 |
#define MATCH_VFWSUBWV 0xd8001057 |
#define MATCH_VGHSH_VV 0xb2002077 |
#define MATCH_VGMUL_VV 0xa208a077 |
#define MATCH_VIDV 0x5008a057 |
#define MATCH_VIOTAM 0x50082057 |
#define MATCH_VL1RE16V 0x02805007 |
#define MATCH_VL1RE32V 0x02806007 |
#define MATCH_VL1RE64V 0x02807007 |
#define MATCH_VL1RE8V 0x02800007 |
#define MATCH_VL2RE16V 0x22805007 |
#define MATCH_VL2RE32V 0x22806007 |
#define MATCH_VL2RE64V 0x22807007 |
#define MATCH_VL2RE8V 0x22800007 |
#define MATCH_VL4RE16V 0x62805007 |
#define MATCH_VL4RE32V 0x62806007 |
#define MATCH_VL4RE64V 0x62807007 |
#define MATCH_VL4RE8V 0x62800007 |
#define MATCH_VL8RE16V 0xe2805007 |
#define MATCH_VL8RE32V 0xe2806007 |
#define MATCH_VL8RE64V 0xe2807007 |
#define MATCH_VL8RE8V 0xe2800007 |
#define MATCH_VLE16FFV 0x01005007 |
#define MATCH_VLE16V 0x00005007 |
#define MATCH_VLE32FFV 0x01006007 |
#define MATCH_VLE32V 0x00006007 |
#define MATCH_VLE64FFV 0x01007007 |
#define MATCH_VLE64V 0x00007007 |
#define MATCH_VLE8FFV 0x01000007 |
#define MATCH_VLE8V 0x00000007 |
#define MATCH_VLMV 0x02b00007 |
#define MATCH_VLOXEI16V 0x0c005007 |
#define MATCH_VLOXEI32V 0x0c006007 |
#define MATCH_VLOXEI64V 0x0c007007 |
#define MATCH_VLOXEI8V 0x0c000007 |
#define MATCH_VLOXSEG2EI16V 0x2c005007 |
#define MATCH_VLOXSEG2EI32V 0x2c006007 |
#define MATCH_VLOXSEG2EI64V 0x2c007007 |
#define MATCH_VLOXSEG2EI8V 0x2c000007 |
#define MATCH_VLOXSEG3EI16V 0x4c005007 |
#define MATCH_VLOXSEG3EI32V 0x4c006007 |
#define MATCH_VLOXSEG3EI64V 0x4c007007 |
#define MATCH_VLOXSEG3EI8V 0x4c000007 |
#define MATCH_VLOXSEG4EI16V 0x6c005007 |
#define MATCH_VLOXSEG4EI32V 0x6c006007 |
#define MATCH_VLOXSEG4EI64V 0x6c007007 |
#define MATCH_VLOXSEG4EI8V 0x6c000007 |
#define MATCH_VLOXSEG5EI16V 0x8c005007 |
#define MATCH_VLOXSEG5EI32V 0x8c006007 |
#define MATCH_VLOXSEG5EI64V 0x8c007007 |
#define MATCH_VLOXSEG5EI8V 0x8c000007 |
#define MATCH_VLOXSEG6EI16V 0xac005007 |
#define MATCH_VLOXSEG6EI32V 0xac006007 |
#define MATCH_VLOXSEG6EI64V 0xac007007 |
#define MATCH_VLOXSEG6EI8V 0xac000007 |
#define MATCH_VLOXSEG7EI16V 0xcc005007 |
#define MATCH_VLOXSEG7EI32V 0xcc006007 |
#define MATCH_VLOXSEG7EI64V 0xcc007007 |
#define MATCH_VLOXSEG7EI8V 0xcc000007 |
#define MATCH_VLOXSEG8EI16V 0xec005007 |
#define MATCH_VLOXSEG8EI32V 0xec006007 |
#define MATCH_VLOXSEG8EI64V 0xec007007 |
#define MATCH_VLOXSEG8EI8V 0xec000007 |
#define MATCH_VLSE16V 0x08005007 |
#define MATCH_VLSE32V 0x08006007 |
#define MATCH_VLSE64V 0x08007007 |
#define MATCH_VLSE8V 0x08000007 |
#define MATCH_VLSEG2E16FFV 0x21005007 |
#define MATCH_VLSEG2E16V 0x20005007 |
#define MATCH_VLSEG2E32FFV 0x21006007 |
#define MATCH_VLSEG2E32V 0x20006007 |
#define MATCH_VLSEG2E64FFV 0x21007007 |
#define MATCH_VLSEG2E64V 0x20007007 |
#define MATCH_VLSEG2E8FFV 0x21000007 |
#define MATCH_VLSEG2E8V 0x20000007 |
#define MATCH_VLSEG3E16FFV 0x41005007 |
#define MATCH_VLSEG3E16V 0x40005007 |
#define MATCH_VLSEG3E32FFV 0x41006007 |
#define MATCH_VLSEG3E32V 0x40006007 |
#define MATCH_VLSEG3E64FFV 0x41007007 |
#define MATCH_VLSEG3E64V 0x40007007 |
#define MATCH_VLSEG3E8FFV 0x41000007 |
#define MATCH_VLSEG3E8V 0x40000007 |
#define MATCH_VLSEG4E16FFV 0x61005007 |
#define MATCH_VLSEG4E16V 0x60005007 |
#define MATCH_VLSEG4E32FFV 0x61006007 |
#define MATCH_VLSEG4E32V 0x60006007 |
#define MATCH_VLSEG4E64FFV 0x61007007 |
#define MATCH_VLSEG4E64V 0x60007007 |
#define MATCH_VLSEG4E8FFV 0x61000007 |
#define MATCH_VLSEG4E8V 0x60000007 |
#define MATCH_VLSEG5E16FFV 0x81005007 |
#define MATCH_VLSEG5E16V 0x80005007 |
#define MATCH_VLSEG5E32FFV 0x81006007 |
#define MATCH_VLSEG5E32V 0x80006007 |
#define MATCH_VLSEG5E64FFV 0x81007007 |
#define MATCH_VLSEG5E64V 0x80007007 |
#define MATCH_VLSEG5E8FFV 0x81000007 |
#define MATCH_VLSEG5E8V 0x80000007 |
#define MATCH_VLSEG6E16FFV 0xa1005007 |
#define MATCH_VLSEG6E16V 0xa0005007 |
#define MATCH_VLSEG6E32FFV 0xa1006007 |
#define MATCH_VLSEG6E32V 0xa0006007 |
#define MATCH_VLSEG6E64FFV 0xa1007007 |
#define MATCH_VLSEG6E64V 0xa0007007 |
#define MATCH_VLSEG6E8FFV 0xa1000007 |
#define MATCH_VLSEG6E8V 0xa0000007 |
#define MATCH_VLSEG7E16FFV 0xc1005007 |
#define MATCH_VLSEG7E16V 0xc0005007 |
#define MATCH_VLSEG7E32FFV 0xc1006007 |
#define MATCH_VLSEG7E32V 0xc0006007 |
#define MATCH_VLSEG7E64FFV 0xc1007007 |
#define MATCH_VLSEG7E64V 0xc0007007 |
#define MATCH_VLSEG7E8FFV 0xc1000007 |
#define MATCH_VLSEG7E8V 0xc0000007 |
#define MATCH_VLSEG8E16FFV 0xe1005007 |
#define MATCH_VLSEG8E16V 0xe0005007 |
#define MATCH_VLSEG8E32FFV 0xe1006007 |
#define MATCH_VLSEG8E32V 0xe0006007 |
#define MATCH_VLSEG8E64FFV 0xe1007007 |
#define MATCH_VLSEG8E64V 0xe0007007 |
#define MATCH_VLSEG8E8FFV 0xe1000007 |
#define MATCH_VLSEG8E8V 0xe0000007 |
#define MATCH_VLSSEG2E16V 0x28005007 |
#define MATCH_VLSSEG2E32V 0x28006007 |
#define MATCH_VLSSEG2E64V 0x28007007 |
#define MATCH_VLSSEG2E8V 0x28000007 |
#define MATCH_VLSSEG3E16V 0x48005007 |
#define MATCH_VLSSEG3E32V 0x48006007 |
#define MATCH_VLSSEG3E64V 0x48007007 |
#define MATCH_VLSSEG3E8V 0x48000007 |
#define MATCH_VLSSEG4E16V 0x68005007 |
#define MATCH_VLSSEG4E32V 0x68006007 |
#define MATCH_VLSSEG4E64V 0x68007007 |
#define MATCH_VLSSEG4E8V 0x68000007 |
#define MATCH_VLSSEG5E16V 0x88005007 |
#define MATCH_VLSSEG5E32V 0x88006007 |
#define MATCH_VLSSEG5E64V 0x88007007 |
#define MATCH_VLSSEG5E8V 0x88000007 |
#define MATCH_VLSSEG6E16V 0xa8005007 |
#define MATCH_VLSSEG6E32V 0xa8006007 |
#define MATCH_VLSSEG6E64V 0xa8007007 |
#define MATCH_VLSSEG6E8V 0xa8000007 |
#define MATCH_VLSSEG7E16V 0xc8005007 |
#define MATCH_VLSSEG7E32V 0xc8006007 |
#define MATCH_VLSSEG7E64V 0xc8007007 |
#define MATCH_VLSSEG7E8V 0xc8000007 |
#define MATCH_VLSSEG8E16V 0xe8005007 |
#define MATCH_VLSSEG8E32V 0xe8006007 |
#define MATCH_VLSSEG8E64V 0xe8007007 |
#define MATCH_VLSSEG8E8V 0xe8000007 |
#define MATCH_VLUXEI16V 0x04005007 |
#define MATCH_VLUXEI32V 0x04006007 |
#define MATCH_VLUXEI64V 0x04007007 |
#define MATCH_VLUXEI8V 0x04000007 |
#define MATCH_VLUXSEG2EI16V 0x24005007 |
#define MATCH_VLUXSEG2EI32V 0x24006007 |
#define MATCH_VLUXSEG2EI64V 0x24007007 |
#define MATCH_VLUXSEG2EI8V 0x24000007 |
#define MATCH_VLUXSEG3EI16V 0x44005007 |
#define MATCH_VLUXSEG3EI32V 0x44006007 |
#define MATCH_VLUXSEG3EI64V 0x44007007 |
#define MATCH_VLUXSEG3EI8V 0x44000007 |
#define MATCH_VLUXSEG4EI16V 0x64005007 |
#define MATCH_VLUXSEG4EI32V 0x64006007 |
#define MATCH_VLUXSEG4EI64V 0x64007007 |
#define MATCH_VLUXSEG4EI8V 0x64000007 |
#define MATCH_VLUXSEG5EI16V 0x84005007 |
#define MATCH_VLUXSEG5EI32V 0x84006007 |
#define MATCH_VLUXSEG5EI64V 0x84007007 |
#define MATCH_VLUXSEG5EI8V 0x84000007 |
#define MATCH_VLUXSEG6EI16V 0xa4005007 |
#define MATCH_VLUXSEG6EI32V 0xa4006007 |
#define MATCH_VLUXSEG6EI64V 0xa4007007 |
#define MATCH_VLUXSEG6EI8V 0xa4000007 |
#define MATCH_VLUXSEG7EI16V 0xc4005007 |
#define MATCH_VLUXSEG7EI32V 0xc4006007 |
#define MATCH_VLUXSEG7EI64V 0xc4007007 |
#define MATCH_VLUXSEG7EI8V 0xc4000007 |
#define MATCH_VLUXSEG8EI16V 0xe4005007 |
#define MATCH_VLUXSEG8EI32V 0xe4006007 |
#define MATCH_VLUXSEG8EI64V 0xe4007007 |
#define MATCH_VLUXSEG8EI8V 0xe4000007 |
#define MATCH_VMACCVV 0xb4002057 |
#define MATCH_VMACCVX 0xb4006057 |
#define MATCH_VMADCVI 0x46003057 |
#define MATCH_VMADCVIM 0x44003057 |
#define MATCH_VMADCVV 0x46000057 |
#define MATCH_VMADCVVM 0x44000057 |
#define MATCH_VMADCVX 0x46004057 |
#define MATCH_VMADCVXM 0x44004057 |
#define MATCH_VMADDVV 0xa4002057 |
#define MATCH_VMADDVX 0xa4006057 |
#define MATCH_VMANDMM 0x66002057 |
#define MATCH_VMANDNMM 0x62002057 |
#define MATCH_VMAXUVV 0x18000057 |
#define MATCH_VMAXUVX 0x18004057 |
#define MATCH_VMAXVV 0x1c000057 |
#define MATCH_VMAXVX 0x1c004057 |
#define MATCH_VMERGEVIM 0x5c003057 |
#define MATCH_VMERGEVVM 0x5c000057 |
#define MATCH_VMERGEVXM 0x5c004057 |
#define MATCH_VMFEQVF 0x60005057 |
#define MATCH_VMFEQVV 0x60001057 |
#define MATCH_VMFGEVF 0x7c005057 |
#define MATCH_VMFGTVF 0x74005057 |
#define MATCH_VMFLEVF 0x64005057 |
#define MATCH_VMFLEVV 0x64001057 |
#define MATCH_VMFLTVF 0x6c005057 |
#define MATCH_VMFLTVV 0x6c001057 |
#define MATCH_VMFNEVF 0x70005057 |
#define MATCH_VMFNEVV 0x70001057 |
#define MATCH_VMINUVV 0x10000057 |
#define MATCH_VMINUVX 0x10004057 |
#define MATCH_VMINVV 0x14000057 |
#define MATCH_VMINVX 0x14004057 |
#define MATCH_VMNANDMM 0x76002057 |
#define MATCH_VMNORMM 0x7a002057 |
#define MATCH_VMORMM 0x6a002057 |
#define MATCH_VMORNMM 0x72002057 |
#define MATCH_VMSBCVV 0x4e000057 |
#define MATCH_VMSBCVVM 0x4c000057 |
#define MATCH_VMSBCVX 0x4e004057 |
#define MATCH_VMSBCVXM 0x4c004057 |
#define MATCH_VMSBFM 0x5000a057 |
#define MATCH_VMSEQVI 0x60003057 |
#define MATCH_VMSEQVV 0x60000057 |
#define MATCH_VMSEQVX 0x60004057 |
#define MATCH_VMSGTUVI 0x78003057 |
#define MATCH_VMSGTUVX 0x78004057 |
#define MATCH_VMSGTVI 0x7c003057 |
#define MATCH_VMSGTVX 0x7c004057 |
#define MATCH_VMSIFM 0x5001a057 |
#define MATCH_VMSLEUVI 0x70003057 |
#define MATCH_VMSLEUVV 0x70000057 |
#define MATCH_VMSLEUVX 0x70004057 |
#define MATCH_VMSLEVI 0x74003057 |
#define MATCH_VMSLEVV 0x74000057 |
#define MATCH_VMSLEVX 0x74004057 |
#define MATCH_VMSLTUVV 0x68000057 |
#define MATCH_VMSLTUVX 0x68004057 |
#define MATCH_VMSLTVV 0x6c000057 |
#define MATCH_VMSLTVX 0x6c004057 |
#define MATCH_VMSNEVI 0x64003057 |
#define MATCH_VMSNEVV 0x64000057 |
#define MATCH_VMSNEVX 0x64004057 |
#define MATCH_VMSOFM 0x50012057 |
#define MATCH_VMULHSUVV 0x98002057 |
#define MATCH_VMULHSUVX 0x98006057 |
#define MATCH_VMULHUVV 0x90002057 |
#define MATCH_VMULHUVX 0x90006057 |
#define MATCH_VMULHVV 0x9c002057 |
#define MATCH_VMULHVX 0x9c006057 |
#define MATCH_VMULVV 0x94002057 |
#define MATCH_VMULVX 0x94006057 |
#define MATCH_VMV1RV 0x9e003057 |
#define MATCH_VMV2RV 0x9e00b057 |
#define MATCH_VMV4RV 0x9e01b057 |
#define MATCH_VMV8RV 0x9e03b057 |
#define MATCH_VMVSX 0x42006057 |
#define MATCH_VMVVI 0x5e003057 |
#define MATCH_VMVVV 0x5e000057 |
#define MATCH_VMVVX 0x5e004057 |
#define MATCH_VMVXS 0x42002057 |
#define MATCH_VMXNORMM 0x7e002057 |
#define MATCH_VMXORMM 0x6e002057 |
#define MATCH_VNCLIPUWI 0xb8003057 |
#define MATCH_VNCLIPUWV 0xb8000057 |
#define MATCH_VNCLIPUWX 0xb8004057 |
#define MATCH_VNCLIPWI 0xbc003057 |
#define MATCH_VNCLIPWV 0xbc000057 |
#define MATCH_VNCLIPWX 0xbc004057 |
#define MATCH_VNCVTXXW 0xb0004057 |
#define MATCH_VNMSACVV 0xbc002057 |
#define MATCH_VNMSACVX 0xbc006057 |
#define MATCH_VNMSUBVV 0xac002057 |
#define MATCH_VNMSUBVX 0xac006057 |
#define MATCH_VNOTV 0x2c0fb057 |
#define MATCH_VNSRAWI 0xb4003057 |
#define MATCH_VNSRAWV 0xb4000057 |
#define MATCH_VNSRAWX 0xb4004057 |
#define MATCH_VNSRLWI 0xb0003057 |
#define MATCH_VNSRLWV 0xb0000057 |
#define MATCH_VNSRLWX 0xb0004057 |
#define MATCH_VORVI 0x28003057 |
#define MATCH_VORVV 0x28000057 |
#define MATCH_VORVX 0x28004057 |
#define MATCH_VQMACCSUVV 0xfc000057 |
#define MATCH_VQMACCSUVX 0xfc004057 |
#define MATCH_VQMACCUSVX 0xf8004057 |
#define MATCH_VQMACCUVV 0xf0000057 |
#define MATCH_VQMACCUVX 0xf0004057 |
#define MATCH_VQMACCVV 0xf4000057 |
#define MATCH_VQMACCVX 0xf4004057 |
#define MATCH_VREDANDVS 0x04002057 |
#define MATCH_VREDMAXUVS 0x18002057 |
#define MATCH_VREDMAXVS 0x1c002057 |
#define MATCH_VREDMINUVS 0x10002057 |
#define MATCH_VREDMINVS 0x14002057 |
#define MATCH_VREDORVS 0x08002057 |
#define MATCH_VREDSUMVS 0x00002057 |
#define MATCH_VREDXORVS 0x0c002057 |
#define MATCH_VREMUVV 0x88002057 |
#define MATCH_VREMUVX 0x88006057 |
#define MATCH_VREMVV 0x8c002057 |
#define MATCH_VREMVX 0x8c006057 |
#define MATCH_VREV8_V 0x4804a057 |
#define MATCH_VRGATHEREI16VV 0x38000057 |
#define MATCH_VRGATHERVI 0x30003057 |
#define MATCH_VRGATHERVV 0x30000057 |
#define MATCH_VRGATHERVX 0x30004057 |
#define MATCH_VROL_VV 0x54000057 |
#define MATCH_VROL_VX 0x54004057 |
#define MATCH_VROR_VI 0x50003057 |
#define MATCH_VROR_VV 0x50000057 |
#define MATCH_VROR_VX 0x50004057 |
#define MATCH_VRSUBVI 0x0c003057 |
#define MATCH_VRSUBVX 0x0c004057 |
#define MATCH_VS1RV 0x02800027 |
#define MATCH_VS2RV 0x22800027 |
#define MATCH_VS4RV 0x62800027 |
#define MATCH_VS8RV 0xe2800027 |
#define MATCH_VSADDUVI 0x80003057 |
#define MATCH_VSADDUVV 0x80000057 |
#define MATCH_VSADDUVX 0x80004057 |
#define MATCH_VSADDVI 0x84003057 |
#define MATCH_VSADDVV 0x84000057 |
#define MATCH_VSADDVX 0x84004057 |
#define MATCH_VSBCVVM 0x48000057 |
#define MATCH_VSBCVXM 0x48004057 |
#define MATCH_VSE16V 0x00005027 |
#define MATCH_VSE32V 0x00006027 |
#define MATCH_VSE64V 0x00007027 |
#define MATCH_VSE8V 0x00000027 |
#define MATCH_VSETIVLI 0xc0007057 |
#define MATCH_VSETVL 0x80007057 |
#define MATCH_VSETVLI 0x00007057 |
#define MATCH_VSEXT_VF2 0x4803a057 |
#define MATCH_VSEXT_VF4 0x4802a057 |
#define MATCH_VSEXT_VF8 0x4801a057 |
#define MATCH_VSHA2CH_VV 0xba002077 |
#define MATCH_VSHA2CL_VV 0xbe002077 |
#define MATCH_VSHA2MS_VV 0xb6002077 |
#define MATCH_VSLIDE1DOWNVX 0x3c006057 |
#define MATCH_VSLIDE1UPVX 0x38006057 |
#define MATCH_VSLIDEDOWNVI 0x3c003057 |
#define MATCH_VSLIDEDOWNVX 0x3c004057 |
#define MATCH_VSLIDEUPVI 0x38003057 |
#define MATCH_VSLIDEUPVX 0x38004057 |
#define MATCH_VSLLVI 0x94003057 |
#define MATCH_VSLLVV 0x94000057 |
#define MATCH_VSLLVX 0x94004057 |
#define MATCH_VSM3C_VI 0xae002077 |
#define MATCH_VSM3ME_VV 0x82002077 |
#define MATCH_VSM4K_VI 0x86002077 |
#define MATCH_VSM4R_VS 0xa6082077 |
#define MATCH_VSM4R_VV 0xa2082077 |
#define MATCH_VSMULVV 0x9c000057 |
#define MATCH_VSMULVX 0x9c004057 |
#define MATCH_VSMV 0x02b00027 |
#define MATCH_VSOXEI16V 0x0c005027 |
#define MATCH_VSOXEI32V 0x0c006027 |
#define MATCH_VSOXEI64V 0x0c007027 |
#define MATCH_VSOXEI8V 0x0c000027 |
#define MATCH_VSOXSEG2EI16V 0x2c005027 |
#define MATCH_VSOXSEG2EI32V 0x2c006027 |
#define MATCH_VSOXSEG2EI64V 0x2c007027 |
#define MATCH_VSOXSEG2EI8V 0x2c000027 |
#define MATCH_VSOXSEG3EI16V 0x4c005027 |
#define MATCH_VSOXSEG3EI32V 0x4c006027 |
#define MATCH_VSOXSEG3EI64V 0x4c007027 |
#define MATCH_VSOXSEG3EI8V 0x4c000027 |
#define MATCH_VSOXSEG4EI16V 0x6c005027 |
#define MATCH_VSOXSEG4EI32V 0x6c006027 |
#define MATCH_VSOXSEG4EI64V 0x6c007027 |
#define MATCH_VSOXSEG4EI8V 0x6c000027 |
#define MATCH_VSOXSEG5EI16V 0x8c005027 |
#define MATCH_VSOXSEG5EI32V 0x8c006027 |
#define MATCH_VSOXSEG5EI64V 0x8c007027 |
#define MATCH_VSOXSEG5EI8V 0x8c000027 |
#define MATCH_VSOXSEG6EI16V 0xac005027 |
#define MATCH_VSOXSEG6EI32V 0xac006027 |
#define MATCH_VSOXSEG6EI64V 0xac007027 |
#define MATCH_VSOXSEG6EI8V 0xac000027 |
#define MATCH_VSOXSEG7EI16V 0xcc005027 |
#define MATCH_VSOXSEG7EI32V 0xcc006027 |
#define MATCH_VSOXSEG7EI64V 0xcc007027 |
#define MATCH_VSOXSEG7EI8V 0xcc000027 |
#define MATCH_VSOXSEG8EI16V 0xec005027 |
#define MATCH_VSOXSEG8EI32V 0xec006027 |
#define MATCH_VSOXSEG8EI64V 0xec007027 |
#define MATCH_VSOXSEG8EI8V 0xec000027 |
#define MATCH_VSRAVI 0xa4003057 |
#define MATCH_VSRAVV 0xa4000057 |
#define MATCH_VSRAVX 0xa4004057 |
#define MATCH_VSRLVI 0xa0003057 |
#define MATCH_VSRLVV 0xa0000057 |
#define MATCH_VSRLVX 0xa0004057 |
#define MATCH_VSSE16V 0x08005027 |
#define MATCH_VSSE32V 0x08006027 |
#define MATCH_VSSE64V 0x08007027 |
#define MATCH_VSSE8V 0x08000027 |
#define MATCH_VSSEG2E16V 0x20005027 |
#define MATCH_VSSEG2E32V 0x20006027 |
#define MATCH_VSSEG2E64V 0x20007027 |
#define MATCH_VSSEG2E8V 0x20000027 |
#define MATCH_VSSEG3E16V 0x40005027 |
#define MATCH_VSSEG3E32V 0x40006027 |
#define MATCH_VSSEG3E64V 0x40007027 |
#define MATCH_VSSEG3E8V 0x40000027 |
#define MATCH_VSSEG4E16V 0x60005027 |
#define MATCH_VSSEG4E32V 0x60006027 |
#define MATCH_VSSEG4E64V 0x60007027 |
#define MATCH_VSSEG4E8V 0x60000027 |
#define MATCH_VSSEG5E16V 0x80005027 |
#define MATCH_VSSEG5E32V 0x80006027 |
#define MATCH_VSSEG5E64V 0x80007027 |
#define MATCH_VSSEG5E8V 0x80000027 |
#define MATCH_VSSEG6E16V 0xa0005027 |
#define MATCH_VSSEG6E32V 0xa0006027 |
#define MATCH_VSSEG6E64V 0xa0007027 |
#define MATCH_VSSEG6E8V 0xa0000027 |
#define MATCH_VSSEG7E16V 0xc0005027 |
#define MATCH_VSSEG7E32V 0xc0006027 |
#define MATCH_VSSEG7E64V 0xc0007027 |
#define MATCH_VSSEG7E8V 0xc0000027 |
#define MATCH_VSSEG8E16V 0xe0005027 |
#define MATCH_VSSEG8E32V 0xe0006027 |
#define MATCH_VSSEG8E64V 0xe0007027 |
#define MATCH_VSSEG8E8V 0xe0000027 |
#define MATCH_VSSRAVI 0xac003057 |
#define MATCH_VSSRAVV 0xac000057 |
#define MATCH_VSSRAVX 0xac004057 |
#define MATCH_VSSRLVI 0xa8003057 |
#define MATCH_VSSRLVV 0xa8000057 |
#define MATCH_VSSRLVX 0xa8004057 |
#define MATCH_VSSSEG2E16V 0x28005027 |
#define MATCH_VSSSEG2E32V 0x28006027 |
#define MATCH_VSSSEG2E64V 0x28007027 |
#define MATCH_VSSSEG2E8V 0x28000027 |
#define MATCH_VSSSEG3E16V 0x48005027 |
#define MATCH_VSSSEG3E32V 0x48006027 |
#define MATCH_VSSSEG3E64V 0x48007027 |
#define MATCH_VSSSEG3E8V 0x48000027 |
#define MATCH_VSSSEG4E16V 0x68005027 |
#define MATCH_VSSSEG4E32V 0x68006027 |
#define MATCH_VSSSEG4E64V 0x68007027 |
#define MATCH_VSSSEG4E8V 0x68000027 |
#define MATCH_VSSSEG5E16V 0x88005027 |
#define MATCH_VSSSEG5E32V 0x88006027 |
#define MATCH_VSSSEG5E64V 0x88007027 |
#define MATCH_VSSSEG5E8V 0x88000027 |
#define MATCH_VSSSEG6E16V 0xa8005027 |
#define MATCH_VSSSEG6E32V 0xa8006027 |
#define MATCH_VSSSEG6E64V 0xa8007027 |
#define MATCH_VSSSEG6E8V 0xa8000027 |
#define MATCH_VSSSEG7E16V 0xc8005027 |
#define MATCH_VSSSEG7E32V 0xc8006027 |
#define MATCH_VSSSEG7E64V 0xc8007027 |
#define MATCH_VSSSEG7E8V 0xc8000027 |
#define MATCH_VSSSEG8E16V 0xe8005027 |
#define MATCH_VSSSEG8E32V 0xe8006027 |
#define MATCH_VSSSEG8E64V 0xe8007027 |
#define MATCH_VSSSEG8E8V 0xe8000027 |
#define MATCH_VSSUBUVV 0x88000057 |
#define MATCH_VSSUBUVX 0x88004057 |
#define MATCH_VSSUBVV 0x8c000057 |
#define MATCH_VSSUBVX 0x8c004057 |
#define MATCH_VSUBVV 0x08000057 |
#define MATCH_VSUBVX 0x08004057 |
#define MATCH_VSUXEI16V 0x04005027 |
#define MATCH_VSUXEI32V 0x04006027 |
#define MATCH_VSUXEI64V 0x04007027 |
#define MATCH_VSUXEI8V 0x04000027 |
#define MATCH_VSUXSEG2EI16V 0x24005027 |
#define MATCH_VSUXSEG2EI32V 0x24006027 |
#define MATCH_VSUXSEG2EI64V 0x24007027 |
#define MATCH_VSUXSEG2EI8V 0x24000027 |
#define MATCH_VSUXSEG3EI16V 0x44005027 |
#define MATCH_VSUXSEG3EI32V 0x44006027 |
#define MATCH_VSUXSEG3EI64V 0x44007027 |
#define MATCH_VSUXSEG3EI8V 0x44000027 |
#define MATCH_VSUXSEG4EI16V 0x64005027 |
#define MATCH_VSUXSEG4EI32V 0x64006027 |
#define MATCH_VSUXSEG4EI64V 0x64007027 |
#define MATCH_VSUXSEG4EI8V 0x64000027 |
#define MATCH_VSUXSEG5EI16V 0x84005027 |
#define MATCH_VSUXSEG5EI32V 0x84006027 |
#define MATCH_VSUXSEG5EI64V 0x84007027 |
#define MATCH_VSUXSEG5EI8V 0x84000027 |
#define MATCH_VSUXSEG6EI16V 0xa4005027 |
#define MATCH_VSUXSEG6EI32V 0xa4006027 |
#define MATCH_VSUXSEG6EI64V 0xa4007027 |
#define MATCH_VSUXSEG6EI8V 0xa4000027 |
#define MATCH_VSUXSEG7EI16V 0xc4005027 |
#define MATCH_VSUXSEG7EI32V 0xc4006027 |
#define MATCH_VSUXSEG7EI64V 0xc4007027 |
#define MATCH_VSUXSEG7EI8V 0xc4000027 |
#define MATCH_VSUXSEG8EI16V 0xe4005027 |
#define MATCH_VSUXSEG8EI32V 0xe4006027 |
#define MATCH_VSUXSEG8EI64V 0xe4007027 |
#define MATCH_VSUXSEG8EI8V 0xe4000027 |
#define MATCH_VT_MASKC 0x607b |
#define MATCH_VT_MASKCN 0x707b |
#define MATCH_VWADDUVV 0xc0002057 |
#define MATCH_VWADDUVX 0xc0006057 |
#define MATCH_VWADDUWV 0xd0002057 |
#define MATCH_VWADDUWX 0xd0006057 |
#define MATCH_VWADDVV 0xc4002057 |
#define MATCH_VWADDVX 0xc4006057 |
#define MATCH_VWADDWV 0xd4002057 |
#define MATCH_VWADDWX 0xd4006057 |
#define MATCH_VWCVTUXXV 0xc0006057 |
#define MATCH_VWCVTXXV 0xc4006057 |
#define MATCH_VWMACCSUVV 0xfc002057 |
#define MATCH_VWMACCSUVX 0xfc006057 |
#define MATCH_VWMACCUSVX 0xf8006057 |
#define MATCH_VWMACCUVV 0xf0002057 |
#define MATCH_VWMACCUVX 0xf0006057 |
#define MATCH_VWMACCVV 0xf4002057 |
#define MATCH_VWMACCVX 0xf4006057 |
#define MATCH_VWMULSUVV 0xe8002057 |
#define MATCH_VWMULSUVX 0xe8006057 |
#define MATCH_VWMULUVV 0xe0002057 |
#define MATCH_VWMULUVX 0xe0006057 |
#define MATCH_VWMULVV 0xec002057 |
#define MATCH_VWMULVX 0xec006057 |
#define MATCH_VWREDSUMUVS 0xc0000057 |
#define MATCH_VWREDSUMVS 0xc4000057 |
#define MATCH_VWSLL_VI 0xd4003057 |
#define MATCH_VWSLL_VV 0xd4000057 |
#define MATCH_VWSLL_VX 0xd4004057 |
#define MATCH_VWSUBUVV 0xc8002057 |
#define MATCH_VWSUBUVX 0xc8006057 |
#define MATCH_VWSUBUWV 0xd8002057 |
#define MATCH_VWSUBUWX 0xd8006057 |
#define MATCH_VWSUBVV 0xcc002057 |
#define MATCH_VWSUBVX 0xcc006057 |
#define MATCH_VWSUBWV 0xdc002057 |
#define MATCH_VWSUBWX 0xdc006057 |
#define MATCH_VXORVI 0x2c003057 |
#define MATCH_VXORVV 0x2c000057 |
#define MATCH_VXORVX 0x2c004057 |
#define MATCH_VZEXT_VF2 0x48032057 |
#define MATCH_VZEXT_VF4 0x48022057 |
#define MATCH_VZEXT_VF8 0x48012057 |
#define MATCH_WFI 0x10500073 |
#define MATCH_WRS_NTO 0x00d00073 |
#define MATCH_WRS_STO 0x01d00073 |
#define MATCH_XNOR 0x40004033 |
#define MATCH_XOR 0x4033 |
#define MATCH_XORI 0x4013 |
#define MATCH_XPERM4 0x28002033 |
#define MATCH_XPERM8 0x28004033 |
#define riscv_breakpoints_debug_printf | ( | fmt, | |
... ) |
Definition at line 84 of file riscv-tdep.c.
Referenced by riscv_breakpoint_kind_from_pc().
#define RISCV_ENCODING_H |
#define riscv_gdbarch_debug_printf | ( | fmt, | |
... ) |
Definition at line 124 of file riscv-tdep.c.
Referenced by riscv_gdbarch_init().
#define riscv_infcall_debug_printf | ( | fmt, | |
... ) |
Definition at line 96 of file riscv-tdep.c.
Referenced by riscv_push_dummy_call(), riscv_push_dummy_code(), and riscv_return_value().
#define RISCV_INFCALL_SCOPED_DEBUG_START_END | ( | fmt, | |
... ) |
Definition at line 102 of file riscv-tdep.c.
Referenced by riscv_push_dummy_call().
#define riscv_unwinder_debug_printf | ( | fmt, | |
... ) |
Definition at line 113 of file riscv-tdep.c.
Referenced by previous_insn_is_add_imm_to_sp(), previous_insn_is_load_fp_from_stack(), riscv_detect_end_of_function(), riscv_frame_cache(), and riscv_scan_prologue().
#define SP_ALIGNMENT 16 |
Definition at line 62 of file riscv-tdep.c.
Referenced by riscv_push_dummy_call().
void _initialize_riscv_tdep | ( | ) |
Definition at line 4547 of file riscv-tdep.c.
References add_setshow_auto_boolean_cmd(), add_setshow_boolean_cmd(), add_setshow_prefix_cmd(), AUTO_BOOLEAN_AUTO, class_maintenance, gdbarch_register(), no_class, riscv_debug_breakpoints, riscv_debug_gdbarch, riscv_debug_infcall, riscv_debug_unwinder, riscv_gdbarch_init(), riscv_init_reggroups(), setdebuglist, setdebugriscvcmdlist, setlist, setriscvcmdlist, show_riscv_debug_variable(), show_use_compressed_breakpoints(), showdebuglist, showdebugriscvcmdlist, showlist, showriscvcmdlist, and use_compressed_breakpoints.
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Definition at line 2018 of file riscv-tdep.c.
References riscv_insn::ADDI, riscv_insn::ADDIW, riscv_insn::rd(), RISCV_SP_REGNUM, and riscv_insn::rs1().
Referenced by previous_insn_is_add_imm_to_sp(), riscv_detect_end_of_function(), and riscv_scan_prologue().
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Definition at line 2002 of file riscv-tdep.c.
References riscv_insn::LD, riscv_insn::LW, riscv_insn::rd(), RISCV_FP_REGNUM, RISCV_SP_REGNUM, and riscv_insn::rs1().
Referenced by previous_insn_is_load_fp_from_stack(), and riscv_detect_end_of_function().
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Definition at line 2074 of file riscv-tdep.c.
References riscv_insn::decode(), is_insn_addi_of_sp_to_sp(), riscv_insn::length(), and riscv_unwinder_debug_printf.
Referenced by riscv_detect_end_of_function().
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Definition at line 2038 of file riscv-tdep.c.
References riscv_insn::decode(), is_insn_load_of_fp_from_sp(), riscv_insn::length(), and riscv_unwinder_debug_printf.
Referenced by riscv_detect_end_of_function().
bool riscv_abi_embedded | ( | struct gdbarch * | gdbarch | ) |
Definition at line 801 of file riscv-tdep.c.
References riscv_gdbarch_tdep::abi_features, riscv_gdbarch_features::embedded, and gdbarch_tdep().
Referenced by riscv_call_info::riscv_call_info().
int riscv_abi_flen | ( | struct gdbarch * | gdbarch | ) |
Definition at line 792 of file riscv-tdep.c.
References riscv_gdbarch_tdep::abi_features, riscv_gdbarch_features::flen, and gdbarch_tdep().
Referenced by riscv_call_info::riscv_call_info(), and riscv_gcc_target_options().
int riscv_abi_xlen | ( | struct gdbarch * | gdbarch | ) |
Definition at line 774 of file riscv-tdep.c.
References riscv_gdbarch_tdep::abi_features, gdbarch_tdep(), and riscv_gdbarch_features::xlen.
Referenced by riscv_call_info::riscv_call_info(), and riscv_gcc_target_options().
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Definition at line 3888 of file riscv-tdep.c.
References csr_reggroup, and reggroup_add().
Referenced by riscv_gdbarch_init().
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Definition at line 3134 of file riscv-tdep.c.
References riscv_arg_info::align, riscv_arg_info::argloc, builtin_type::builtin_long, builtin_type::builtin_long_long, builtin_type(), riscv_arg_info::location::c_length, type::code(), riscv_arg_info::contents, riscv_arg_info::is_unnamed, riscv_arg_info::length, type::length(), riscv_call_arg_complex_float(), riscv_call_arg_scalar_float(), riscv_call_arg_scalar_int(), riscv_call_arg_struct(), riscv_arg_info::type, type, type_align(), TYPE_HAS_DYNAMIC_LENGTH, and riscv_call_info::xlen.
Referenced by riscv_push_dummy_call(), and riscv_return_value().
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Definition at line 2684 of file riscv-tdep.c.
References riscv_arg_reg::last_regnum, and riscv_arg_reg::next_regnum.
Referenced by riscv_call_arg_complex_float(), and riscv_call_arg_struct().
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Definition at line 2702 of file riscv-tdep.c.
References riscv_arg_info::location::in_reg, riscv_arg_reg::last_regnum, loc, and riscv_arg_reg::next_regnum.
Referenced by riscv_call_arg_complex_float(), riscv_call_arg_scalar_float(), riscv_call_arg_scalar_int(), and riscv_call_arg_struct().
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Definition at line 2728 of file riscv-tdep.c.
References riscv_memory_offsets::arg_offset, loc, and riscv_arg_info::location::on_stack.
Referenced by riscv_call_arg_scalar_int().
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Definition at line 836 of file riscv-tdep.c.
References AUTO_BOOLEAN_AUTO, AUTO_BOOLEAN_TRUE, bp, paddress(), riscv_breakpoints_debug_printf, riscv_debug_breakpoints, target_read_code(), and use_compressed_breakpoints.
Referenced by riscv_gdbarch_init().
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Definition at line 2835 of file riscv-tdep.c.
References riscv_arg_info::argloc, riscv_call_info::flen, riscv_call_info::float_regs, riscv_arg_info::is_unnamed, riscv_arg_info::length, riscv_arg_regs_available(), riscv_assign_reg_location(), and riscv_call_arg_scalar_int().
Referenced by riscv_arg_location().
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Definition at line 2816 of file riscv-tdep.c.
References riscv_arg_info::argloc, riscv_call_info::flen, riscv_call_info::float_regs, riscv_arg_info::is_unnamed, riscv_arg_info::length, riscv_assign_reg_location(), and riscv_call_arg_scalar_int().
Referenced by riscv_arg_location().
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Definition at line 2759 of file riscv-tdep.c.
References riscv_arg_info::align, riscv_arg_info::argloc, riscv_arg_info::location::by_ref, riscv_arg_info::location::c_length, riscv_call_info::int_regs, riscv_arg_info::is_unnamed, riscv_arg_info::length, riscv_arg_info::location::loc_data, riscv_arg_info::location::loc_type, riscv_call_info::memory, riscv_arg_reg::next_regnum, riscv_arg_info::location::offset, riscv_memory_offsets::ref_offset, riscv_assign_reg_location(), riscv_assign_stack_location(), riscv_arg_info::type, TYPE_HAS_DYNAMIC_LENGTH, and riscv_call_info::xlen.
Referenced by riscv_arg_location(), riscv_call_arg_complex_float(), riscv_call_arg_scalar_float(), and riscv_call_arg_struct().
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Definition at line 2982 of file riscv-tdep.c.
References riscv_struct_info::analyse(), riscv_arg_info::argloc, type::code(), riscv_struct_info::field_offset(), riscv_struct_info::field_type(), riscv_call_info::flen, riscv_call_info::float_regs, riscv_call_info::int_regs, is_integral_type(), riscv_arg_info::is_unnamed, type::length(), riscv_struct_info::number_of_fields(), riscv_arg_regs_available(), riscv_assign_reg_location(), riscv_call_arg_scalar_int(), riscv_arg_info::type, and riscv_call_info::xlen.
Referenced by riscv_arg_location().
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Definition at line 1038 of file riscv-tdep.c.
References regnum, and RISCV_ZERO_REGNUM.
Referenced by riscv_gdbarch_init().
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Definition at line 2139 of file riscv-tdep.c.
References riscv_insn::decode(), riscv_insn::imm_signed(), is_insn_addi_of_sp_to_sp(), is_insn_load_of_fp_from_sp(), riscv_insn::JALR, riscv_insn::length(), previous_insn_is_add_imm_to_sp(), previous_insn_is_load_fp_from_stack(), RISCV_RA_REGNUM, riscv_unwinder_debug_printf, RISCV_ZERO_REGNUM, riscv_insn::rs1(), and riscv_insn::rs2().
Referenced by riscv_scan_prologue().
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Definition at line 3896 of file riscv-tdep.c.
References RISCV_DWARF_FIRST_CSR, RISCV_DWARF_LAST_CSR, RISCV_DWARF_REGNUM_F0, RISCV_DWARF_REGNUM_F31, RISCV_DWARF_REGNUM_V0, RISCV_DWARF_REGNUM_V31, RISCV_DWARF_REGNUM_X0, RISCV_DWARF_REGNUM_X31, RISCV_FIRST_CSR_REGNUM, RISCV_FIRST_FP_REGNUM, RISCV_V0_REGNUM, and RISCV_ZERO_REGNUM.
Referenced by riscv_gdbarch_init().
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Definition at line 3822 of file riscv-tdep.c.
References riscv_gdbarch_features::embedded, riscv_gdbarch_features::flen, and riscv_gdbarch_features::xlen.
Referenced by riscv_find_default_target_description(), and riscv_gdbarch_init().
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Definition at line 3868 of file riscv-tdep.c.
References riscv_features_from_bfd(), riscv_lookup_target_description(), and riscv_gdbarch_features::xlen.
Referenced by riscv_gdbarch_init().
Definition at line 1046 of file riscv-tdep.c.
References append_composite_type_field(), arch_composite_type(), builtin_type::builtin_double, builtin_type::builtin_float, builtin_type(), f(), gdbarch_tdep(), riscv_gdbarch_tdep::riscv_fpreg_d_type, type::set_is_vector(), and type::set_name().
Referenced by riscv_register_type().
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Definition at line 3701 of file riscv-tdep.c.
Referenced by riscv_gdbarch_init().
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Definition at line 3710 of file riscv-tdep.c.
References trad_frame_saved_reg::addr, riscv_unwind_cache::frame_base, riscv_unwind_cache::frame_base_offset, riscv_unwind_cache::frame_base_reg, frame_id_build(), FRAME_OBSTACK_ZALLOC, gdbarch_num_pseudo_regs(), gdbarch_num_regs(), gdbarch_pc_regnum(), gdbarch_register_name(), gdbarch_sp_regnum(), get_frame_arch(), get_frame_func(), get_frame_pc(), get_frame_register_unsigned(), trad_frame_saved_reg::is_addr(), riscv_unwind_cache::regs, RISCV_RA_REGNUM, riscv_scan_prologue(), riscv_unwinder_debug_printf, trad_frame_saved_reg::set_addr(), trad_frame_saved_reg::set_unknown(), trad_frame_saved_reg::set_value(), riscv_unwind_cache::this_id, and trad_frame_alloc_saved_regs().
Referenced by riscv_frame_prev_register(), and riscv_frame_this_id().
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Definition at line 3791 of file riscv-tdep.c.
References regnum, riscv_unwind_cache::regs, riscv_frame_cache(), and trad_frame_get_prev_register().
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Definition at line 3770 of file riscv-tdep.c.
References riscv_frame_cache(), and riscv_unwind_cache::this_id.
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Definition at line 3919 of file riscv-tdep.c.
References riscv_abi_flen(), riscv_abi_xlen(), riscv_isa_flen(), and riscv_isa_xlen().
Referenced by riscv_gdbarch_init().
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Definition at line 4082 of file riscv-tdep.c.
References riscv_gdbarch_tdep::abi_features, alias, arches, riscv_csr_feature::check(), riscv_freg_feature::check(), riscv_vector_feature::check(), riscv_virtual_feature::check(), riscv_xreg_feature::check(), core_addr_lessthan(), dwarf2_append_unwinders(), riscv_gdbarch_tdep::fflags_regnum, riscv_gdbarch_features::flen, floatformats_ieee_quad, frame_unwind_append_unwinder(), riscv_gdbarch_tdep::frm_regnum, gdbarch_alloc(), gdbarch_init_osabi(), gdbarch_list_lookup_by_info(), gdbarch_num_regs(), gdbarch_tdep(), registry< T >::get(), riscv_gdbarch_features::has_fcsr_reg, riscv_gdbarch_features::has_fflags_reg, riscv_gdbarch_features::has_frm_reg, riscv_gdbarch_tdep::isa_features, ON_STACK, register_riscv_ravenscar_ops(), riscv_add_reggroups(), riscv_breakpoint_kind_from_pc(), riscv_cannot_store_register(), riscv_disassembler_options, riscv_dwarf_reg_to_regnum(), riscv_features_from_bfd(), riscv_find_default_target_description(), riscv_frame_align(), riscv_frame_unwind, riscv_gcc_target_options(), riscv_gdbarch_debug_printf, riscv_gnu_triplet_regexp(), riscv_isa_xlen(), RISCV_LAST_REGNUM, RISCV_PC_REGNUM, riscv_print_registers_info(), riscv_pseudo_register_name(), riscv_pseudo_register_read(), riscv_pseudo_register_reggroup_p(), riscv_pseudo_register_type(), riscv_pseudo_register_write(), riscv_push_dummy_call(), riscv_push_dummy_code(), riscv_register_name(), riscv_register_reggroup_p(), riscv_register_type(), riscv_return_value(), riscv_skip_prologue(), RISCV_SP_REGNUM, riscv_stap_is_single_operand(), riscv_sw_breakpoint_from_kind(), riscv_tdesc_unknown_reg(), riscv_type_align(), set_gdbarch_breakpoint_kind_from_pc(), set_gdbarch_call_dummy_location(), set_gdbarch_cannot_store_register(), set_gdbarch_char_signed(), set_gdbarch_disassembler_options(), set_gdbarch_double_bit(), set_gdbarch_dwarf2_reg_to_regnum(), set_gdbarch_float_bit(), set_gdbarch_frame_align(), set_gdbarch_gcc_target_options(), set_gdbarch_gnu_triplet_regexp(), set_gdbarch_have_nonsteppable_watchpoint(), set_gdbarch_inner_than(), set_gdbarch_int_bit(), set_gdbarch_long_bit(), set_gdbarch_long_double_bit(), set_gdbarch_long_double_format(), set_gdbarch_long_long_bit(), set_gdbarch_num_pseudo_regs(), set_gdbarch_num_regs(), set_gdbarch_pc_regnum(), set_gdbarch_print_registers_info(), set_gdbarch_pseudo_register_read(), set_gdbarch_pseudo_register_write(), set_gdbarch_ptr_bit(), set_gdbarch_push_dummy_call(), set_gdbarch_push_dummy_code(), set_gdbarch_register_name(), set_gdbarch_register_reggroup_p(), set_gdbarch_register_type(), set_gdbarch_return_value_as_value(), set_gdbarch_short_bit(), set_gdbarch_skip_prologue(), set_gdbarch_sp_regnum(), set_gdbarch_stap_is_single_operand(), set_gdbarch_stap_register_indirection_prefixes(), set_gdbarch_stap_register_indirection_suffixes(), set_gdbarch_sw_breakpoint_from_kind(), set_gdbarch_type_align(), set_gdbarch_valid_disassembler_options(), set_tdesc_pseudo_register_name(), set_tdesc_pseudo_register_reggroup_p(), set_tdesc_pseudo_register_type(), stap_register_indirection_prefixes, stap_register_indirection_suffixes, tdesc_data, tdesc_data_alloc(), tdesc_found_register(), tdesc_has_registers(), tdesc_use_registers(), and riscv_gdbarch_features::xlen.
Referenced by _initialize_riscv_tdep().
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Definition at line 4042 of file riscv-tdep.c.
Referenced by riscv_gdbarch_init().
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Definition at line 818 of file riscv-tdep.c.
References riscv_gdbarch_tdep::abi_features, riscv_gdbarch_features::flen, and gdbarch_tdep().
Referenced by riscv_call_info::riscv_call_info(), and riscv_push_dummy_call().
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Definition at line 810 of file riscv-tdep.c.
References riscv_isa_flen().
Referenced by riscv_register_name(), and riscv_register_reggroup_p().
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Definition at line 4476 of file riscv-tdep.c.
References csr_reggroup, reggroup_new(), and USER_REGGROUP.
Referenced by _initialize_riscv_tdep().
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Definition at line 827 of file riscv-tdep.c.
References RISCV_FIRST_FP_REGNUM, and RISCV_LAST_FP_REGNUM.
Referenced by riscv_push_dummy_call(), riscv_regcache_cooked_write(), riscv_register_reggroup_p(), and riscv_register_type().
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Definition at line 1348 of file riscv-tdep.c.
References regnum, RISCV_FIRST_CSR_REGNUM, and RISCV_LAST_CSR_REGNUM.
Referenced by riscv_register_reggroup_p().
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Definition at line 1369 of file riscv-tdep.c.
References gdbarch_tdep(), regnum, riscv_gdbarch_tdep::unknown_csrs_count, and riscv_gdbarch_tdep::unknown_csrs_first_regnum.
Referenced by riscv_register_reggroup_p().
int riscv_isa_flen | ( | struct gdbarch * | gdbarch | ) |
Definition at line 783 of file riscv-tdep.c.
References riscv_gdbarch_features::flen, gdbarch_tdep(), and riscv_gdbarch_tdep::isa_features.
Referenced by riscv_gcc_target_options(), riscv_has_fp_regs(), riscv_iterate_over_regset_sections(), riscv_linux_iterate_over_regset_sections(), riscv_linux_sigframe_init(), and riscv_register_type().
int riscv_isa_xlen | ( | struct gdbarch * | gdbarch | ) |
Definition at line 765 of file riscv-tdep.c.
References gdbarch_tdep(), riscv_gdbarch_tdep::isa_features, and riscv_gdbarch_features::xlen.
Referenced by riscv_insn::decode(), riscv_fbsd_init_abi(), riscv_fbsd_iterate_over_regset_sections(), riscv_fbsd_sigframe_init(), riscv_gcc_target_options(), riscv_gdbarch_init(), riscv_iterate_over_regset_sections(), riscv_linux_init_abi(), riscv_linux_iterate_over_regset_sections(), riscv_linux_sigframe_init(), riscv_ravenscar_ops::riscv_ravenscar_ops(), and riscv_register_type().
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Definition at line 4331 of file riscv-tdep.c.
References reg_buffer::arch(), riscv_insn::BEQ, riscv_insn::BGE, riscv_insn::BGEU, riscv_insn::BLT, riscv_insn::BLTU, riscv_insn::BNE, readable_regcache::cooked_read(), riscv_insn::decode(), riscv_insn::ECALL, gdbarch_tdep(), get_current_frame(), riscv_insn::imm_signed(), riscv_insn::JAL, riscv_insn::JALR, riscv_insn::length(), riscv_insn::rs1(), riscv_insn::rs2(), and riscv_gdbarch_tdep::syscall_next_pc.
Referenced by riscv_software_single_step().
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Definition at line 4411 of file riscv-tdep.c.
References reg_buffer::arch(), riscv_insn::BNE, riscv_insn::decode(), riscv_insn::imm_signed(), riscv_insn::length(), riscv_insn::LR, and riscv_insn::SC.
Referenced by riscv_software_single_step().
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Definition at line 3200 of file riscv-tdep.c.
References riscv_arg_info::location::by_ref, gdb_printf(), gdbarch_register_name(), riscv_arg_info::location::in_reg, riscv_arg_info::location::on_stack, and TYPE_SAFE_NAME.
Referenced by riscv_push_dummy_call(), and riscv_return_value().
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Definition at line 1136 of file riscv-tdep.c.
References type::code(), common_val_print(), value::contents_for_printing(), current_language, value::entirely_available(), type::field(), gdb_printf(), gdb_puts(), gdbarch_register_name(), gdbarch_tdep(), get_formatted_print_options(), get_user_print_options(), type::is_vector(), type::length(), riscv_register_feature::name(), type::num_fields(), value::optimized_out(), print_hex_chars(), print_spaces(), register_size(), regnum, RISCV_PRIV_REGNUM, size, field::type(), value::type(), type_byte_order(), value_as_long(), and value_of_register().
Referenced by riscv_print_registers_info().
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Definition at line 1505 of file riscv-tdep.c.
References all_reggroup, gdbarch_num_cooked_regs(), gdbarch_register_name(), gdbarch_register_reggroup_p(), general_reggroup, regnum, riscv_print_one_register_info(), and RISCV_ZERO_REGNUM.
Referenced by riscv_gdbarch_init().
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Definition at line 1465 of file riscv-tdep.c.
References riscv_gdbarch_tdep::fflags_regnum, riscv_gdbarch_tdep::frm_regnum, gdbarch_tdep(), and regnum.
Referenced by riscv_gdbarch_init().
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Definition at line 974 of file riscv-tdep.c.
References riscv_gdbarch_tdep::fflags_regnum, riscv_gdbarch_tdep::frm_regnum, gdbarch_tdep(), readable_regcache::raw_read_part(), register_size(), regnum, and status.
Referenced by riscv_gdbarch_init().
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Definition at line 1494 of file riscv-tdep.c.
References regnum, and riscv_register_reggroup_p().
Referenced by riscv_gdbarch_init().
Definition at line 1480 of file riscv-tdep.c.
References builtin_type::builtin_int32, builtin_type(), riscv_gdbarch_tdep::fflags_regnum, riscv_gdbarch_tdep::frm_regnum, gdbarch_tdep(), and regnum.
Referenced by riscv_gdbarch_init().
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Definition at line 1010 of file riscv-tdep.c.
References riscv_gdbarch_tdep::fflags_regnum, riscv_gdbarch_tdep::frm_regnum, gdbarch_tdep(), readable_regcache::raw_read(), regcache::raw_write(), register_size(), and regnum.
Referenced by riscv_gdbarch_init().
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Definition at line 3297 of file riscv-tdep.c.
References riscv_memory_offsets::arg_offset, riscv_arg_info::location::by_ref, check_typedef(), type::code(), value::contents(), regcache::cooked_write(), riscv_call_info::flen, gdbarch_byte_order(), type::has_varargs(), riscv_arg_info::location::in_reg, riscv_call_info::int_regs, riscv_call_info::memory, riscv_arg_reg::next_regnum, type::num_fields(), riscv_arg_info::location::on_stack, riscv_memory_offsets::ref_offset, regcache_cooked_write_unsigned(), return_method_struct, RISCV_A0_REGNUM, riscv_arg_location(), riscv_debug_infcall, riscv_has_fp_abi(), riscv_infcall_debug_printf, RISCV_INFCALL_SCOPED_DEBUG_START_END, riscv_is_fp_regno_p(), riscv_print_arg_location(), RISCV_RA_REGNUM, riscv_regcache_cooked_write(), RISCV_SP_REGNUM, SP_ALIGNMENT, store_unsigned_integer(), string_file::string(), type::target_type(), value::type(), value_cast(), write_memory(), and riscv_call_info::xlen.
Referenced by riscv_gdbarch_init().
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Definition at line 2458 of file riscv-tdep.c.
References paddress(), riscv_infcall_debug_printf, status, and target_write_memory().
Referenced by riscv_gdbarch_init().
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Definition at line 3280 of file riscv-tdep.c.
References regcache::cooked_write(), regnum, and riscv_is_fp_regno_p().
Referenced by riscv_push_dummy_call(), and riscv_return_value().
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Definition at line 912 of file riscv-tdep.c.
References riscv_gdbarch_tdep::duplicate_fcsr_regnum, riscv_gdbarch_tdep::duplicate_fflags_regnum, riscv_gdbarch_tdep::duplicate_frm_regnum, gdbarch_tdep(), riscv_register_feature::name(), riscv_freg_feature::register_name(), riscv_xreg_feature::register_name(), regnum, RISCV_FIRST_FP_REGNUM, riscv_has_fp_regs(), RISCV_LAST_FP_REGNUM, RISCV_ZERO_REGNUM, and tdesc_register_name().
Referenced by riscv_gdbarch_init().
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Definition at line 1381 of file riscv-tdep.c.
References all_reggroup, csr_reggroup, default_register_reggroup_p(), riscv_gdbarch_tdep::fflags_regnum, float_reggroup, riscv_gdbarch_tdep::frm_regnum, gdbarch_num_regs(), gdbarch_register_name(), gdbarch_tdep(), general_reggroup, regnum, restore_reggroup, RISCV_FIRST_FP_REGNUM, riscv_has_fp_regs(), riscv_is_fp_regno_p(), riscv_is_regnum_a_named_csr(), riscv_is_unknown_csr(), RISCV_LAST_CSR_REGNUM, RISCV_LAST_FP_REGNUM, RISCV_LAST_REGNUM, RISCV_PRIV_REGNUM, RISCV_V0_REGNUM, RISCV_V31_REGNUM, save_reggroup, system_reggroup, tdesc_register_in_reggroup_p(), and vector_reggroup.
Referenced by riscv_gdbarch_init(), and riscv_pseudo_register_reggroup_p().
Definition at line 1084 of file riscv-tdep.c.
References builtin_type::builtin_data_ptr, builtin_type::builtin_func_ptr, builtin_type(), type::code(), gdbarch_pc_regnum(), type::length(), type::name(), regnum, RISCV_FP_REGNUM, riscv_fpreg_d_type(), RISCV_GP_REGNUM, riscv_is_fp_regno_p(), riscv_isa_flen(), riscv_isa_xlen(), RISCV_RA_REGNUM, RISCV_SP_REGNUM, RISCV_TP_REGNUM, tdesc_register_type(), and type.
Referenced by riscv_gdbarch_init().
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Definition at line 3490 of file riscv-tdep.c.
References value::allocate(), riscv_arg_info::location::by_ref, check_typedef(), value::contents(), value::contents_raw(), readable_regcache::cooked_read_part(), riscv_call_info::flen, riscv_arg_info::location::in_reg, is_fixed_point_type(), type::is_unsigned(), type::length(), riscv_arg_info::location::on_stack, gdb_mpz::read(), regcache_cooked_read_unsigned(), register_size(), regnum, RETURN_VALUE_ABI_PRESERVES_ADDRESS, RETURN_VALUE_REGISTER_CONVENTION, RISCV_A0_REGNUM, riscv_arg_location(), riscv_debug_infcall, riscv_infcall_debug_printf, riscv_print_arg_location(), riscv_regcache_cooked_write(), string_file::string(), value::type(), type_byte_order(), value_at_non_lval(), value_cast(), value_from_contents(), gdb_mpz::write(), and write_memory().
Referenced by riscv_gdbarch_init().
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Definition at line 2210 of file riscv-tdep.c.
References riscv_insn::ADD, riscv_insn::ADDI, riscv_insn::ADDW, riscv_insn::AUIPC, riscv_insn::decode(), pv_area::fetch(), pv_area::find_reg(), riscv_unwind_cache::frame_base_offset, riscv_unwind_cache::frame_base_reg, gdbarch_addr_bit(), gdbarch_register_name(), riscv_insn::imm_signed(), is_insn_addi_of_sp_to_sp(), prologue_value::k, riscv_insn::LD, riscv_insn::length(), riscv_insn::LI, riscv_insn::LUI, riscv_insn::LW, riscv_insn::MV, pv_add(), pv_add_constant(), pv_constant(), pv_is_register(), pv_register(), riscv_insn::rd(), riscv_unwind_cache::regs, riscv_detect_end_of_function(), RISCV_FP_REGNUM, RISCV_NUM_INTEGER_REGS, RISCV_SP_REGNUM, riscv_unwinder_debug_printf, RISCV_ZERO_REGNUM, riscv_insn::rs1(), riscv_insn::rs2(), riscv_insn::SD, trad_frame_saved_reg::set_addr(), skip_prologue_using_sal(), pv_area::store(), and riscv_insn::SW.
Referenced by riscv_frame_cache(), and riscv_skip_prologue().
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Definition at line 2433 of file riscv-tdep.c.
References find_pc_partial_function(), riscv_scan_prologue(), and skip_prologue_using_sal().
Referenced by riscv_gdbarch_init().
std::vector< CORE_ADDR > riscv_software_single_step | ( | struct regcache * | regcache | ) |
Definition at line 4459 of file riscv-tdep.c.
References regcache_read_pc(), riscv_next_pc(), and riscv_next_pc_atomic_sequence().
Referenced by riscv_fbsd_init_abi(), and riscv_linux_init_abi().
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Definition at line 4051 of file riscv-tdep.c.
Referenced by riscv_gdbarch_init().
void riscv_supply_regset | ( | const struct regset * | regset, |
struct regcache * | regcache, | ||
int | regnum, | ||
const void * | regs, | ||
size_t | len ) |
Definition at line 4484 of file riscv-tdep.c.
References reg_buffer::arch(), riscv_gdbarch_tdep::fflags_regnum, riscv_gdbarch_tdep::frm_regnum, gdbarch_num_regs(), gdbarch_tdep(), reg_buffer::get_register_status(), readable_regcache::raw_read(), reg_buffer::raw_supply_integer(), reg_buffer::raw_supply_zeroed(), regnum, RISCV_ZERO_REGNUM, and regcache::supply_regset().
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Definition at line 3962 of file riscv-tdep.c.
References riscv_gdbarch_tdep::duplicate_fcsr_regnum, riscv_gdbarch_tdep::duplicate_fflags_regnum, riscv_gdbarch_tdep::duplicate_frm_regnum, gdbarch_tdep(), riscv_register_feature::name(), tdesc_feature_name(), riscv_gdbarch_tdep::unknown_csrs_count, and riscv_gdbarch_tdep::unknown_csrs_first_regnum.
Referenced by riscv_gdbarch_init().
Definition at line 2506 of file riscv-tdep.c.
References BIGGEST_ALIGNMENT, check_typedef(), type::code(), type::is_vector(), and type::length().
Referenced by riscv_gdbarch_init().
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Definition at line 753 of file riscv-tdep.c.
References gdb_printf(), and cmd_list_element::name.
Referenced by _initialize_riscv_tdep().
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Definition at line 731 of file riscv-tdep.c.
References gdb_printf().
Referenced by _initialize_riscv_tdep().
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Definition at line 168 of file riscv-tdep.c.
References value_of_register().
Referenced by riscv_pending_register_alias::create().
Definition at line 163 of file riscv-tdep.c.
Referenced by riscv_add_reggroups(), riscv_init_reggroups(), and riscv_register_reggroup_p().
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Definition at line 611 of file riscv-tdep.c.
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Definition at line 80 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep(), and riscv_breakpoint_kind_from_pc().
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Definition at line 120 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep().
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Definition at line 92 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep(), riscv_push_dummy_call(), and riscv_return_value().
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Definition at line 109 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep().
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Definition at line 136 of file riscv-tdep.c.
Referenced by riscv_gdbarch_init().
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Definition at line 130 of file riscv-tdep.c.
const char* riscv_feature_name_csr = "org.gnu.gdb.riscv.csr" |
Definition at line 129 of file riscv-tdep.c.
Referenced by riscv_iterate_over_regset_sections().
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Definition at line 131 of file riscv-tdep.c.
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Definition at line 133 of file riscv-tdep.c.
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Definition at line 132 of file riscv-tdep.c.
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Definition at line 3805 of file riscv-tdep.c.
Referenced by riscv_gdbarch_init().
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Definition at line 515 of file riscv-tdep.c.
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Definition at line 720 of file riscv-tdep.c.
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Definition at line 555 of file riscv-tdep.c.
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Definition at line 391 of file riscv-tdep.c.
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Definition at line 747 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep().
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Definition at line 742 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep().
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Definition at line 748 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep().
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Definition at line 743 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep().
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Definition at line 4061 of file riscv-tdep.c.
Referenced by aarch64_linux_init_abi(), amd64_init_abi(), arm_linux_init_abi(), i386_elf_init_abi(), ia64_linux_init_abi(), ppc_linux_init_abi(), riscv_gdbarch_init(), s390_gdbarch_init(), and set_gdbarch_stap_register_indirection_prefixes().
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Definition at line 4069 of file riscv-tdep.c.
Referenced by aarch64_linux_init_abi(), amd64_init_abi(), arm_linux_init_abi(), i386_elf_init_abi(), ia64_linux_init_abi(), ppc_linux_init_abi(), riscv_gdbarch_init(), s390_gdbarch_init(), and set_gdbarch_stap_register_indirection_suffixes().
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Definition at line 726 of file riscv-tdep.c.
Referenced by _initialize_riscv_tdep(), and riscv_breakpoint_kind_from_pc().