49#include "count-one-bits.h"
54#include "gdb/sim-arm.h"
57#include "coff/internal.h"
67#include "gdbsupport/selftest.h"
74#define arm_debug_printf(fmt, ...) \
75 debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__)
84#define MSYMBOL_SET_SPECIAL(msym) \
85 (msym)->set_target_flag_1 (true)
87#define MSYMBOL_IS_SPECIAL(msym) \
88 (msym)->target_flag_1 ()
96 {
return this->value < other.
value; }
225{
"r0",
"r1",
"r2",
"r3",
226 "r4",
"r5",
"r6",
"r7",
227 "r8",
"r9",
"r10",
"r11",
228 "r12",
"sp",
"lr",
"pc",
229 "f0",
"f1",
"f2",
"f3",
230 "f4",
"f5",
"f6",
"f7",
256 int regnum, gdb_byte *buf);
259 int regnum,
const gdb_byte *buf);
315static inline ULONGEST
351 const CORE_ADDR msp_val
353 const CORE_ADDR psp_val
366 if (msp_val == cache->
msp_s)
368 else if (msp_val == cache->
msp_ns)
372 warning (_(
"Invalid state, unable to determine msp alias, assuming "
378 if (psp_val == cache->
psp_s)
380 else if (psp_val == cache->
psp_ns)
384 warning (_(
"Invalid state, unable to determine psp alias, assuming "
390 if (msp_val == cache->
sp)
392 else if (psp_val == cache->
sp)
396 warning (_(
"Invalid state, unable to determine sp alias, assuming "
411 else if (cache->
psp_s == cache->
sp)
415 warning (_(
"Invalid state, unable to determine sp alias, assuming "
466 gdb_assert_not_reached (
"Invalid SP selection");
513 gdb_assert_not_reached (
"Invalid SP selection");
566class arm_instruction_reader
570 virtual uint32_t
read (CORE_ADDR memaddr, bfd_endian byte_order)
const = 0;
575class target_arm_instruction_reader :
public arm_instruction_reader
578 uint32_t
read (CORE_ADDR memaddr, bfd_endian byte_order)
const override
587 (
struct gdbarch *
gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end,
593#define DISPLACED_STEPPING_ARCH_VERSION 5
623 return (cpsr & t_bit) != 0;
644 return (cpsr & t_bit) != 0;
665 = data->section_maps[section_idx];
668 if (!data->section_maps_sorted[section_idx])
670 std::sort (map.begin (), map.end ());
671 data->section_maps_sorted[section_idx] =
true;
675 arm_mapping_symbol_vec::const_iterator it
676 = std::lower_bound (map.begin (), map.end (), map_key);
684 if (it->value == map_key.
value)
687 *start = it->value + sec->
addr ();
692 if (it > map.begin ())
694 arm_mapping_symbol_vec::const_iterator prev_it
698 *start = prev_it->value + sec->
addr ();
699 return prev_it->type;
730 (
unsigned long) memaddr);
852 switch ((addr & 0xff000000))
904 return (val & 0x03fffffc);
926 if (strstr (
name,
"_from_thumb") != NULL)
932 if (startswith (
name,
"__truncdfsf2"))
934 if (startswith (
name,
"__aeabi_d2f"))
938 if (startswith (
name,
"__tls_get_addr"))
940 if (startswith (
name,
"__aeabi_read_tp"))
964#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
965 ((bits ((insn1), 0, 3) << 12) \
966 | (bits ((insn1), 10, 10) << 11) \
967 | (bits ((insn2), 12, 14) << 8) \
968 | bits ((insn2), 0, 7))
972#define EXTRACT_MOVW_MOVT_IMM_A(insn) \
973 ((bits ((insn), 16, 19) << 12) \
974 | bits ((insn), 0, 11))
981 unsigned int count = imm >> 7;
989 return (imm & 0xff) | ((imm & 0xff) << 16);
991 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
993 return (imm & 0xff) | ((imm & 0xff) << 8)
994 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
997 return (0x80 | (imm & 0x7f)) << (32 - count);
1006 return (insn == 0x46bd
1007 || (insn & 0xff80) == 0xb000
1008 || (insn & 0xfe00) == 0xbc00);
1019 CORE_ADDR start, CORE_ADDR limit,
1028 CORE_ADDR unrecognized_pc = 0;
1030 for (i = 0; i < 16; i++)
1034 while (start < limit)
1036 unsigned short insn;
1037 gdb::optional<bool> ra_signed_state;
1041 if ((insn & 0xfe00) == 0xb400)
1051 mask = (insn & 0xff) | ((insn & 0x100) << 6);
1055 if (mask & (1 << regno))
1062 else if ((insn & 0xff80) == 0xb080)
1064 offset = (insn & 0x7f) << 2;
1073 else if ((insn & 0xf800) == 0xa800)
1075 (insn & 0xff) << 2);
1076 else if ((insn & 0xfe00) == 0x1c00
1080 else if ((insn & 0xf800) == 0x3000
1084 else if ((insn & 0xfe00) == 0x1800
1088 regs[
bits (insn, 6, 8)]);
1089 else if ((insn & 0xff00) == 0x4400
1092 int rd = (
bit (insn, 7) << 3) +
bits (insn, 0, 2);
1093 int rm =
bits (insn, 3, 6);
1094 regs[rd] =
pv_add (regs[rd], regs[rm]);
1096 else if ((insn & 0xff00) == 0x4600)
1098 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
1099 int src_reg = (insn & 0x78) >> 3;
1100 regs[dst_reg] = regs[src_reg];
1102 else if ((insn & 0xf800) == 0x9000)
1107 int regno = (insn >> 8) & 0x7;
1110 offset = (insn & 0xff) << 2;
1116 stack.
store (addr, 4, regs[regno]);
1118 else if ((insn & 0xf800) == 0x6000)
1120 int rd =
bits (insn, 0, 2);
1121 int rn =
bits (insn, 3, 5);
1124 offset =
bits (insn, 6, 10) << 2;
1130 stack.
store (addr, 4, regs[rd]);
1132 else if (((insn & 0xf800) == 0x7000
1133 || (insn & 0xf800) == 0x8000)
1137 else if ((insn & 0xf800) == 0xc800
1142 else if ((insn & 0xf800) == 0x9800
1143 || ((insn & 0xf800) == 0x6800
1147 else if ((insn & 0xffc0) == 0x0000
1148 || (insn & 0xffc0) == 0x1c00)
1152 else if ((insn & 0xf800) == 0x2000)
1156 else if ((insn & 0xf800) == 0x4800)
1159 unsigned int constant;
1162 loc = start + 4 +
bits (insn, 0, 7) * 4;
1168 unsigned short inst2;
1171 byte_order_for_code);
1172 uint32_t whole_insn = (insn << 16) | inst2;
1174 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
1180 int j1, j2, imm1, imm2;
1182 imm1 =
sbits (insn, 0, 10);
1183 imm2 =
bits (inst2, 0, 10);
1184 j1 =
bit (inst2, 13);
1185 j2 =
bit (inst2, 11);
1187 offset = ((imm1 << 12) + (imm2 << 1));
1188 offset ^= ((!j2) << 22) | ((!j1) << 23);
1190 nextpc = start + 4 + offset;
1192 if (
bit (inst2, 12) == 0)
1193 nextpc = nextpc & 0xfffffffc;
1196 bit (inst2, 12) != 0))
1200 else if ((insn & 0xffd0) == 0xe900
1204 pv_t addr = regs[
bits (insn, 0, 3)];
1212 if (inst2 & (1 << regno))
1215 stack.
store (addr, 4, regs[regno]);
1219 regs[
bits (insn, 0, 3)] = addr;
1223 else if ((insn & 0xff20) == 0xed20
1224 && (inst2 & 0x0f00) == 0x0b00
1228 pv_t addr = regs[
bits (insn, 0, 3)];
1231 unsigned int number =
bits (inst2, 0, 7) >> 1;
1234 int vd =
bits (inst2, 12, 15) | (
bits (insn, 6, 6) << 4);
1240 for (; number > 0; number--)
1248 regs[
bits (insn, 0, 3)] = addr;
1251 else if ((insn & 0xff50) == 0xe940
1255 int regno1 =
bits (inst2, 12, 15);
1256 int regno2 =
bits (inst2, 8, 11);
1257 pv_t addr = regs[
bits (insn, 0, 3)];
1259 offset = inst2 & 0xff;
1268 stack.
store (addr, 4, regs[regno1]);
1273 regs[
bits (insn, 0, 3)] = addr;
1276 else if ((insn & 0xfff0) == 0xf8c0
1277 && (inst2 & 0x0c00) == 0x0c00
1280 int regno =
bits (inst2, 12, 15);
1281 pv_t addr = regs[
bits (insn, 0, 3)];
1283 offset = inst2 & 0xff;
1292 stack.
store (addr, 4, regs[regno]);
1295 regs[
bits (insn, 0, 3)] = addr;
1298 else if ((insn & 0xfff0) == 0xf8c0
1301 int regno =
bits (inst2, 12, 15);
1304 offset = inst2 & 0xfff;
1310 stack.
store (addr, 4, regs[regno]);
1313 else if ((insn & 0xffd0) == 0xf880
1318 else if ((insn & 0xffd0) == 0xf800
1319 && (inst2 & 0x0d00) == 0x0c00
1324 else if ((insn & 0xffd0) == 0xe890
1326 && (inst2 & 0x8000) == 0x0000
1332 else if ((insn & 0xff70) == 0xe950
1338 else if ((insn & 0xfff0) == 0xf850
1339 && (inst2 & 0x0d00) == 0x0c00
1344 else if ((insn & 0xfff0) == 0xf8d0
1349 else if ((insn & 0xfbf0) == 0xf100
1350 && (inst2 & 0x8000) == 0x0000)
1352 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1353 | (
bits (inst2, 12, 14) << 8)
1354 |
bits (inst2, 0, 7));
1356 regs[
bits (inst2, 8, 11)]
1361 else if ((insn & 0xfbf0) == 0xf200
1362 && (inst2 & 0x8000) == 0x0000)
1364 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1365 | (
bits (inst2, 12, 14) << 8)
1366 |
bits (inst2, 0, 7));
1368 regs[
bits (inst2, 8, 11)]
1372 else if ((insn & 0xfbf0) == 0xf1a0
1373 && (inst2 & 0x8000) == 0x0000)
1375 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1376 | (
bits (inst2, 12, 14) << 8)
1377 |
bits (inst2, 0, 7));
1379 regs[
bits (inst2, 8, 11)]
1384 else if ((insn & 0xfbf0) == 0xf2a0
1385 && (inst2 & 0x8000) == 0x0000)
1387 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1388 | (
bits (inst2, 12, 14) << 8)
1389 |
bits (inst2, 0, 7));
1391 regs[
bits (inst2, 8, 11)]
1395 else if ((insn & 0xfbff) == 0xf04f)
1397 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1398 | (
bits (inst2, 12, 14) << 8)
1399 |
bits (inst2, 0, 7));
1401 regs[
bits (inst2, 8, 11)]
1405 else if ((insn & 0xfbf0) == 0xf240)
1413 else if (insn == 0xea5f
1414 && (inst2 & 0xf0f0) == 0)
1416 int dst_reg = (inst2 & 0x0f00) >> 8;
1417 int src_reg = inst2 & 0xf;
1418 regs[dst_reg] = regs[src_reg];
1421 else if ((insn & 0xff7f) == 0xf85f)
1424 unsigned int constant;
1427 offset =
bits (inst2, 0, 11);
1429 loc = start + 4 + offset;
1431 loc = start + 4 - offset;
1437 else if ((insn & 0xff7f) == 0xe95f)
1440 unsigned int constant;
1443 offset =
bits (inst2, 0, 7) << 2;
1445 loc = start + 4 + offset;
1447 loc = start + 4 - offset;
1456 else if (
IS_PAC (whole_insn))
1460 ra_signed_state =
true;
1467 ra_signed_state =
true;
1469 else if (
IS_BTI (whole_insn))
1473 else if (
IS_PACG (whole_insn))
1477 ra_signed_state =
true;
1483 ra_signed_state =
false;
1495 unrecognized_pc = start;
1501 && ra_signed_state.has_value ())
1506 *ra_signed_state?
"signed" :
"not signed");
1521 unrecognized_pc = start;
1530 if (unrecognized_pc == 0)
1531 unrecognized_pc = start;
1534 return unrecognized_pc;
1563 return unrecognized_pc;
1575 unsigned int *destreg,
int *offset)
1579 unsigned int low, high, address;
1584 unsigned short insn1
1587 if ((insn1 & 0xf800) == 0x4800)
1589 *destreg =
bits (insn1, 8, 10);
1591 address = (pc & 0xfffffffc) + 4 + (
bits (insn1, 0, 7) << 2);
1593 byte_order_for_code);
1595 else if ((insn1 & 0xfbf0) == 0xf240)
1597 unsigned short insn2
1608 if ((insn1 & 0xfbc0) == 0xf2c0)
1611 *destreg =
bits (insn2, 8, 11);
1613 address = (high << 16 | low);
1622 if ((insn & 0x0e5f0000) == 0x041f0000)
1624 address =
bits (insn, 0, 11) + pc + 8;
1626 byte_order_for_code);
1628 *destreg =
bits (insn, 12, 15);
1631 else if ((insn & 0x0ff00000) == 0x03000000)
1638 if ((insn & 0x0ff00000) == 0x03400000)
1641 *destreg =
bits (insn, 12, 15);
1643 address = (high << 16 | low);
1685 unsigned int basereg;
1700 if (stack_chk_guard.
minsym == NULL
1706 unsigned int destreg;
1711 if ((insn & 0xf800) != 0x6800)
1713 if (
bits (insn, 3, 5) != basereg)
1715 destreg =
bits (insn, 0, 2);
1718 byte_order_for_code);
1720 if ((insn & 0xf800) != 0x6000)
1722 if (destreg !=
bits (insn, 0, 2))
1727 unsigned int destreg;
1732 if ((insn & 0x0e500000) != 0x04100000)
1734 if (
bits (insn, 16, 19) != basereg)
1736 destreg =
bits (insn, 12, 15);
1739 4, byte_order_for_code);
1740 if ((insn & 0x0e500000) != 0x04000000)
1742 if (
bits (insn, 12, 15) != destreg)
1748 return pc + offset + 4;
1750 return pc + offset + 8;
1771 CORE_ADDR func_addr, limit_pc;
1778 CORE_ADDR post_prologue_pc
1782 if (post_prologue_pc)
1793 if (post_prologue_pc
1796 || startswith (cust->
producer (),
"GNU ")
1798 return post_prologue_pc;
1800 if (post_prologue_pc != 0)
1802 CORE_ADDR analyzed_limit;
1815 post_prologue_pc, NULL);
1819 NULL, target_arm_instruction_reader ());
1821 if (analyzed_limit != post_prologue_pc)
1824 return post_prologue_pc;
1845 target_arm_instruction_reader ());
1874 CORE_ADDR prologue_start;
1875 CORE_ADDR prologue_end;
1882 if (prologue_end > prologue_start + 64)
1884 prologue_end = prologue_start + 64;
1892 prologue_end = std::min (prologue_end, prev_pc);
1905 if ((insn & 0x0df0f000) == 0x0080d000
1907 || (insn & 0x0df0f000) == 0x0040d000
1909 || (insn & 0x0ffffff0) == 0x01a0d000
1911 || (insn & 0x0fff0000) == 0x08bd0000
1913 || (insn & 0x0fff0000) == 0x049d0000)
1929 gdb_assert ((imm & 0xfffff000) == 0);
1931 uint32_t unrotated_value = imm & 0xff;
1932 uint32_t rotate_amount = (imm & 0xf00) >> 7;
1934 if (rotate_amount == 0)
1935 return unrotated_value;
1937 return ((unrotated_value >> rotate_amount)
1938 | (unrotated_value << (32 - rotate_amount)));
1953 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1955 const arm_instruction_reader &insn_reader)
1959 CORE_ADDR offset, current_pc;
1961 CORE_ADDR unrecognized_pc = 0;
1978 for (current_pc = prologue_start;
1979 current_pc < prologue_end;
1982 uint32_t insn = insn_reader.read (current_pc, byte_order_for_code);
1984 if (insn == 0xe1a0c00d)
1989 else if ((insn & 0xfff00000) == 0xe2800000
1993 int rd =
bits (insn, 12, 15);
1997 else if ((insn & 0xfff00000) == 0xe2400000
2001 int rd =
bits (insn, 12, 15);
2005 else if ((insn & 0xffff0fff) == 0xe52d0004)
2012 regs[
bits (insn, 12, 15)]);
2015 else if ((insn & 0xffff0000) == 0xe92d0000)
2020 int mask = insn & 0xffff;
2027 if (mask & (1 << regno))
2034 else if ((insn & 0xffff0000) == 0xe54b0000
2035 || (insn & 0xffff00f0) == 0xe14b00b0
2036 || (insn & 0xffffc000) == 0xe50b0000)
2041 else if ((insn & 0xffff0000) == 0xe5cd0000
2042 || (insn & 0xffff00f0) == 0xe1cd00b0
2043 || (insn & 0xffffc000) == 0xe58d0000)
2048 else if ((insn & 0xfff00000) == 0xe8800000
2055 else if ((insn & 0xfffff000) == 0xe24cb000)
2060 else if ((insn & 0xfffff000) == 0xe24dd000)
2065 else if ((insn & 0xffff7fff) == 0xed6d0103
2076 else if ((insn & 0xffbf0fff) == 0xec2d0200
2080 int n_saved_fp_regs;
2081 unsigned int fp_start_reg, fp_bound_reg;
2086 if ((insn & 0x800) == 0x800)
2088 if ((insn & 0x40000) == 0x40000)
2089 n_saved_fp_regs = 3;
2091 n_saved_fp_regs = 1;
2095 if ((insn & 0x40000) == 0x40000)
2096 n_saved_fp_regs = 2;
2098 n_saved_fp_regs = 4;
2102 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
2103 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
2107 regs[fp_start_reg++]);
2110 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL)
2115 CORE_ADDR dest =
BranchDest (current_pc, insn);
2122 else if ((insn & 0xf0000000) != 0xe0000000)
2132 else if ((insn & 0xfe500000) == 0xe8100000
2137 else if ((insn & 0xfc500000) == 0xe4100000
2141 else if ((insn & 0xffff0ff0) == 0xe1a00000)
2153 unrecognized_pc = current_pc;
2161 if (unrecognized_pc == 0)
2162 unrecognized_pc = current_pc;
2166 int framereg, framesize;
2198 return unrecognized_pc;
2207 CORE_ADDR prologue_start, prologue_end;
2260 if (prologue_end > prologue_start + 64)
2262 prologue_end = prologue_start + 64;
2272 CORE_ADDR frame_loc;
2273 ULONGEST return_value;
2287 prologue_end = prologue_start + 64;
2291 if (prev_pc < prologue_end)
2292 prologue_end = prev_pc;
2295 target_arm_instruction_reader ());
2303 CORE_ADDR unwound_fp, prev_sp;
2311 if (unwound_fp == 0)
2317 prev_sp = unwound_fp + cache->
framesize;
2339 if (*this_cache == NULL)
2347 if (pc <= tdep->lowest_pc)
2348 return UNWIND_OUTERMOST;
2352 return UNWIND_OUTERMOST;
2354 return UNWIND_NO_REASON;
2369 if (*this_cache == NULL)
2388static struct value *
2397 if (*this_cache == NULL)
2500 bfd_vma start,
size;
2504 if (start <= vma && vma < start +
size)
2529 asection *exidx, *extab;
2530 bfd_vma exidx_vma = 0, extab_vma = 0;
2538 exidx = bfd_get_section_by_name (
objfile->
obfd.get (),
2539 ELF_STRING_ARM_unwind);
2540 gdb::byte_vector exidx_data;
2543 exidx_vma = bfd_section_vma (exidx);
2544 exidx_data.resize (bfd_section_size (exidx));
2546 if (!bfd_get_section_contents (
objfile->
obfd.get (), exidx,
2547 exidx_data.data (), 0,
2548 exidx_data.size ()))
2552 extab = bfd_get_section_by_name (
objfile->
obfd.get (),
".ARM.extab");
2553 gdb::byte_vector extab_data;
2556 extab_vma = bfd_section_vma (extab);
2557 extab_data.resize (bfd_section_size (extab));
2559 if (!bfd_get_section_contents (
objfile->
obfd.get (), extab,
2560 extab_data.data (), 0,
2561 extab_data.size ()))
2567 data->section_maps.resize (
objfile->
obfd->section_count);
2570 for (i = 0; i < exidx_data.size () / 8; i++)
2573 bfd_vma idx = bfd_h_get_32 (
objfile->
obfd, exidx_data.data () + i * 8);
2575 exidx_data.data () + i * 8 + 4);
2576 bfd_vma
addr = 0, word = 0;
2577 int n_bytes = 0, n_words = 0;
2579 gdb_byte *entry = NULL;
2582 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2583 idx += exidx_vma + i * 8;
2596 else if ((val & 0xff000000) == 0x80000000)
2603 else if (!(val & 0x80000000))
2606 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2607 addr += exidx_vma + i * 8 + 4;
2609 if (
addr >= extab_vma &&
addr + 4 <= extab_vma + extab_data.size ())
2612 extab_data.data () +
addr - extab_vma);
2615 if ((word & 0xff000000) == 0x80000000)
2620 else if ((word & 0xff000000) == 0x81000000
2621 || (word & 0xff000000) == 0x82000000)
2625 n_words = ((word >> 16) & 0xff);
2627 else if (!(word & 0x80000000))
2631 int gnu_personality = 0;
2634 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2642 static const char *personality[] =
2644 "__gcc_personality_v0",
2645 "__gxx_personality_v0",
2646 "__gcj_personality_v0",
2647 "__gnu_objc_personality_v0",
2651 CORE_ADDR pc = pers + pers_sec->
offset ();
2654 for (k = 0; personality[k]; k++)
2656 (pc, personality[k],
objfile))
2658 gnu_personality = 1;
2667 &&
addr + 4 <= extab_vma + extab_data.size ())
2671 +
addr - extab_vma));
2674 n_words = ((word >> 24) & 0xff);
2682 if (
addr < extab_vma
2683 ||
addr + 4 * n_words > extab_vma + extab_data.size ())
2684 n_words = n_bytes = 0;
2689 if (n_bytes || n_words)
2693 n_bytes + n_words * 4 + 1);
2696 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2701 extab_data.data () +
addr - extab_vma);
2704 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2705 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2706 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2707 *p++ = (gdb_byte) (word & 0xff);
2716 new_exidx_entry.
addr = idx;
2717 new_exidx_entry.
entry = entry;
2741 std::vector<arm_exidx_entry> &map
2745 auto idx = std::lower_bound (map.begin (), map.end (), map_key);
2751 if (idx < map.end ())
2753 if (idx->addr == map_key.
addr)
2756 *start = idx->addr + sec->
addr ();
2761 if (idx > map.begin ())
2765 *start = idx->addr + sec->
addr ();
2819 if ((insn & 0xc0) == 0)
2821 int offset = insn & 0x3f;
2822 vsp += (offset << 2) + 4;
2824 else if ((insn & 0xc0) == 0x40)
2826 int offset = insn & 0x3f;
2827 vsp -= (offset << 2) + 4;
2829 else if ((insn & 0xf0) == 0x80)
2831 int mask = ((insn & 0xf) << 8) | *entry++;
2841 for (i = 0; i < 12; i++)
2842 if (mask & (1 << i))
2852 else if ((insn & 0xf0) == 0x90)
2854 int reg = insn & 0xf;
2864 else if ((insn & 0xf0) == 0xa0)
2866 int count = insn & 0x7;
2867 int pop_lr = (insn & 0x8) != 0;
2871 for (i = 0; i <= count; i++)
2884 else if (insn == 0xb0)
2895 else if (insn == 0xb1)
2897 int mask = *entry++;
2901 if (mask == 0 || mask >= 16)
2905 for (i = 0; i < 4; i++)
2906 if (mask & (1 << i))
2912 else if (insn == 0xb2)
2914 ULONGEST offset = 0;
2919 offset |= (*entry & 0x7f) << shift;
2922 while (*entry++ & 0x80);
2924 vsp += 0x204 + (offset << 2);
2926 else if (insn == 0xb3)
2928 int start = *entry >> 4;
2929 int count = (*entry++) & 0xf;
2933 if (start + count >= 16)
2937 for (i = 0; i <= count; i++)
2946 else if ((insn & 0xf8) == 0xb8)
2948 int count = insn & 0x7;
2952 for (i = 0; i <= count; i++)
2961 else if (insn == 0xc6)
2963 int start = *entry >> 4;
2964 int count = (*entry++) & 0xf;
2968 if (start + count >= 16)
2972 for (i = 0; i <= count; i++)
2978 else if (insn == 0xc7)
2980 int mask = *entry++;
2984 if (mask == 0 || mask >= 16)
2988 for (i = 0; i < 4; i++)
2989 if (mask & (1 << i))
2995 else if ((insn & 0xf8) == 0xc0)
2997 int count = insn & 0x7;
3001 for (i = 0; i <= count; i++)
3007 else if (insn == 0xc8)
3009 int start = *entry >> 4;
3010 int count = (*entry++) & 0xf;
3014 if (start + count >= 16)
3019 for (i = 0; i <= count; i++)
3025 else if (insn == 0xc9)
3027 int start = *entry >> 4;
3028 int count = (*entry++) & 0xf;
3032 for (i = 0; i <= count; i++)
3038 else if ((insn & 0xf8) == 0xd0)
3040 int count = insn & 0x7;
3044 for (i = 0; i <= count; i++)
3084 void **this_prologue_cache)
3088 CORE_ADDR addr_in_block, exidx_region, func_start;
3127 2, byte_order_for_code, &insn)
3128 && (insn & 0xff00) == 0xdf00 )
3136 4, byte_order_for_code, &insn)
3137 && (insn & 0x0f000000) == 0x0f000000 )
3157 if (func_start > exidx_region)
3167 *this_prologue_cache = cache;
3221 if (*this_cache == NULL)
3241static struct value *
3243 void **this_cache,
int regnum)
3245 if (*this_cache == NULL)
3262 void **this_prologue_cache)
3329 enum bfd_endian byte_order_for_code
3334 if ((insn & 0xff80) == 0x4700)
3375 if (*this_cache == NULL)
3388 void **this_prologue_cache)
3390 CORE_ADDR addr_in_block;
3392 CORE_ADDR pc, start_addr;
3456 warning (_(
"ARM M in lockup state, stack unwinding terminated."));
3469 if (lr == 0xffffffff)
3477 bool fnc_return = (((lr >> 24) & 0xff) == 0xfe);
3483 error (_(
"While unwinding an exception frame, found unexpected Link "
3484 "Register value %s that requires the security extension, "
3485 "but the extension was not found or is disabled. This "
3486 "should not happen and may be caused by corrupt data or a "
3492 warning (_(
"Non-secure to secure stack unwinding disabled."));
3500 if ((xpsr & 0x1ff) != 0)
3532 bool exc_return = (((lr >> 24) & 0xff) == 0xff);
3536 bool secure_stack_used =
false;
3537 bool default_callee_register_stacking =
false;
3538 bool exception_domain_is_secure =
false;
3542 bool process_stack_used = (
bit (lr, 2) != 0);
3546 secure_stack_used = (
bit (lr, 6) != 0);
3547 default_callee_register_stacking = (
bit (lr, 5) != 0);
3548 exception_domain_is_secure = (
bit (lr, 0) != 0);
3554 if (secure_stack_used && !exception_domain_is_secure
3557 warning (_(
"Non-secure to secure stack unwinding disabled."));
3564 if (process_stack_used)
3566 if (secure_stack_used)
3575 if (secure_stack_used)
3585 if (process_stack_used)
3654 uint32_t sp_r0_offset = 0;
3658 && (!default_callee_register_stacking || !exception_domain_is_secure))
3669 sp_r0_offset = 0x28;
3691 bool extended_frame_used = (
bit (lr, 4) == 0);
3692 if (extended_frame_used)
3699 byte_order, &fpccr))
3701 warning (_(
"Could not fetch required FPCCR content. Further "
3702 "unwinding is impossible."));
3709 byte_order, &fpcar))
3711 warning (_(
"Could not fetch FPCAR content. Further unwinding of "
3712 "FP register values will be unreliable."));
3716 bool fpccr_aspen =
bit (fpccr, 31);
3717 bool fpccr_lspen =
bit (fpccr, 30);
3718 bool fpccr_ts =
bit (fpccr, 26);
3719 bool fpccr_lspact =
bit (fpccr, 0);
3727 bool fpcar_points_to_this_frame = ((unwound_sp + sp_r0_offset + 0x20)
3729 bool read_fp_regs_from_stack = (!(fpccr_aspen && fpccr_lspen
3731 && fpcar_points_to_this_frame));
3734 if (read_fp_regs_from_stack)
3736 CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x20;
3737 for (
int i = 0; i < 8; i++)
3744 + sp_r0_offset + 0x60);
3746 if (tdep->
have_sec_ext && !default_callee_register_stacking
3750 if (read_fp_regs_from_stack)
3752 CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x68;
3753 for (
int i = 8; i < 16; i++)
3761 unwound_sp + sp_r0_offset + 0xA8);
3767 unwound_sp + sp_r0_offset + 0x68);
3774 unwound_sp + sp_r0_offset + 0x20);
3785 warning (_(
"Could not fetch required XPSR content. Further "
3786 "unwinding is impossible."));
3791 if (
bit (xpsr, 9) != 0)
3800 internal_error (_(
"While unwinding an exception frame, "
3801 "found unexpected Link Register value "
3802 "%s. This should not happen and may "
3803 "be caused by corrupt data or a bug in"
3818 if (*this_cache == NULL)
3824 return UNWIND_OUTERMOST;
3826 return UNWIND_NO_REASON;
3839 if (*this_cache == NULL)
3853static struct value *
3861 if (*this_cache == NULL)
3920 void **this_prologue_cache)
3937 "arm m exception lockup sec_fnc",
3951 if (*this_cache == NULL)
3979static struct value *
4017 else if (tdep->
is_m)
4041 CORE_ADDR ra_auth_code
4045 if (ra_auth_code != 0)
4064 bool override_with_sp_value =
false;
4072 && (cache->
msp_s == cache->
sp);
4078 && (cache->
psp_s == cache->
sp);
4082 override_with_sp_value = is_msp || is_msp_s || is_msp_ns
4083 || is_psp || is_psp_s || is_psp_ns;
4086 else if (tdep->
is_m)
4089 && (cache->
sp == cache->
msp);
4091 && (cache->
sp == cache->
psp);
4093 override_with_sp_value = is_msp || is_psp;
4096 if (override_with_sp_value)
4112 internal_error (_(
"Unexpected register %d"),
regnum);
4121 unsigned int insn, insn2;
4122 int found_return = 0, found_stack_adjust = 0;
4123 CORE_ADDR func_start, func_end;
4148 while (scan_pc < func_end && !found_return)
4156 if ((insn & 0xff80) == 0x4700)
4158 else if (insn == 0x46f7)
4162 if ((insn & 0xff00) == 0xbd00)
4178 else if (insn == 0xf85d
4179 && (insn2 & 0x0fff) == 0x0b04)
4181 if ((insn2 & 0xf000) == 0xf000)
4184 else if ((insn & 0xffbf) == 0xecbd
4185 && (insn2 & 0x0e00) == 0x0a00)
4203 if (pc - 4 < func_start)
4212 found_stack_adjust = 1;
4213 else if (insn == 0xe8bd)
4214 found_stack_adjust = 1;
4215 else if (insn == 0xf85d
4216 && (insn2 & 0x0fff) == 0x0b04)
4217 found_stack_adjust = 1;
4218 else if ((insn & 0xffbf) == 0xecbd
4219 && (insn2 & 0x0e00) == 0x0a00)
4220 found_stack_adjust = 1;
4222 return found_stack_adjust;
4231 CORE_ADDR func_start, func_end;
4246 if ((insn & 0x0ffffff0) == 0x012fff10)
4249 else if ((insn & 0x0ffffff0) == 0x01a0f000)
4252 else if ((insn & 0x0fff0000) == 0x08bd0000
4253 && (insn & 0x0000c000) != 0)
4264 if (pc < func_start + 4)
4304 memcpy (si->
data, contents,
len);
4367 internal_error (_(
"Invalid VFP CPRC type: %d."),
4389 internal_error (_(
"Invalid VFP CPRC type: %d."),
4436 case TYPE_CODE_COMPLEX:
4468 case TYPE_CODE_ARRAY:
4499 gdb_assert (count == 0);
4502 else if (count == 0)
4505 gdb_assert ((t->
length () % unitlen) == 0);
4506 return t->
length () / unitlen;
4511 case TYPE_CODE_STRUCT:
4523 if (sub_count == -1)
4529 gdb_assert (count == 0);
4532 else if (count == 0)
4535 if (t->
length () != unitlen * count)
4540 case TYPE_CODE_UNION:
4549 if (sub_count == -1)
4551 count = (count > sub_count ? count : sub_count);
4555 gdb_assert (count == 0);
4558 else if (count == 0)
4561 if (t->
length () != unitlen * count)
4585 if (c <= 0 || c > 4)
4621 struct value **args, CORE_ADDR sp,
4623 CORE_ADDR struct_addr)
4632 unsigned vfp_regs_free = (1 << 16) - 1;
4638 if (ftype->
code () == TYPE_CODE_PTR)
4668 for (argnum = 0; argnum < nargs; argnum++)
4671 struct type *arg_type;
4674 const bfd_byte *val;
4678 int may_use_core_reg = 1;
4681 len = arg_type->
length ();
4683 typecode = arg_type->
code ();
4718 may_use_core_reg = 0;
4721 shift = unit_length / 4;
4722 mask = (1 << (shift * vfp_base_count)) - 1;
4723 for (regno = 0; regno < 16; regno += shift)
4724 if (((vfp_regs_free >> regno) & mask) == mask)
4733 vfp_regs_free &= ~(mask << regno);
4734 reg_scaled = regno / shift;
4736 for (i = 0; i < vfp_base_count; i++)
4740 if (reg_char ==
'q')
4742 val + i * unit_length);
4745 xsnprintf (name_buf,
sizeof (name_buf),
"%c%d",
4746 reg_char, reg_scaled + i);
4763 if (nstack & (align - 1))
4770 if (may_use_core_reg
4779 if (TYPE_CODE_PTR == typecode
4786 bfd_byte *copy = (bfd_byte *) alloca (len);
4807 if (byte_order == BFD_ENDIAN_BIG)
4821 memset (buf, 0,
sizeof (buf));
4860 return sp & ~ (CORE_ADDR) 7;
4866 if (
flags & (1 << 0))
4868 if (
flags & (1 << 1))
4870 if (
flags & (1 << 2))
4872 if (
flags & (1 << 3))
4874 if (
flags & (1 << 4))
4922 struct type *t, *elem;
4961 struct type *t, *elem;
5092 && t->
code () == TYPE_CODE_FLT
5125 if (reg >= 0 && reg <= 15)
5132 if (reg >= 16 && reg <= 23)
5136 if (reg >= 96 && reg <= 103)
5140 if (reg >= 104 && reg <= 111)
5143 if (reg >= 112 && reg <= 127)
5157 if (reg >= 192 && reg <= 199)
5168 if (reg >= 64 && reg <= 95)
5172 xsnprintf (name_buf,
sizeof (name_buf),
"s%d", reg - 64);
5179 if (reg >= 256 && reg <= 287)
5183 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", reg - 256);
5208 return SIM_ARM_R0_REGNUM + reg;
5212 return SIM_ARM_FP0_REGNUM + reg;
5216 return SIM_ARM_FPS_REGNUM + reg;
5219 internal_error (_(
"Bad REGNUM %d"),
regnum);
5261 int old_len,
int new_len)
5264 int bytes_to_read = new_len - old_len;
5266 new_buf = (gdb_byte *)
xmalloc (new_len);
5267 memcpy (new_buf + bytes_to_read, buf, old_len);
5281#define MAX_IT_BLOCK_PREFIX 14
5285#define IT_SCAN_THRESHOLD 32
5295 CORE_ADDR boundary, func_start;
5298 int i, any, last_it, last_it_count;
5321 && func_start > boundary)
5322 boundary = func_start;
5333 buf = (gdb_byte *)
xmalloc (buf_len);
5337 for (i = 0; i < buf_len; i += 2)
5340 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5373 for (i = 0; i < buf_len -
sizeof (buf) && ! definite; i += 2)
5394 buf_len = bpaddr - boundary;
5403 buf_len = bpaddr - boundary;
5414 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5419 else if (inst1 & 0x0002)
5421 else if (inst1 & 0x0004)
5435 if (last_it_count < 1)
5441 return bpaddr - buf_len + last_it;
5466#define ARM_NOP 0xe1a00000
5467#define THUMB_NOP 0x4600
5494 (
unsigned long) from);
5495 return (ULONGEST) from;
5502 regno, (
unsigned long) ret);
5516 return (ps & t_bit) == 0;
5529 val & ~(ULONGEST) 0x3);
5532 val & ~(ULONGEST) 0x1);
5550 else if ((val & 2) == 0)
5559 warning (_(
"Single-stepping BX to non-word-aligned ARM instruction."));
5620 warning (_(
"Instruction wrote to PC in an unexpected way when "
5621 "single-stepping"));
5625 internal_error (_(
"Invalid argument to displaced_write_reg"));
5633 regno, (
unsigned long) val);
5647 uint32_t lowbit = 1;
5649 while (bitmask != 0)
5653 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5659 mask = lowbit * 0xf;
5661 if ((insn & mask) == mask)
5678 (
unsigned long) insn, iname);
5687 uint16_t insn2,
const char *iname,
5691 "unmodified", insn1, insn2, iname);
5749 unsigned int rn =
bits (insn, 16, 19);
5756 dsc->
modinsn[0] = insn & 0xfff0ffff;
5767 unsigned int rn =
bits (insn1, 0, 3);
5768 unsigned int u_bit =
bit (insn1, 7);
5769 int imm12 =
bits (insn2, 0, 11);
5778 (
unsigned int) dsc->
insn_addr, u_bit ?
'+' :
'-',
5801 dsc->
modinsn[0] = insn1 & 0xfff0;
5816 ULONGEST rn_val, rm_val;
5840 unsigned int rn =
bits (insn, 16, 19);
5841 unsigned int rm =
bits (insn, 0, 3);
5848 (
unsigned long) insn);
5850 dsc->
modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5874 int writeback,
unsigned int rn)
5889 rn_val = rn_val & 0xfffffffc;
5903 unsigned int rn =
bits (insn, 16, 19);
5909 (
unsigned long) insn);
5911 dsc->
modinsn[0] = insn & 0xfff0ffff;
5920 uint16_t insn2,
struct regcache *regs,
5923 unsigned int rn =
bits (insn1, 0, 3);
5927 "copro load/store", dsc);
5932 dsc->
modinsn[0] = insn1 & 0xfff0;
5966 next_insn_addr |= 0x1;
5980 unsigned int cond,
int exchange,
int link,
long offset)
5995 if (link && exchange)
6010 unsigned int cond =
bits (insn, 28, 31);
6011 int exchange = (cond == 0xf);
6012 int link = exchange ||
bit (insn, 24);
6016 (exchange) ?
"blx" : (link) ?
"bl" :
"b",
6017 (
unsigned long) insn);
6021 offset = (
bits (insn, 0, 23) << 2) | (
bit (insn, 24) << 1) | 1;
6023 offset =
bits (insn, 0, 23) << 2;
6025 if (
bit (offset, 25))
6026 offset = offset | ~0x3ffffff;
6036 uint16_t insn2,
struct regcache *regs,
6039 int link =
bit (insn2, 14);
6040 int exchange = link && !
bit (insn2, 12);
6043 int j1 =
bit (insn2, 13);
6044 int j2 =
bit (insn2, 11);
6045 int s =
sbits (insn1, 10, 10);
6046 int i1 = !(j1 ^
bit (insn1, 10));
6047 int i2 = !(j2 ^
bit (insn1, 10));
6049 if (!link && !exchange)
6051 offset = (
bits (insn2, 0, 10) << 1);
6052 if (
bit (insn2, 12))
6054 offset |= (
bits (insn1, 0, 9) << 12)
6062 offset |= (
bits (insn1, 0, 5) << 12)
6066 cond =
bits (insn1, 6, 9);
6071 offset = (
bits (insn1, 0, 9) << 12);
6072 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6073 offset |= exchange ?
6074 (
bits (insn2, 1, 10) << 2) : (
bits (insn2, 0, 10) << 1);
6078 link ? (exchange) ?
"blx" :
"bl" :
"b",
6079 insn1, insn2, offset);
6092 unsigned int cond = 0;
6094 unsigned short bit_12_15 =
bits (insn, 12, 15);
6097 if (bit_12_15 == 0xd)
6100 offset =
sbits ((insn << 1), 0, 8);
6101 cond =
bits (insn, 8, 11);
6103 else if (bit_12_15 == 0xe)
6105 offset =
sbits ((insn << 1), 0, 11);
6129 unsigned int cond,
unsigned int rm)
6153 unsigned int cond =
bits (insn, 28, 31);
6156 int link =
bit (insn, 5);
6157 unsigned int rm =
bits (insn, 0, 3);
6172 int link =
bit (insn, 7);
6173 unsigned int rm =
bits (insn, 3, 6);
6201 unsigned int rn =
bits (insn, 16, 19);
6202 unsigned int rd =
bits (insn, 12, 15);
6203 unsigned int op =
bits (insn, 21, 24);
6204 int is_mov = (op == 0xd);
6205 ULONGEST rd_val, rn_val;
6211 is_mov ?
"move" :
"ALU",
6212 (
unsigned long) insn);
6235 dsc->
modinsn[0] = insn & 0xfff00fff;
6237 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6246 uint16_t insn2,
struct regcache *regs,
6249 unsigned int op =
bits (insn1, 5, 8);
6250 unsigned int rn, rm, rd;
6251 ULONGEST rd_val, rn_val;
6253 rn =
bits (insn1, 0, 3);
6254 rm =
bits (insn2, 0, 3);
6255 rd =
bits (insn2, 8, 11);
6258 gdb_assert (op == 0x2 && rn == 0xf);
6286 dsc->
modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6305 for (i = 0; i < 3; i++)
6314 unsigned int rd,
unsigned int rn,
unsigned int rm)
6316 ULONGEST rd_val, rn_val, rm_val;
6348 unsigned int op =
bits (insn, 21, 24);
6349 int is_mov = (op == 0xd);
6355 is_mov ?
"move" :
"ALU", (
unsigned long) insn);
6358 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6360 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6374 rm =
bits (insn, 3, 6);
6375 rd = (
bit (insn, 7) << 3) |
bits (insn, 0, 2);
6382 dsc->
modinsn[0] = ((insn & 0xff00) | 0x10);
6399 for (i = 0; i < 4; i++)
6408 unsigned int rd,
unsigned int rn,
unsigned int rm,
6412 ULONGEST rd_val, rn_val, rm_val, rs_val;
6428 for (i = 0; i < 4; i++)
6448 unsigned int op =
bits (insn, 21, 24);
6449 int is_mov = (op == 0xd);
6450 unsigned int rd, rn, rm, rs;
6456 is_mov ?
"move" :
"ALU",
6457 (
unsigned long) insn);
6459 rn =
bits (insn, 16, 19);
6460 rm =
bits (insn, 0, 3);
6461 rs =
bits (insn, 8, 11);
6462 rd =
bits (insn, 12, 15);
6465 dsc->
modinsn[0] = (insn & 0xfff000f0) | 0x302;
6467 dsc->
modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6480 ULONGEST rt_val, rt_val2 = 0, rn_val;
6532 unsigned int op1 =
bits (insn, 20, 24);
6533 unsigned int op2 =
bits (insn, 5, 6);
6534 unsigned int rt =
bits (insn, 12, 15);
6535 unsigned int rn =
bits (insn, 16, 19);
6536 unsigned int rm =
bits (insn, 0, 3);
6537 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6538 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6539 int immed = (op1 & 0x4) != 0;
6541 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6547 unprivileged ?
"unprivileged " :
"",
6548 (
unsigned long) insn);
6550 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6553 internal_error (_(
"copy_extra_ld_st: instruction decode error"));
6562 if (bytesize[opcode] == 8)
6569 if (bytesize[opcode] == 8)
6586 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6591 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6603 int immed,
int writeback,
int size,
int usermode,
6604 int rt,
int rm,
int rn)
6606 ULONGEST rt_val, rn_val, rm_val = 0;
6657 uint16_t insn2,
struct regcache *regs,
6660 unsigned int u_bit =
bit (insn1, 7);
6661 unsigned int rt =
bits (insn2, 12, 15);
6662 int imm12 =
bits (insn2, 0, 11);
6666 (
unsigned int) dsc->
insn_addr, rt, u_bit ?
'+' :
'-',
6687 pc_val = pc_val & 0xfffffffc;
6711 uint16_t insn2,
struct regcache *regs,
6713 int writeback,
int immed)
6715 unsigned int rt =
bits (insn2, 12, 15);
6716 unsigned int rn =
bits (insn1, 0, 3);
6717 unsigned int rm =
bits (insn2, 0, 3);
6726 rt, rn, insn1, insn2);
6738 dsc->
modinsn[0] = (insn1 & 0xfff0) | 0x2;
6739 dsc->
modinsn[1] = insn2 & 0x0fff;
6746 dsc->
modinsn[0] = (insn1 & 0xfff0) | 0x2;
6747 dsc->
modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6760 int load,
int size,
int usermode)
6762 int immed = !
bit (insn, 25);
6763 int writeback = (
bit (insn, 24) == 0 ||
bit (insn, 21) != 0);
6764 unsigned int rt =
bits (insn, 12, 15);
6765 unsigned int rn =
bits (insn, 16, 19);
6766 unsigned int rm =
bits (insn, 0, 3);
6772 load ? (
size == 1 ?
"ldrb" :
"ldr")
6773 : (
size == 1 ?
"strb" :
"str"),
6774 usermode ?
"t" :
"",
6776 (
unsigned long) insn);
6779 usermode, rt, rm, rn);
6789 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6794 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6808 dsc->
modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6810 dsc->
modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6845 int bump_before = dsc->
u.
block.
before ? (inc ? 4 : -4) : 0;
6846 int bump_after = dsc->
u.
block.
before ? 0 : (inc ? 4 : -4);
6848 int regno = inc ? 0 : 15;
6851 && (regmask & 0x8000) != 0;
6861 if (exception_return)
6862 error (_(
"Cannot single-step exception return"));
6877 while (regno <=
ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6880 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6883 xfer_addr += bump_before;
6888 xfer_addr += bump_after;
6890 regmask &= ~(1 << regno);
6906 CORE_ADDR pc_stored_at, transferred_regs
6908 CORE_ADDR stm_insn_addr;
6914 if (!store_executed)
6934 offset = pc_val - stm_insn_addr;
6958 unsigned int regs_loaded = count_one_bits (mask);
6959 unsigned int num_to_shuffle = regs_loaded, clobbered;
6963 gdb_assert (num_to_shuffle < 16);
6968 clobbered = (1 << num_to_shuffle) - 1;
6970 while (num_to_shuffle > 0)
6972 if ((mask & (1 << write_reg)) != 0)
6974 unsigned int read_reg = num_to_shuffle - 1;
6976 if (read_reg != write_reg)
6981 read_reg, write_reg);
6985 "place", write_reg);
6987 clobbered &= ~(1 << write_reg);
6996 for (write_reg = 0; clobbered != 0; write_reg++)
6998 if ((clobbered & (1 << write_reg)) != 0)
7004 clobbered &= ~(1 << write_reg);
7014 new_rn_val += regs_loaded * 4;
7016 new_rn_val -= regs_loaded * 4;
7031 int load =
bit (insn, 20);
7032 int user =
bit (insn, 22);
7033 int increment =
bit (insn, 23);
7034 int before =
bit (insn, 24);
7035 int writeback =
bit (insn, 21);
7036 int rn =
bits (insn, 16, 19);
7045 warning (_(
"displaced: Unpredictable LDM or STM with "
7046 "base register r15"));
7051 (
unsigned long) insn);
7067 if ((insn & 0xffff) == 0xffff)
7084 unsigned int regmask = insn & 0xffff;
7085 unsigned int num_in_list = count_one_bits (regmask), new_regmask;
7088 for (i = 0; i < num_in_list; i++)
7110 new_regmask = (1 << num_in_list) - 1;
7113 "%.4x, modified list %.4x",
7114 rn, writeback ?
"!" :
"",
7115 (int) insn & 0xffff, new_regmask);
7117 dsc->
modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7143 int rn =
bits (insn1, 0, 3);
7144 int load =
bit (insn1, 4);
7145 int writeback =
bit (insn1, 5);
7154 warning (_(
"displaced: Unpredictable LDM or STM with "
7155 "base register r15"));
7157 "unpredictable ldm/stm", dsc);
7185 unsigned int num_in_list = count_one_bits (regmask), new_regmask;
7188 for (i = 0; i < num_in_list; i++)
7194 new_regmask = (1 << num_in_list) - 1;
7197 "%.4x, modified list %.4x",
7198 rn, writeback ?
"!" :
"",
7202 dsc->
modinsn[1] = (new_regmask & 0xffff);
7226 (
enum bfd_endian) byte_order);
7259std::vector<CORE_ADDR>
7274 for (CORE_ADDR &pc_ref : next_pcs)
7290 (
unsigned long) resume_addr);
7326 (
unsigned long) insn);
7352 (
unsigned long) insn);
7365 (
unsigned short) insn1, (
unsigned short) insn2);
7381 (
unsigned long) insn);
7396 unsigned int op1 =
bits (insn, 20, 26), op2 =
bits (insn, 4, 7);
7397 unsigned int rn =
bits (insn, 16, 19);
7399 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
7401 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
7403 else if ((op1 & 0x60) == 0x20)
7405 else if ((op1 & 0x71) == 0x40)
7408 else if ((op1 & 0x77) == 0x41)
7410 else if ((op1 & 0x77) == 0x45)
7412 else if ((op1 & 0x77) == 0x51)
7419 else if ((op1 & 0x77) == 0x55)
7421 else if (op1 == 0x57)
7430 else if ((op1 & 0x63) == 0x43)
7432 else if ((op2 & 0x1) == 0x0)
7433 switch (op1 & ~0x80)
7439 case 0x71:
case 0x75:
7442 case 0x63:
case 0x67:
case 0x73:
case 0x77:
7456 if (
bit (insn, 27) == 0)
7459 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7467 case 0x4:
case 0x5:
case 0x6:
case 0x7:
7471 switch ((insn & 0xe00000) >> 21)
7473 case 0x1:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
7486 int rn_f = (
bits (insn, 16, 19) == 0xf);
7487 switch ((insn & 0xe00000) >> 21)
7497 case 0x4:
case 0x5:
case 0x6:
case 0x7:
7511 if (
bits (insn, 16, 19) == 0xf)
7541 unsigned int op2 =
bits (insn, 4, 6);
7542 unsigned int op =
bits (insn, 21, 22);
7593 switch (
bits (insn, 20, 24))
7601 case 0x12:
case 0x16:
7609 uint32_t op1 =
bits (insn, 20, 24), op2 =
bits (insn, 4, 7);
7611 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7613 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7615 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7617 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7619 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7621 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7623 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7638 int a =
bit (insn, 25), b =
bit (insn, 4);
7639 uint32_t op1 =
bits (insn, 20, 24);
7641 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7642 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7644 else if ((!a && (op1 & 0x17) == 0x02)
7645 || (a && (op1 & 0x17) == 0x02 && !b))
7647 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7648 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7650 else if ((!a && (op1 & 0x17) == 0x03)
7651 || (a && (op1 & 0x17) == 0x03 && !b))
7653 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7654 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7656 else if ((!a && (op1 & 0x17) == 0x06)
7657 || (a && (op1 & 0x17) == 0x06 && !b))
7659 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7660 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7662 else if ((!a && (op1 & 0x17) == 0x07)
7663 || (a && (op1 & 0x17) == 0x07 && !b))
7674 switch (
bits (insn, 20, 24))
7676 case 0x00:
case 0x01:
case 0x02:
case 0x03:
7679 case 0x04:
case 0x05:
case 0x06:
case 0x07:
7682 case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
7683 case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
7685 "decode/pack/unpack/saturate/reverse", dsc);
7688 if (
bits (insn, 5, 7) == 0)
7690 if (
bits (insn, 12, 15) == 0xf)
7698 case 0x1a:
case 0x1b:
7699 if (
bits (insn, 5, 6) == 0x2)
7704 case 0x1c:
case 0x1d:
7705 if (
bits (insn, 5, 6) == 0x0)
7707 if (
bits (insn, 0, 3) == 0xf)
7715 case 0x1e:
case 0x1f:
7716 if (
bits (insn, 5, 6) == 0x2)
7742 unsigned int opcode =
bits (insn, 20, 24);
7746 case 0x04:
case 0x05:
7749 case 0x08:
case 0x0a:
case 0x0c:
case 0x0e:
7750 case 0x12:
case 0x16:
7753 case 0x09:
case 0x0b:
case 0x0d:
case 0x0f:
7754 case 0x13:
case 0x17:
7757 case 0x10:
case 0x14:
case 0x18:
case 0x1c:
7758 case 0x11:
case 0x15:
case 0x19:
case 0x1d:
7772 uint16_t insn2,
struct regcache *regs,
7777 unsigned int op =
bits (insn1, 5, 8);
7778 unsigned int rn =
bits (insn1, 0, 3);
7780 if (op == 0x2 && rn == 0xf)
7784 "dp (shift reg)", dsc);
7793 uint16_t insn2,
struct regcache *regs,
7796 unsigned int opcode =
bits (insn1, 4, 8);
7800 case 0x04:
case 0x05:
7802 "vfp/neon vmov", dsc);
7804 case 0x08:
case 0x0c:
7805 case 0x0a:
case 0x0e:
7806 case 0x12:
case 0x16:
7808 "vfp/neon vstm/vpush", dsc);
7810 case 0x09:
case 0x0d:
7811 case 0x0b:
case 0x0f:
7812 case 0x13:
case 0x17:
7814 "vfp/neon vldm/vpop", dsc);
7816 case 0x10:
case 0x14:
case 0x18:
case 0x1c:
7819 case 0x11:
case 0x15:
case 0x19:
case 0x1d:
7831 unsigned int op1 =
bits (insn, 20, 25);
7832 int op =
bit (insn, 4);
7833 unsigned int coproc =
bits (insn, 8, 11);
7835 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7837 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7838 && (coproc & 0xe) != 0xa)
7841 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7842 && (coproc & 0xe) != 0xa)
7845 else if ((op1 & 0x3e) == 0x00)
7847 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7849 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7851 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7853 else if ((op1 & 0x30) == 0x20 && !op)
7855 if ((coproc & 0xe) == 0xa)
7860 else if ((op1 & 0x30) == 0x20 && op)
7862 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7864 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7866 else if ((op1 & 0x30) == 0x30)
7874 uint16_t insn2,
struct regcache *regs,
7877 unsigned int coproc =
bits (insn2, 8, 11);
7878 unsigned int bit_5_8 =
bits (insn1, 5, 8);
7879 unsigned int bit_9 =
bit (insn1, 9);
7880 unsigned int bit_4 =
bit (insn1, 4);
7886 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7888 else if (bit_5_8 == 0)
7893 if ((coproc & 0xe) == 0xa)
7934 int rd,
unsigned int imm)
7938 dsc->
modinsn[0] = (0x3000 | (rd << 8) | imm);
7950 unsigned int rd =
bits (insn, 8, 10);
7951 unsigned int imm8 =
bits (insn, 0, 7);
7961 uint16_t insn2,
struct regcache *regs,
7964 unsigned int rd =
bits (insn2, 8, 11);
7969 unsigned int imm_3_8 = insn2 & 0x70ff;
7970 unsigned int imm_i = insn1 & 0x0400;
7973 rd, imm_i, imm_3_8, insn1, insn2);
7978 dsc->
modinsn[0] = (0xf1a0 | rd | imm_i);
7979 dsc->
modinsn[1] = ((rd << 8) | imm_3_8);
7984 dsc->
modinsn[0] = (0xf100 | rd | imm_i);
7985 dsc->
modinsn[1] = ((rd << 8) | imm_3_8);
7999 unsigned int rt =
bits (insn1, 8, 10);
8001 int imm8 = (
bits (insn1, 0, 7) << 2);
8020 pc = pc & 0xfffffffc;
8046 int non_zero =
bit (insn1, 11);
8047 unsigned int imm5 = (
bit (insn1, 9) << 6) | (
bits (insn1, 3, 7) << 1);
8049 int rn =
bits (insn1, 0, 2);
8052 dsc->
u.
branch.
cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8068 non_zero ?
"cbnz" :
"cbz",
8080 uint16_t insn2,
struct regcache *regs,
8083 ULONGEST rn_val, rm_val;
8084 int is_tbh =
bit (insn2, 4);
8085 CORE_ADDR halfwords = 0;
8107 is_tbh ?
"tbh" :
"tbb",
8108 (
unsigned int) rn_val, (
unsigned int) rm_val,
8109 (
unsigned int) halfwords);
8173 dsc->
modinsn[0] = (insn1 & 0xfeff);
8182 unsigned int num_in_list = count_one_bits (dsc->
u.
block.
regmask);
8184 unsigned int new_regmask;
8186 for (i = 0; i < num_in_list + 1; i++)
8189 new_regmask = (1 << (num_in_list + 1)) - 1;
8192 "modified list %.4x",
8199 dsc->
modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8212 unsigned short op_bit_12_15 =
bits (insn1, 12, 15);
8213 unsigned short op_bit_10_11 =
bits (insn1, 10, 11);
8217 switch (op_bit_12_15)
8220 case 0:
case 1:
case 2:
case 3:
8222 "shift/add/sub/mov/cmp",
8226 switch (op_bit_10_11)
8235 unsigned short op =
bits (insn1, 7, 9);
8236 if (op == 6 || op == 7)
8238 else if (
bits (insn1, 6, 7) != 0)
8249 case 5:
case 6:
case 7:
case 8:
case 9:
8253 if (op_bit_10_11 < 2)
8260 switch (
bits (insn1, 8, 11))
8262 case 1:
case 3:
case 9:
case 11:
8272 if (
bits (insn1, 0, 3))
8287 if (op_bit_10_11 < 2)
8293 if (
bits (insn1, 9, 11) != 7)
8306 internal_error (_(
"thumb_process_displaced_16bit_insn: Instruction decode error"));
8311 uint16_t insn1, uint16_t insn2,
8315 int rt =
bits (insn2, 12, 15);
8316 int rn =
bits (insn1, 0, 3);
8317 int op1 =
bits (insn1, 7, 8);
8319 switch (
bits (insn1, 5, 6))
8338 "ldrb{reg, immediate}/ldrbt",
8346 "pld/unalloc memhint", dsc);
8359 int insn2_bit_8_11 =
bits (insn2, 8, 11);
8363 else if (op1 == 0x1)
8368 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8371 dsc,
bit (insn2, 8), 1);
8372 else if (insn2_bit_8_11 == 0xe)
8391 uint16_t insn2,
struct regcache *regs,
8395 unsigned short op =
bit (insn2, 15);
8396 unsigned int op1 =
bits (insn1, 11, 12);
8402 switch (
bits (insn1, 9, 10))
8408 if (
bits (insn1, 7, 8) == 1 &&
bits (insn1, 4, 5) == 1
8409 &&
bits (insn2, 5, 7) == 0)
8416 "load/store dual/ex", dsc);
8420 switch (
bits (insn1, 7, 8))
8449 || (
bits (insn1, 7, 9) != 0x7))
8459 int dp_op =
bits (insn1, 4, 8);
8460 int rn =
bits (insn1, 0, 3);
8461 if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf)
8474 switch (
bits (insn1, 9, 10))
8482 "neon elt/struct load/store",
8486 switch (
bits (insn1, 7, 8))
8494 "mul/mua/diff", dsc);
8512 internal_error (_(
"thumb_process_displaced_32bit_insn: Instruction decode error"));
8526 insn1, (
unsigned long) from);
8542 CORE_ADDR to,
struct regcache *regs,
8564 (
unsigned long) insn, (
unsigned long) from);
8566 if ((insn & 0xf0000000) == 0xf0000000)
8568 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8570 case 0x0:
case 0x1:
case 0x2:
case 0x3:
8574 case 0x4:
case 0x5:
case 0x6:
8582 case 0x8:
case 0x9:
case 0xa:
case 0xb:
8586 case 0xc:
case 0xd:
case 0xe:
case 0xf:
8592 internal_error (_(
"arm_process_displaced_insn: Instruction decode error"));
8603 unsigned int i, len, offset;
8606 const gdb_byte *bkp_insn;
8610 for (i = 0; i < dsc->
numinsns; i++)
8614 dsc->
modinsn[i], (
unsigned long) to + offset);
8617 (
unsigned short) dsc->
modinsn[i],
8618 (
unsigned long) to + offset);
8651 CORE_ADDR from, CORE_ADDR to,
8678 static asymbol *asym;
8679 static combined_entry_type ce;
8680 static struct coff_symbol_struct csym;
8681 static struct bfd fake_bfd;
8682 static bfd_target fake_target;
8684 if (csym.native == NULL)
8692 fake_target.flavour = bfd_target_coff_flavour;
8693 fake_bfd.xvec = &fake_target;
8694 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8696 csym.symbol.the_bfd = &fake_bfd;
8697 csym.symbol.name =
"fake";
8698 asym = (asymbol *) & csym;
8702 info->symbols = &asym;
8705 info->symbols = NULL;
8716 info->flags |= USER_SPECIFIED_MACHINE_TYPE;
8750#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8751#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8752#define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8753#define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8780 unsigned short inst1;
8797static const gdb_byte *
8814 gdb_assert_not_reached (
"unexpected arm breakpoint kind");
8844 for (CORE_ADDR pc : next_pcs)
8874 if (TYPE_CODE_FLT ==
type->
code ())
8876 switch (tdep->fp_model)
8903 internal_error (_(
"arm_extract_return_value: "
8904 "Floating point model not supported"));
8908 else if (
type->
code () == TYPE_CODE_INT
8948 memcpy (valbuf, tmpbuf,
8971 if (TYPE_CODE_STRUCT !=
code && TYPE_CODE_UNION !=
code
8972 && TYPE_CODE_ARRAY !=
code && TYPE_CODE_COMPLEX !=
code)
9024 if ((TYPE_CODE_STRUCT ==
code) || (TYPE_CODE_UNION ==
code))
9050 if (field_type_code == TYPE_CODE_FLT)
9080 const gdb_byte *valbuf)
9085 if (
type->
code () == TYPE_CODE_FLT)
9090 switch (tdep->fp_model)
9110 internal_error (_(
"arm_store_return_value: Floating "
9111 "point model not supported"));
9115 else if (
type->
code () == TYPE_CODE_INT
9120 ||
type->
code () == TYPE_CODE_ENUM)
9159 memcpy (tmpbuf, valbuf,
9174 gdb_byte *readbuf,
const gdb_byte *writebuf)
9187 for (i = 0; i < vfp_base_count; i++)
9189 if (reg_char ==
'q')
9193 writebuf + i * unit_length);
9197 readbuf + i * unit_length);
9204 xsnprintf (name_buf,
sizeof (name_buf),
"%c%d", reg_char, i);
9216 if (valtype->
code () == TYPE_CODE_STRUCT
9217 || valtype->
code () == TYPE_CODE_UNION
9218 || valtype->
code () == TYPE_CODE_ARRAY)
9248 else if (valtype->
code () == TYPE_CODE_COMPLEX)
9309 int target_len = strlen (
name) + strlen (
"__acle_se_") + 1;
9316 if (
minsym.minsym !=
nullptr)
9327 return (sec !=
nullptr
9341 CORE_ADDR start_addr;
9349 if (start_addr != 0)
9360 if (startswith (
name,
"_call_via_")
9361 || startswith (
name,
"__ARM_call_via_"))
9365 static const char *table[15] =
9366 {
"r0",
"r1",
"r2",
"r3",
"r4",
"r5",
"r6",
"r7",
9367 "r8",
"r9",
"sl",
"fp",
"ip",
"sp",
"lr"
9370 int offset = strlen (
name) - 2;
9372 for (regno = 0; regno <= 14; regno++)
9373 if (strcmp (&
name[offset], table[regno]) == 0)
9380 namelen = strlen (
name);
9381 if (
name[0] ==
'_' &&
name[1] ==
'_'
9382 && ((namelen > 2 + strlen (
"_from_thumb")
9383 && startswith (
name + namelen - strlen (
"_from_thumb"),
"_from_thumb"))
9384 || (namelen > 2 + strlen (
"_from_arm")
9385 && startswith (
name + namelen - strlen (
"_from_arm"),
"_from_arm"))))
9388 int target_len = namelen - 2;
9393 if (
name[namelen - 1] ==
'b')
9394 target_len -= strlen (
"_from_thumb");
9396 target_len -= strlen (
"_from_arm");
9405 if (minsym.
minsym != NULL)
9430 internal_error (_(
"could not update architecture"));
9447 internal_error (_(
"Invalid fp model accepted: %s."),
9464The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9469The current ARM floating point model is \"%s\".\n"),
9487 internal_error (_(
"Invalid ABI accepted: %s."),
9504The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9508 gdb_printf (file, _(
"The current ARM ABI is \"%s\".\n"),
9517 _(
"The current execution mode assumed "
9518 "(when symbols are unavailable) is \"%s\".\n"),
9527 _(
"The current execution mode assumed "
9528 "(even when symbols are available) is \"%s\".\n"),
9537 _(
"Usage of non-secure to secure exception stack unwinding is %s.\n"),
9562 const char *style =
"";
9566 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
9567 if (startswith (opt,
"reg-names-"))
9569 style = &opt[strlen (
"reg-names-")];
9570 len = strcspn (style,
",");
9573 gdb_printf (file,
"The disassembly style is \"%.*s\".\n", len, style);
9584 static const char *
const s_pseudo_names[] = {
9585 "s0",
"s1",
"s2",
"s3",
"s4",
"s5",
"s6",
"s7",
9586 "s8",
"s9",
"s10",
"s11",
"s12",
"s13",
"s14",
"s15",
9587 "s16",
"s17",
"s18",
"s19",
"s20",
"s21",
"s22",
"s23",
9588 "s24",
"s25",
"s26",
"s27",
"s28",
"s29",
"s30",
"s31",
9596 static const char *
const q_pseudo_names[] = {
9597 "q0",
"q1",
"q2",
"q3",
"q4",
"q5",
"q6",
"q7",
9598 "q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15",
9626 return (val == C_THUMBEXT
9627 || val == C_THUMBSTAT
9628 || val == C_THUMBEXTFUNC
9629 || val == C_THUMBSTATFUNC
9630 || val == C_THUMBLABEL);
9643 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
9645 if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal)
9646 == ST_BRANCH_TO_THUMB)
9661 const char *
name = bfd_asymbol_name (sym);
9665 gdb_assert (
name[0] ==
'$');
9666 if (
name[1] !=
'a' &&
name[1] !=
't' &&
name[1] !=
'd')
9674 = data->section_maps[bfd_asymbol_section (sym)->index];
9676 new_map_sym.
value = sym->value;
9680 map.push_back (new_map_sym);
9692 ULONGEST val, t_bit;
9711static enum register_status
9713 int regnum, gdb_byte *buf)
9716 gdb_byte reg_buf[8];
9717 int offset, double_regnum;
9718 enum register_status
status;
9720 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum << 1);
9733 memcpy (buf + offset, reg_buf, 8);
9735 offset = 8 - offset;
9739 memcpy (buf + offset, reg_buf, 8);
9747static enum register_status
9749 int regnum, gdb_byte *buf)
9757static enum register_status
9759 int regnum, gdb_byte *buf)
9763 gdb_byte reg_buf[8];
9764 int offset, double_regnum;
9767 gdb_assert (
regnum >= num_regs);
9779 enum register_status
status;
9783 gdb_assert (
regnum < 32);
9787 offset = (
regnum & 1) ? 0 : 4;
9789 offset = (
regnum & 1) ? 4 : 0;
9791 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum >> 1);
9797 memcpy (buf, reg_buf + offset, 4);
9811 int regnum,
const gdb_byte *buf)
9814 int offset, double_regnum;
9816 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum << 1);
9827 offset = 8 - offset;
9835 int regnum,
const gdb_byte *buf)
9845 int regnum,
const gdb_byte *buf)
9849 gdb_byte reg_buf[8];
9850 int offset, double_regnum;
9853 gdb_assert (
regnum >= num_regs);
9867 gdb_assert (
regnum < 32);
9871 offset = (
regnum & 1) ? 0 : 4;
9873 offset = (
regnum & 1) ? 4 : 0;
9875 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum >> 1);
9880 memcpy (reg_buf + offset, buf, 4);
9885static struct value *
9888 const int *reg_p = (
const int *) baton;
9895 unsigned int elfosabi;
9898 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9900 if (elfosabi == ELFOSABI_ARM)
10001 return "arm(v[^- ]*)?";
10033 bool have_sec_ext =
false;
10034 int vfp_register_count = 0;
10035 bool have_s_pseudos =
false, have_q_pseudos =
false;
10036 bool have_wmmx_registers =
false;
10037 bool have_neon =
false;
10038 bool have_fpa_registers =
true;
10039 const struct target_desc *tdesc = info.target_desc;
10040 bool have_vfp =
false;
10041 bool have_mve =
false;
10042 bool have_pacbti =
false;
10043 int mve_vpr_regnum = -1;
10045 bool have_m_profile_msp =
false;
10046 int m_profile_msp_regnum = -1;
10047 int m_profile_psp_regnum = -1;
10048 int m_profile_msp_ns_regnum = -1;
10049 int m_profile_psp_ns_regnum = -1;
10050 int m_profile_msp_s_regnum = -1;
10051 int m_profile_psp_s_regnum = -1;
10052 int tls_regnum = 0;
10059 int ei_osabi, e_flags;
10061 switch (bfd_get_flavour (info.abfd))
10063 case bfd_target_coff_flavour:
10069 case bfd_target_elf_flavour:
10070 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
10071 e_flags = elf_elfheader (info.abfd)->e_flags;
10073 if (ei_osabi == ELFOSABI_ARM)
10080 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
10082 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
10086 case EF_ARM_EABI_UNKNOWN:
10091 case EF_ARM_EABI_VER4:
10092 case EF_ARM_EABI_VER5:
10101 switch (bfd_elf_get_obj_attr_int (info.abfd,
10105 case AEABI_VFP_args_base:
10111 case AEABI_VFP_args_vfp:
10117 case AEABI_VFP_args_toolchain:
10123 case AEABI_VFP_args_compatible:
10144 warning (_(
"unknown ARM EABI version 0x%x"), eabi_ver);
10154 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10157 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10158 Tag_CPU_arch_profile);
10165 && (attr_arch == TAG_CPU_ARCH_V6_M
10166 || attr_arch == TAG_CPU_ARCH_V6S_M
10167 || attr_arch == TAG_CPU_ARCH_V7E_M
10168 || attr_arch == TAG_CPU_ARCH_V8M_BASE
10169 || attr_arch == TAG_CPU_ARCH_V8M_MAIN
10170 || attr_arch == TAG_CPU_ARCH_V8_1M_MAIN
10171 || attr_profile ==
'M'))
10178 int attr_pac_extension
10179 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10180 Tag_PAC_extension);
10182 int attr_bti_extension
10183 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10184 Tag_BTI_extension);
10186 int attr_pacret_use
10187 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10191 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10194 if (attr_pac_extension != 0 || attr_bti_extension != 0
10195 || attr_pacret_use != 0 || attr_bti_use != 0)
10196 have_pacbti =
true;
10203 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
10211 case EF_ARM_SOFT_FLOAT:
10214 case EF_ARM_VFP_FLOAT:
10217 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
10223 if (e_flags & EF_ARM_BE8)
10224 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10239 static const char *
const arm_sp_names[] = {
"r13",
"sp", NULL };
10240 static const char *
const arm_lr_names[] = {
"r14",
"lr", NULL };
10241 static const char *
const arm_pc_names[] = {
"r15",
"pc", NULL };
10243 const struct tdesc_feature *feature;
10247 "org.gnu.gdb.arm.core");
10248 if (feature == NULL)
10251 "org.gnu.gdb.arm.m-profile");
10252 if (feature == NULL)
10286 "org.gnu.gdb.arm.m-system");
10287 if (feature !=
nullptr)
10291 register_count,
"msp");
10294 warning (_(
"M-profile m-system feature is missing required register msp."));
10297 have_m_profile_msp =
true;
10298 m_profile_msp_regnum = register_count++;
10302 register_count,
"psp");
10305 warning (_(
"M-profile m-system feature is missing required register psp."));
10308 m_profile_psp_regnum = register_count++;
10313 "org.gnu.gdb.arm.fpa");
10314 if (feature != NULL)
10324 have_fpa_registers =
false;
10327 "org.gnu.gdb.xscale.iwmmxt");
10328 if (feature != NULL)
10330 static const char *
const iwmmxt_names[] = {
10331 "wR0",
"wR1",
"wR2",
"wR3",
"wR4",
"wR5",
"wR6",
"wR7",
10332 "wR8",
"wR9",
"wR10",
"wR11",
"wR12",
"wR13",
"wR14",
"wR15",
10333 "wCID",
"wCon",
"wCSSF",
"wCASF",
"",
"",
"",
"",
10334 "wCGR0",
"wCGR1",
"wCGR2",
"wCGR3",
"",
"",
"",
"",
10357 have_wmmx_registers =
true;
10364 "org.gnu.gdb.arm.vfp");
10365 if (feature != NULL)
10367 static const char *
const vfp_double_names[] = {
10368 "d0",
"d1",
"d2",
"d3",
"d4",
"d5",
"d6",
"d7",
10369 "d8",
"d9",
"d10",
"d11",
"d12",
"d13",
"d14",
"d15",
10370 "d16",
"d17",
"d18",
"d19",
"d20",
"d21",
"d22",
"d23",
10371 "d24",
"d25",
"d26",
"d27",
"d28",
"d29",
"d30",
"d31",
10377 for (i = 0; i < 32; i++)
10381 vfp_double_names[i]);
10385 if (!valid_p && i == 16)
10397 have_s_pseudos =
true;
10399 vfp_register_count = i;
10405 "org.gnu.gdb.arm.neon");
10406 if (feature != NULL)
10416 have_q_pseudos =
true;
10422 if (feature !=
nullptr)
10425 register_count,
"tpidruro");
10429 tls_regnum = register_count;
10440 if (feature !=
nullptr)
10444 register_count,
"vpr");
10447 warning (_(
"MVE feature is missing required register vpr."));
10452 mve_vpr_regnum = register_count;
10458 gdb_assert (!have_q_pseudos);
10464 have_q_pseudos =
true;
10469 "org.gnu.gdb.arm.m-profile-pacbti");
10470 if (feature !=
nullptr)
10480 have_pacbti =
true;
10485 "org.gnu.gdb.arm.secext");
10486 if (feature !=
nullptr)
10491 register_count,
"msp_ns");
10494 warning (_(
"M-profile secext feature is missing required register msp_ns."));
10497 m_profile_msp_ns_regnum = register_count++;
10501 register_count,
"psp_ns");
10504 warning (_(
"M-profile secext feature is missing required register psp_ns."));
10507 m_profile_psp_ns_regnum = register_count++;
10511 register_count,
"msp_s");
10514 warning (_(
"M-profile secext feature is missing required register msp_s."));
10517 m_profile_msp_s_regnum = register_count++;
10521 register_count,
"psp_s");
10524 warning (_(
"M-profile secext feature is missing required register psp_s."));
10527 m_profile_psp_s_regnum = register_count++;
10529 have_sec_ext =
true;
10541 = gdbarch_tdep<arm_gdbarch_tdep> (best_arch->
gdbarch);
10543 if (arm_abi !=
ARM_ABI_AUTO && arm_abi != tdep->arm_abi)
10555 if (is_m != tdep->
is_m)
10567 if (best_arch != NULL)
10575 tdep->arm_abi = arm_abi;
10576 tdep->fp_model = fp_model;
10581 gdb_assert (vfp_register_count == 0
10582 || vfp_register_count == 16
10583 || vfp_register_count == 32);
10601 if (have_m_profile_msp)
10614 switch (info.byte_order_for_code)
10616 case BFD_ENDIAN_BIG:
10624 case BFD_ENDIAN_LITTLE:
10633 internal_error (_(
"arm_gdbarch_init: bad byte order for float format"));
10760 if (tdep->
jb_pc >= 0)
10780 if (is_m && have_pacbti)
10796 int num_pseudos = 0;
10865 gdb_printf (file, _(
"arm_dump_tdep: fp_model = %i\n"),
10866 (
int) tdep->fp_model);
10867 gdb_printf (file, _(
"arm_dump_tdep: have_fpa_registers = %i\n"),
10869 gdb_printf (file, _(
"arm_dump_tdep: have_wmmx_registers = %i\n"),
10871 gdb_printf (file, _(
"arm_dump_tdep: vfp_register_count = %i\n"),
10873 gdb_printf (file, _(
"arm_dump_tdep: have_s_pseudos = %s\n"),
10875 gdb_printf (file, _(
"arm_dump_tdep: s_pseudo_base = %i\n"),
10877 gdb_printf (file, _(
"arm_dump_tdep: s_pseudo_count = %i\n"),
10879 gdb_printf (file, _(
"arm_dump_tdep: have_q_pseudos = %s\n"),
10881 gdb_printf (file, _(
"arm_dump_tdep: q_pseudo_base = %i\n"),
10883 gdb_printf (file, _(
"arm_dump_tdep: q_pseudo_count = %i\n"),
10885 gdb_printf (file, _(
"arm_dump_tdep: have_neon = %i\n"),
10887 gdb_printf (file, _(
"arm_dump_tdep: have_mve = %s\n"),
10889 gdb_printf (file, _(
"arm_dump_tdep: mve_vpr_regnum = %i\n"),
10891 gdb_printf (file, _(
"arm_dump_tdep: mve_pseudo_base = %i\n"),
10893 gdb_printf (file, _(
"arm_dump_tdep: mve_pseudo_count = %i\n"),
10895 gdb_printf (file, _(
"arm_dump_tdep: m_profile_msp_regnum = %i\n"),
10897 gdb_printf (file, _(
"arm_dump_tdep: m_profile_psp_regnum = %i\n"),
10899 gdb_printf (file, _(
"arm_dump_tdep: m_profile_msp_ns_regnum = %i\n"),
10901 gdb_printf (file, _(
"arm_dump_tdep: m_profile_psp_ns_regnum = %i\n"),
10903 gdb_printf (file, _(
"arm_dump_tdep: m_profile_msp_s_regnum = %i\n"),
10905 gdb_printf (file, _(
"arm_dump_tdep: m_profile_psp_s_regnum = %i\n"),
10907 gdb_printf (file, _(
"arm_dump_tdep: Lowest pc = 0x%lx\n"),
10909 gdb_printf (file, _(
"arm_dump_tdep: have_pacbti = %s\n"),
10911 gdb_printf (file, _(
"arm_dump_tdep: pacbti_pseudo_base = %i\n"),
10913 gdb_printf (file, _(
"arm_dump_tdep: pacbti_pseudo_count = %i\n"),
10915 gdb_printf (file, _(
"arm_dump_tdep: is_m = %s\n"),
10916 tdep->
is_m?
"yes" :
"no");
10922static void arm_record_test (
void);
10923static void arm_analyze_prologue_test ();
10933 char regdesc[1024], *rdptr = regdesc;
10934 size_t rest =
sizeof (regdesc);
10943 bfd_target_elf_flavour,
10948 _(
"Various ARM-specific commands."),
10949 _(
"Various ARM-specific commands."),
10954 const disasm_options_t *disasm_options
10955 = &disassembler_options_arm ()->options;
10956 int num_disassembly_styles = 0;
10957 for (i = 0; disasm_options->name[i] != NULL; i++)
10958 if (startswith (disasm_options->name[i],
"reg-names-"))
10959 num_disassembly_styles++;
10963 num_disassembly_styles + 1);
10964 for (i = j = 0; disasm_options->name[i] != NULL; i++)
10965 if (startswith (disasm_options->name[i],
"reg-names-"))
10967 size_t offset = strlen (
"reg-names-");
10968 const char *style = disasm_options->name[i];
10970 if (strcmp (&style[offset],
"std") == 0)
10972 length = snprintf (rdptr, rest,
"%s - %s\n", &style[offset],
10973 disasm_options->description[i]);
10981 std::string helptext = string_printf (
"%s%s%s",
10982 _(
"The valid values are:\n"),
10984 _(
"The default is \"std\"."));
10988 _(
"Set the disassembly style."),
10989 _(
"Show the disassembly style."),
10996 _(
"Set usage of ARM 32-bit mode."),
10997 _(
"Show usage of ARM 32-bit mode."),
10998 _(
"When off, a 26-bit PC will be used."),
11006 _(
"Set the floating point type."),
11007 _(
"Show the floating point type."),
11008 _(
"auto - Determine the FP typefrom the OS-ABI.\n\
11009softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
11010fpa - FPA co-processor (GCC compiled).\n\
11011softvfp - Software FP with pure-endian doubles.\n\
11012vfp - VFP co-processor."),
11019 _(
"Show the ABI."),
11027 _(
"Set the mode assumed when symbols are unavailable."),
11028 _(
"Show the mode assumed when symbols are unavailable."),
11033 _(
"Set the mode assumed even when symbols are available."),
11034 _(
"Show the mode assumed even when symbols are available."),
11041 _(
"Set usage of non-secure to secure exception stack unwinding."),
11042 _(
"Show usage of non-secure to secure exception stack unwinding."),
11043 _(
"When on, the debugger can trigger memory access traps."),
11049 _(
"Set ARM debugging."),
11050 _(
"Show ARM debugging."),
11051 _(
"When on, arm-specific debugging is enabled."),
11057 selftests::register_test (
"arm-record", selftests::arm_record_test);
11058 selftests::register_test (
"arm_analyze_prologue", selftests::arm_analyze_prologue_test);
11065#define ARM_INSN_SIZE_BYTES 4
11066#define THUMB_INSN_SIZE_BYTES 2
11067#define THUMB2_INSN_SIZE_BYTES 4
11072#define INSN_S_L_BIT_NUM 20
11074#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
11077 unsigned int reg_len = LENGTH; \
11080 REGS = XNEWVEC (uint32_t, reg_len); \
11081 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
11086#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
11089 unsigned int mem_len = LENGTH; \
11092 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
11093 memcpy(&MEMS->len, &RECORD_BUF[0], \
11094 sizeof(struct arm_mem_r) * LENGTH); \
11100#define INSN_RECORDED(ARM_RECORD) \
11101 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
11136 uint32_t ones =
bits (insn, bit_num - 1, (bit_num -1) + (
len - 1));
11181 ULONGEST u_regval[2]= {0};
11183 uint32_t reg_src1 = 0, reg_src2 = 0;
11184 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
11189 if (14 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
11200 u_regval[0] = u_regval[0] + 8;
11202 offset_8 = (immed_high << 4) | immed_low;
11204 if (14 == arm_insn_r->
opcode)
11206 tgt_mem_addr = u_regval[0] + offset_8;
11210 tgt_mem_addr = u_regval[0] - offset_8;
11214 record_buf_mem[0] = 2;
11215 record_buf_mem[1] = tgt_mem_addr;
11220 record_buf_mem[0] = 4;
11221 record_buf_mem[1] = tgt_mem_addr;
11222 record_buf_mem[2] = 4;
11223 record_buf_mem[3] = tgt_mem_addr + 4;
11227 else if (12 == arm_insn_r->
opcode || 8 == arm_insn_r->
opcode)
11236 if (15 == reg_src2)
11239 u_regval[0] = u_regval[0] + 8;
11242 if (12 == arm_insn_r->
opcode)
11244 tgt_mem_addr = u_regval[0] + u_regval[1];
11248 tgt_mem_addr = u_regval[1] - u_regval[0];
11252 record_buf_mem[0] = 2;
11253 record_buf_mem[1] = tgt_mem_addr;
11258 record_buf_mem[0] = 4;
11259 record_buf_mem[1] = tgt_mem_addr;
11260 record_buf_mem[2] = 4;
11261 record_buf_mem[3] = tgt_mem_addr + 4;
11265 else if (11 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
11266 || 2 == arm_insn_r->
opcode || 6 == arm_insn_r->
opcode)
11272 offset_8 = (immed_high << 4) | immed_low;
11276 if (15 == arm_insn_r->
opcode || 6 == arm_insn_r->
opcode)
11278 tgt_mem_addr = u_regval[0] + offset_8;
11282 tgt_mem_addr = u_regval[0] - offset_8;
11286 record_buf_mem[0] = 2;
11287 record_buf_mem[1] = tgt_mem_addr;
11292 record_buf_mem[0] = 4;
11293 record_buf_mem[1] = tgt_mem_addr;
11294 record_buf_mem[2] = 4;
11295 record_buf_mem[3] = tgt_mem_addr + 4;
11302 else if (9 == arm_insn_r->
opcode || 13 == arm_insn_r->
opcode
11303 || 0 == arm_insn_r->
opcode || 4 == arm_insn_r->
opcode)
11312 if (13 == arm_insn_r->
opcode || 4 == arm_insn_r->
opcode)
11314 tgt_mem_addr = u_regval[0] + u_regval[1];
11318 tgt_mem_addr = u_regval[1] - u_regval[0];
11322 record_buf_mem[0] = 2;
11323 record_buf_mem[1] = tgt_mem_addr;
11328 record_buf_mem[0] = 4;
11329 record_buf_mem[1] = tgt_mem_addr;
11330 record_buf_mem[2] = 4;
11331 record_buf_mem[3] = tgt_mem_addr + 4;
11347 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
11348 uint32_t record_buf[8], record_buf_mem[8];
11349 uint32_t reg_src1 = 0;
11351 ULONGEST u_regval = 0;
11358 if (arm_insn_r->
cond)
11362 if (5 == ((opcode1 & 0xE0) >> 5))
11374 if (3 == opcode1 &&
bit (arm_insn_r->
arm_insn, 4))
11386 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->
cond
11390 if (in_inclusive_range (insn_op1, 0U, 3U))
11396 else if (in_inclusive_range (insn_op1, 4U, 15U))
11412 if (!opcode1 && 2 == opcode2 && !
bit (arm_insn_r->
arm_insn, 20)
11419 if ((0 == insn_op1) || (2 == insn_op1))
11425 else if (1 == insn_op1)
11431 else if (3 == insn_op1)
11446 else if (3 == insn_op1)
11483 if (0 == insn_op1 || 1 == insn_op1)
11492 else if (2 == insn_op1)
11499 else if (3 == insn_op1)
11516 else if (3 == insn_op1)
11544 if (8 == arm_insn_r->
opcode)
11546 record_buf_mem[0] = 4;
11551 record_buf_mem[0] = 1;
11553 record_buf_mem[1] = u_regval;
11558 else if (1 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11564 else if (2 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11568 record_buf[1] = record_buf[0] + 1;
11571 else if (3 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11577 else if (
bit (arm_insn_r->
arm_insn, 20) && insn_op1 <= 3)
11587 if (24 == opcode1 &&
bit (arm_insn_r->
arm_insn, 21)
11610 uint32_t record_buf[8], record_buf_mem[8];
11611 ULONGEST u_regval[2] = {0};
11613 uint32_t reg_src1 = 0;
11614 uint32_t opcode1 = 0;
11620 if (!((opcode1 & 0x19) == 0x10))
11630 else if ((arm_insn_r->
decode < 8) && ((opcode1 & 0x19) == 0x10))
11634 if (3 == arm_insn_r->
decode && 0x12 == opcode1
11638 if (9 == arm_insn_r->
opcode)
11647 else if (7 == arm_insn_r->
decode && 0x12 == opcode1)
11663 else if (1 == arm_insn_r->
decode && 0x12 == opcode1
11671 else if (1 == arm_insn_r->
decode && 0x16 == opcode1
11680 && (8 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
11689 else if (9 == arm_insn_r->
decode && opcode1 < 0x10)
11695 if (0 == arm_insn_r->
opcode || 1 == arm_insn_r->
opcode)
11702 else if (4 <= arm_insn_r->
opcode && 7 >= arm_insn_r->
opcode)
11711 else if (9 == arm_insn_r->
decode && opcode1 > 0x10)
11722 if (8 == arm_insn_r->
opcode)
11724 record_buf_mem[0] = 4;
11729 record_buf_mem[0] = 1;
11731 record_buf_mem[1] = u_regval[0];
11736 else if (11 == arm_insn_r->
decode || 13 == arm_insn_r->
decode
11737 || 15 == arm_insn_r->
decode)
11739 if ((opcode1 & 0x12) == 2)
11750 if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4)
11756 else if ((opcode1 & 0x05) == 0x1)
11769 else if ((opcode1 & 0x05) == 0x5)
11791 if ((opcode1 & 0x05) == 0x0)
11795 record_buf[1] = record_buf[0] + 1;
11805 else if ((opcode1 & 0x05) == 0x1)
11818 else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5)
11841 if ((opcode1 & 0x05) == 0x0)
11847 else if ((opcode1 & 0x05) == 0x1)
11860 else if ((opcode1 & 0x05) == 0x4)
11866 else if ((opcode1 & 0x05) == 0x5)
11902 uint32_t record_buf[8], record_buf_mem[8];
11907 if ((9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode)
11913 if (9 == arm_insn_r->
opcode)
11924 else if (arm_insn_r->
opcode <= 15)
11946 uint32_t record_buf[8];
11969 unsigned int op1 =
bits (arm_insn_r->
arm_insn, 20, 22);
11974 else if (op1 == 0x4)
12032 uint32_t reg_base , reg_dest;
12033 uint32_t offset_12, tgt_mem_addr;
12034 uint32_t record_buf[8], record_buf_mem[8];
12035 unsigned char wback;
12076 tgt_mem_addr = (uint32_t) u_regval + offset_12;
12081 tgt_mem_addr = (uint32_t) u_regval - offset_12;
12089 record_buf_mem[0] = 1;
12094 record_buf_mem[0] = 4;
12099 record_buf_mem[1] = tgt_mem_addr;
12101 record_buf_mem[1] = (uint32_t) u_regval;
12123 uint32_t shift_imm = 0;
12124 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
12125 uint32_t offset_12 = 0, tgt_mem_addr = 0;
12126 uint32_t record_buf[8], record_buf_mem[8];
12129 ULONGEST u_regval[2];
12149 if (15 != reg_dest)
12156 record_buf[0] = reg_dest;
12175 if (15 == reg_src2)
12179 u_regval[0] = u_regval[0] + 8;
12185 tgt_mem_addr = u_regval[0] + u_regval[1];
12189 tgt_mem_addr = u_regval[1] - u_regval[0];
12192 switch (arm_insn_r->
opcode)
12206 record_buf_mem[0] = 4;
12221 record_buf_mem[0] = 1;
12225 gdb_assert_not_reached (
"no decoding pattern found");
12228 record_buf_mem[1] = tgt_mem_addr;
12231 if (9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode
12232 || 13 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
12241 record_buf[0] = reg_src2;
12263 offset_12 = u_regval[0] << shift_imm;
12267 offset_12 = (!shift_imm)?0:u_regval[0] >> shift_imm;
12273 if (
bit (u_regval[0], 31))
12275 offset_12 = 0xFFFFFFFF;
12285 offset_12 = s_word >> shift_imm;
12295 offset_12 = (((
bit (u_regval[1], 29)) << 31) \
12296 | (u_regval[0]) >> 1);
12300 offset_12 = (u_regval[0] >> shift_imm) \
12302 (
sizeof(uint32_t) - shift_imm));
12307 gdb_assert_not_reached (
"no decoding pattern found");
12315 tgt_mem_addr = u_regval[1] + offset_12;
12319 tgt_mem_addr = u_regval[1] - offset_12;
12322 switch (arm_insn_r->
opcode)
12336 record_buf_mem[0] = 4;
12351 record_buf_mem[0] = 1;
12355 gdb_assert_not_reached (
"no decoding pattern found");
12358 record_buf_mem[1] = tgt_mem_addr;
12361 if (9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode
12362 || 13 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
12371 record_buf[0] = reg_src2;
12388 uint32_t register_count = 0, register_bits;
12389 uint32_t reg_base, addr_mode;
12390 uint32_t record_buf[24], record_buf_mem[48];
12410 while (register_bits)
12412 if (register_bits & 0x00000001)
12414 register_bits = register_bits >> 1;
12436 while (register_bits)
12438 if (register_bits & 0x00000001)
12440 register_bits = register_bits >> 1;
12447 record_buf_mem[1] = (uint32_t) u_regval
12452 record_buf_mem[1] = (uint32_t) u_regval;
12456 record_buf_mem[1] = (uint32_t) u_regval
12464 gdb_assert_not_reached (
"no decoding pattern found");
12487 uint32_t record_buf[8];
12508 _(
"Process record does not support instruction "
12509 "0x%0x at address %s.\n"),arm_insn_r->
arm_insn,
12520 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
12521 uint32_t record_buf[4];
12530 if (bit_l && bit_c)
12532 record_buf[0] = reg_t;
12535 else if (bit_l && !bit_c)
12538 if (bits_a == 0x00)
12540 record_buf[0] = reg_t;
12544 else if (bits_a == 0x07)
12549 record_buf[0] = reg_t;
12553 else if (!bit_l && !bit_c)
12556 if (bits_a == 0x00)
12563 else if (bits_a == 0x07)
12569 else if (!bit_l && bit_c)
12572 if (!(bits_a & 0x04))
12574 record_buf[0] = (reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4))
12583 reg_v = reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4);
12590 reg_v = reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4);
12606 uint32_t opcode, single_reg;
12607 uint8_t op_vldm_vstm;
12608 uint32_t record_buf[8], record_buf_mem[128];
12609 ULONGEST u_regval = 0;
12615 op_vldm_vstm = opcode & 0x1b;
12618 if ((opcode & 0x1e) == 0x04)
12656 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
12657 || op_vldm_vstm == 0x12)
12659 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12660 uint32_t memory_index = 0;
12665 imm_off32 = imm_off8 << 2;
12666 memory_count = imm_off8;
12669 start_address = u_regval;
12671 start_address = u_regval - imm_off32;
12675 record_buf[0] = reg_rn;
12679 while (memory_count > 0)
12683 record_buf_mem[memory_index] = 4;
12684 record_buf_mem[memory_index + 1] = start_address;
12685 start_address = start_address + 4;
12686 memory_index = memory_index + 2;
12690 record_buf_mem[memory_index] = 4;
12691 record_buf_mem[memory_index + 1] = start_address;
12692 record_buf_mem[memory_index + 2] = 4;
12693 record_buf_mem[memory_index + 3] = start_address + 4;
12694 start_address = start_address + 8;
12695 memory_index = memory_index + 4;
12702 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
12703 || op_vldm_vstm == 0x13)
12705 uint32_t reg_count, reg_vd;
12706 uint32_t reg_index = 0;
12717 reg_vd = reg_vd | (bit_d << 4);
12720 record_buf[reg_index++] =
bits (arm_insn_r->
arm_insn, 16, 19);
12726 reg_count = reg_count / 2;
12727 if (single_reg && bit_d)
12734 while (reg_count > 0)
12736 record_buf[reg_index++] =
ARM_D0_REGNUM + reg_vd + reg_count - 1;
12742 else if ((opcode & 0x13) == 0x10)
12744 uint32_t start_address, reg_rn, imm_off32, imm_off8;
12745 uint32_t memory_index = 0;
12750 imm_off32 = imm_off8 << 2;
12753 start_address = u_regval + imm_off32;
12755 start_address = u_regval - imm_off32;
12759 record_buf_mem[memory_index] = 4;
12760 record_buf_mem[memory_index + 1] = start_address;
12765 record_buf_mem[memory_index] = 4;
12766 record_buf_mem[memory_index + 1] = start_address;
12767 record_buf_mem[memory_index + 2] = 4;
12768 record_buf_mem[memory_index + 3] = start_address + 4;
12773 else if ((opcode & 0x13) == 0x11)
12775 uint32_t reg_vd =
bits (arm_insn_r->
arm_insn, 12, 15);
12779 reg_vd = reg_vd | (
bit (arm_insn_r->
arm_insn, 22) << 4);
12784 reg_vd = (reg_vd << 1) |
bit (arm_insn_r->
arm_insn, 22);
12801 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12802 uint32_t record_buf[4];
12803 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
12804 enum insn_types curr_insn_type = INSN_INV;
12813 opc1 = opc1 & ~0x04;
12821 curr_insn_type = INSN_T0;
12823 curr_insn_type = INSN_T1;
12828 curr_insn_type = INSN_T1;
12830 curr_insn_type = INSN_T2;
12834 else if (opc1 == 0x01)
12837 curr_insn_type = INSN_T1;
12839 curr_insn_type = INSN_T2;
12842 else if (opc1 == 0x02 && !(opc3 & 0x01))
12847 curr_insn_type = INSN_T0;
12849 curr_insn_type = INSN_T1;
12854 curr_insn_type = INSN_T1;
12856 curr_insn_type = INSN_T2;
12860 else if (opc1 == 0x03)
12865 curr_insn_type = INSN_T0;
12867 curr_insn_type = INSN_T1;
12872 curr_insn_type = INSN_T1;
12874 curr_insn_type = INSN_T2;
12878 else if (opc1 == 0x08)
12881 curr_insn_type = INSN_T1;
12883 curr_insn_type = INSN_T2;
12886 else if (opc1 == 0x0b)
12889 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
12894 curr_insn_type = INSN_T0;
12896 curr_insn_type = INSN_T1;
12901 curr_insn_type = INSN_T1;
12903 curr_insn_type = INSN_T2;
12907 else if ((opc2 == 0x01 && opc3 == 0x01)
12908 || (opc2 == 0x00 && opc3 == 0x03))
12913 curr_insn_type = INSN_T0;
12915 curr_insn_type = INSN_T1;
12920 curr_insn_type = INSN_T1;
12922 curr_insn_type = INSN_T2;
12926 else if (opc2 == 0x01 && opc3 == 0x03)
12929 curr_insn_type = INSN_T1;
12931 curr_insn_type = INSN_T2;
12934 else if (opc2 == 0x07 && opc3 == 0x03)
12937 curr_insn_type = INSN_T1;
12939 curr_insn_type = INSN_T2;
12941 else if (opc3 & 0x01)
12944 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
12947 curr_insn_type = INSN_T2;
12951 curr_insn_type = INSN_T1;
12953 curr_insn_type = INSN_T2;
12957 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
12960 curr_insn_type = INSN_T1;
12962 curr_insn_type = INSN_T2;
12965 else if ((opc2 & 0x0e) == 0x02)
12966 curr_insn_type = INSN_T2;
12968 else if ((opc2 & 0x0e) == 0x04)
12969 curr_insn_type = INSN_T3;
12973 switch (curr_insn_type)
12976 reg_vd = reg_vd | (bit_d << 4);
12983 reg_vd = reg_vd | (bit_d << 4);
12989 reg_vd = (reg_vd << 1) | bit_d;
13000 gdb_assert_not_reached (
"no decoding pattern found");
13013 uint32_t op1, op1_ebit, coproc;
13019 if ((coproc & 0x0e) == 0x0a)
13026 if ((op1 & 0x3e) == 0x04)
13067 uint32_t op, op1_ebit, coproc, bits_24_25;
13069 = gdbarch_tdep<arm_gdbarch_tdep> (arm_insn_r->
gdbarch);
13079 if (bits_24_25 == 0x3)
13083 ULONGEST svc_operand, svc_number;
13085 svc_operand = (0x00ffffff & arm_insn_r->
arm_insn);
13088 svc_number = svc_operand - 0x900000;
13100 else if (bits_24_25 == 0x02)
13104 if ((coproc & 0x0e) == 0x0a)
13114 uint32_t record_buf[1];
13117 if (record_buf[0] == 15)
13134 if ((coproc & 0x0e) == 0x0a)
13148 unsigned int op1 =
bits (arm_insn_r->
arm_insn, 20, 25);
13152 if ((coproc & 0x0e) != 0x0a)
13158 else if (op1 == 4 || op1 == 5)
13160 if ((coproc & 0x0e) == 0x0a)
13171 else if (op1 == 0 || op1 == 1)
13178 if ((coproc & 0x0e) == 0x0a)
13198 uint32_t record_buf[8];
13199 uint32_t reg_src1 = 0;
13204 record_buf[1] = reg_src1;
13218 uint32_t record_buf[8];
13219 uint32_t reg_src1 = 0;
13224 record_buf[1] = reg_src1;
13238 uint32_t record_buf[8], record_buf_mem[8];
13240 uint32_t reg_src1 = 0, reg_src2 = 0;
13241 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
13243 ULONGEST u_regval[2] = {0};
13252 if (in_inclusive_range (opB, 4U, 7U))
13256 record_buf[0] = reg_src1;
13259 else if (in_inclusive_range (opB, 0U, 2U))
13267 record_buf_mem[0] = 4;
13269 record_buf_mem[0] = 1;
13271 record_buf_mem[0] = 2;
13272 record_buf_mem[1] = u_regval[0] + u_regval[1];
13281 record_buf[0] = reg_src1;
13289 if ((3 == opcode2) && (!opcode3))
13299 record_buf[1] = (
bit (thumb_insn_r->
arm_insn, 7) << 3
13310 reg_src1 = reg_src1 + 8;
13313 record_buf[1] = reg_src1;
13330 uint32_t record_buf[8], record_buf_mem[8];
13332 uint32_t reg_src1 = 0;
13333 uint32_t opcode = 0, immed_5 = 0;
13335 ULONGEST u_regval = 0;
13343 record_buf[0] = reg_src1;
13352 record_buf_mem[0] = 4;
13353 record_buf_mem[1] = u_regval + (immed_5 * 4);
13370 uint32_t record_buf[8], record_buf_mem[8];
13372 uint32_t reg_src1 = 0;
13373 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
13375 ULONGEST u_regval = 0;
13383 record_buf[0] = reg_src1;
13386 else if (1 == opcode)
13390 record_buf[0] = reg_src1;
13393 else if (2 == opcode)
13398 record_buf_mem[0] = 4;
13399 record_buf_mem[1] = u_regval + (immed_8 * 4);
13402 else if (0 == opcode)
13408 record_buf_mem[0] = 2;
13409 record_buf_mem[1] = u_regval + (immed_5 * 2);
13427 uint32_t opcode = 0;
13428 uint32_t register_bits = 0, register_count = 0;
13429 uint32_t index = 0, start_address = 0;
13430 uint32_t record_buf[24], record_buf_mem[48];
13433 ULONGEST u_regval = 0;
13437 if (opcode == 0 || opcode == 1)
13442 record_buf[0] = reg_src1;
13448 uint32_t opcode2 =
bits (thumb_insn_r->
arm_insn, 8, 11);
13477 while (register_bits)
13479 if (register_bits & 0x00000001)
13481 register_bits = register_bits >> 1;
13483 start_address = u_regval - \
13484 (4 * (
bit (thumb_insn_r->
arm_insn, 8) + register_count));
13486 while (register_count)
13488 record_buf_mem[(register_count * 2) - 1] = start_address;
13489 record_buf_mem[(register_count * 2) - 2] = 4;
13490 start_address = start_address + 4;
13505 while (register_bits)
13507 if (register_bits & 0x00000001)
13508 record_buf[index++] = register_count;
13509 register_bits = register_bits >> 1;
13529 _(
"Process record does not support instruction "
13530 "0x%0x at address %s.\n"),
13557 = gdbarch_tdep<arm_gdbarch_tdep> (thumb_insn_r->
gdbarch);
13561 uint32_t reg_src1 = 0;
13562 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
13563 uint32_t index = 0, start_address = 0;
13564 uint32_t record_buf[24], record_buf_mem[48];
13566 ULONGEST u_regval = 0;
13578 while (register_bits)
13580 if (register_bits & 0x00000001)
13581 record_buf[index++] = register_count;
13582 register_bits = register_bits >> 1;
13585 record_buf[index++] = reg_src1;
13588 else if (0 == opcode2)
13595 while (register_bits)
13597 if (register_bits & 0x00000001)
13599 register_bits = register_bits >> 1;
13601 start_address = u_regval;
13603 while (register_count)
13605 record_buf_mem[(register_count * 2) - 1] = start_address;
13606 record_buf_mem[(register_count * 2) - 2] = 4;
13607 start_address = start_address + 4;
13611 else if (0x1F == opcode1)
13641 uint32_t record_buf[8];
13642 uint32_t bits_h = 0;
13646 if (2 == bits_h || 3 == bits_h)
13652 else if (1 == bits_h)
13675 uint32_t reg_rn, op;
13676 uint32_t register_bits = 0, register_count = 0;
13677 uint32_t index = 0, start_address = 0;
13678 uint32_t record_buf[24], record_buf_mem[48];
13680 ULONGEST u_regval = 0;
13685 if (0 == op || 3 == op)
13699 else if (1 == op || 2 == op)
13704 register_bits =
bits (thumb2_insn_r->
arm_insn, 0, 15);
13705 while (register_bits)
13707 if (register_bits & 0x00000001)
13708 record_buf[index++] = register_count;
13711 register_bits = register_bits >> 1;
13713 record_buf[index++] = reg_rn;
13720 register_bits =
bits (thumb2_insn_r->
arm_insn, 0, 15);
13722 while (register_bits)
13724 if (register_bits & 0x00000001)
13727 register_bits = register_bits >> 1;
13733 start_address = u_regval;
13738 start_address = u_regval - register_count * 4;
13742 while (register_count)
13744 record_buf_mem[register_count * 2 - 1] = start_address;
13745 record_buf_mem[register_count * 2 - 2] = 4;
13746 start_address = start_address + 4;
13749 record_buf[0] = reg_rn;
13770 uint32_t reg_rd, reg_rn, offset_imm;
13771 uint32_t reg_dest1, reg_dest2;
13772 uint32_t address, offset_addr;
13773 uint32_t record_buf[8], record_buf_mem[8];
13774 uint32_t op1, op2, op3;
13776 ULONGEST u_regval[2];
13784 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
13787 record_buf[0] = reg_dest1;
13792 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
13795 record_buf[2] = reg_dest2;
13804 if (0 == op1 && 0 == op2)
13808 address = u_regval[0] + (offset_imm * 4);
13809 record_buf_mem[0] = 4;
13810 record_buf_mem[1] = address;
13813 record_buf[0] = reg_rd;
13816 else if (1 == op1 && 0 == op2)
13819 record_buf[0] = reg_rd;
13821 address = u_regval[0];
13822 record_buf_mem[1] = address;
13827 record_buf_mem[0] = 1;
13833 record_buf_mem[0] = 2 ;
13839 address = u_regval[0];
13840 record_buf_mem[0] = 4;
13841 record_buf_mem[2] = 4;
13842 record_buf_mem[3] = address + 4;
13853 offset_addr = u_regval[0] + (offset_imm * 4);
13855 offset_addr = u_regval[0] - (offset_imm * 4);
13857 address = offset_addr;
13860 address = u_regval[0];
13862 record_buf_mem[0] = 4;
13863 record_buf_mem[1] = address;
13864 record_buf_mem[2] = 4;
13865 record_buf_mem[3] = address + 4;
13867 record_buf[0] = reg_rn;
13885 uint32_t reg_rd, op;
13886 uint32_t record_buf[8];
13891 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
13898 record_buf[0] = reg_rd;
13915 uint32_t record_buf[8];
13919 record_buf[0] = reg_rd;
13933 uint32_t op, op1, op2;
13934 uint32_t record_buf[8];
13941 if (!(op1 & 0x2) && 0x38 == op)
13955 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
13975 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
13976 uint32_t address, offset_addr;
13977 uint32_t record_buf[8], record_buf_mem[8];
13980 ULONGEST u_regval[2];
13991 offset_addr = u_regval[0] + offset_imm;
13992 address = offset_addr;
13997 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
14003 offset_addr = u_regval[1] << shift_imm;
14004 address = u_regval[0] + offset_addr;
14012 offset_addr = u_regval[0] + offset_imm;
14014 offset_addr = u_regval[0] - offset_imm;
14016 address = offset_addr;
14019 address = u_regval[0];
14028 record_buf_mem[0] = 1;
14033 record_buf_mem[0] = 2;
14038 record_buf_mem[0] = 4;
14042 gdb_assert_not_reached (
"no decoding pattern found");
14046 record_buf_mem[1] = address;
14048 record_buf[0] = reg_rn;
14063 uint32_t record_buf[8];
14064 uint32_t reg_rt, reg_rn;
14071 record_buf[0] = reg_rt;
14072 record_buf[1] = reg_rn;
14089 uint32_t record_buf[8];
14091 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
14106 uint32_t opcode1 = 0, opcode2 = 0;
14107 uint32_t record_buf[8];
14112 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
14116 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 16, 19);
14117 record_buf[1] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
14121 else if (1 == opcode1 || 3 == opcode2)
14124 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 16, 19);
14125 record_buf[1] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
14154 uint32_t l_bit, a_bit, b_bits;
14155 uint32_t record_buf[128], record_buf_mem[128];
14156 uint32_t reg_rn, reg_vd, address, f_elem;
14157 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
14165 reg_vd = (
bit (thumb2_insn_r->
arm_insn, 22) << 4) | reg_vd;
14166 f_ebytes = (1 <<
bits (thumb2_insn_r->
arm_insn, 6, 7));
14167 f_elem = 8 / f_ebytes;
14171 ULONGEST u_regval = 0;
14173 address = u_regval;
14178 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
14180 if (b_bits == 0x07)
14182 else if (b_bits == 0x0a)
14184 else if (b_bits == 0x06)
14186 else if (b_bits == 0x02)
14191 for (index_r = 0; index_r < bf_regs; index_r++)
14193 for (index_e = 0; index_e < f_elem; index_e++)
14195 record_buf_mem[index_m++] = f_ebytes;
14196 record_buf_mem[index_m++] = address;
14197 address = address + f_ebytes;
14203 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
14205 if (b_bits == 0x09 || b_bits == 0x08)
14207 else if (b_bits == 0x03)
14212 for (index_r = 0; index_r < bf_regs; index_r++)
14213 for (index_e = 0; index_e < f_elem; index_e++)
14215 for (loop_t = 0; loop_t < 2; loop_t++)
14217 record_buf_mem[index_m++] = f_ebytes;
14218 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
14221 address = address + (2 * f_ebytes);
14225 else if ((b_bits & 0x0e) == 0x04)
14227 for (index_e = 0; index_e < f_elem; index_e++)
14229 for (loop_t = 0; loop_t < 3; loop_t++)
14231 record_buf_mem[index_m++] = f_ebytes;
14232 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
14235 address = address + (3 * f_ebytes);
14239 else if (!(b_bits & 0x0e))
14241 for (index_e = 0; index_e < f_elem; index_e++)
14243 for (loop_t = 0; loop_t < 4; loop_t++)
14245 record_buf_mem[index_m++] = f_ebytes;
14246 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
14249 address = address + (4 * f_ebytes);
14255 uint8_t bft_size =
bits (thumb2_insn_r->
arm_insn, 10, 11);
14257 if (bft_size == 0x00)
14259 else if (bft_size == 0x01)
14261 else if (bft_size == 0x02)
14267 if (!(b_bits & 0x0b) || b_bits == 0x08)
14270 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
14273 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
14276 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
14279 for (index_m = 0; index_m < thumb2_insn_r->
mem_rec_count; index_m++)
14281 record_buf_mem[index_m] = f_ebytes;
14282 record_buf_mem[index_m] = address + (index_m * f_ebytes);
14291 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
14294 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
14297 else if ((b_bits & 0x0e) == 0x04)
14300 else if (!(b_bits & 0x0e))
14306 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
14309 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
14312 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
14315 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
14318 for (index_r = 0; index_r < thumb2_insn_r->
reg_rec_count; index_r++)
14325 record_buf[index_r] = reg_rn;
14341 uint32_t op, op1, op2;
14349 if (!(op2 & 0x64 ))
14354 else if ((op2 & 0x64) == 0x4)
14359 else if ((op2 & 0x60) == 0x20)
14364 else if (op2 & 0x40)
14370 else if (op1 == 0x02)
14377 else if (op2 & 0x20)
14388 else if (op1 == 0x03)
14390 if (!(op2 & 0x71 ))
14395 else if (!((op2 & 0x71) ^ 0x10))
14400 else if (!((op2 & 0x67) ^ 0x01))
14405 else if (!((op2 & 0x67) ^ 0x03))
14410 else if (!((op2 & 0x67) ^ 0x05))
14415 else if (!((op2 & 0x70) ^ 0x20))
14420 else if (!((op2 & 0x78) ^ 0x30))
14425 else if (!((op2 & 0x78) ^ 0x38))
14430 else if (op2 & 0x40)
14443class abstract_instruction_reader
14449 virtual ULONGEST
read (CORE_ADDR memaddr,
const size_t len,
14450 enum bfd_endian byte_order) = 0;
14455class instruction_reader :
public abstract_instruction_reader
14458 ULONGEST
read (CORE_ADDR memaddr,
const size_t len,
14459 enum bfd_endian byte_order)
override
14507 uint32_t insn_id = 0;
14508 enum bfd_endian code_endian
14511 = reader.read (arm_record->
this_addr, insn_size, code_endian);
14518 if (arm_record->
cond == 0xf)
14524 ret = arm_handle_insn[insn_id] (arm_record);
14535 arm_record->
cond = -1;
14537 ret = thumb_handle_insn[insn_id] (arm_record);
14547 arm_record->
cond = -1;
14564 gdb_assert_not_reached (
"not a valid instruction, could not decode");
14580template<
typename T>
14581class instruction_reader_selftest :
public abstract_instruction_reader
14584 template<
size_t SIZE>
14585 instruction_reader_selftest (
const T (&insns)[
SIZE])
14586 : m_insns (insns), m_insns_size (
SIZE)
14589 ULONGEST
read (CORE_ADDR memaddr,
const size_t length,
14590 enum bfd_endian byte_order)
override
14592 SELF_CHECK (length ==
sizeof (
T));
14593 SELF_CHECK (memaddr %
sizeof (
T) == 0);
14594 SELF_CHECK ((memaddr /
sizeof (
T)) < m_insns_size);
14596 return m_insns[memaddr /
sizeof (
T)];
14601 const size_t m_insns_size;
14605arm_record_test (
void)
14608 info.bfd_arch_info = bfd_scan_arch (
"arm");
14612 SELF_CHECK (
gdbarch != NULL);
14623 static const uint16_t insns[] = {
14630 instruction_reader_selftest<uint16_t> reader (insns);
14634 SELF_CHECK (ret == 0);
14637 SELF_CHECK (arm_record.
arm_regs[0] == 3);
14643 SELF_CHECK (ret == 0);
14646 SELF_CHECK (arm_record.
arm_regs[0] == 5);
14658 static const uint32_t insns[] = {
14663 instruction_reader_selftest<uint32_t> reader (insns);
14667 SELF_CHECK (ret == 0);
14670 SELF_CHECK (arm_record.
arm_regs[0] == 7);
14682 static const uint32_t insns[] = {
14687 instruction_reader_selftest<uint32_t> reader (insns);
14691 SELF_CHECK (ret == 0);
14697class test_arm_instruction_reader :
public arm_instruction_reader
14700 explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns)
14704 uint32_t
read (CORE_ADDR memaddr,
enum bfd_endian byte_order)
const override
14706 SELF_CHECK (memaddr % 4 == 0);
14707 SELF_CHECK (memaddr / 4 < m_insns.size ());
14709 return m_insns[memaddr / 4];
14713 const gdb::array_view<const uint32_t> m_insns;
14717arm_analyze_prologue_test ()
14719 for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG})
14722 info.byte_order = endianness;
14723 info.byte_order_for_code = endianness;
14724 info.bfd_arch_info = bfd_scan_arch (
"arm");
14728 SELF_CHECK (
gdbarch != NULL);
14733 const uint32_t insns[] = {
14740 test_arm_instruction_reader mem_reader (insns);
14756 xfree (record->arm_regs);
14757 xfree (record->arm_mems);
14767 CORE_ADDR insn_addr)
14770 uint32_t no_of_rec = 0;
14772 ULONGEST t_bit = 0, insn_id = 0;
14774 ULONGEST u_regval = 0;
14791 instruction_reader reader;
14792 enum bfd_endian code_endian
14795 = reader.read (arm_record.
this_addr, 2, code_endian);
14803 if (!(u_regval & t_bit))
14812 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
14831 for (no_of_rec = 0; no_of_rec < arm_record.
reg_rec_count; no_of_rec++)
14841 for (no_of_rec = 0; no_of_rec < arm_record.
mem_rec_count; no_of_rec++)
14867 if (tdesc ==
nullptr)
14883 if (tdesc ==
nullptr)
#define IS_BTI(instruction)
#define sbits(obj, st, fn)
#define bits(obj, st, fn)
int default_print_insn(bfd_vma memaddr, disassemble_info *info)
int gdbarch_update_p(struct gdbarch_info info)
struct gdbarch * get_current_arch(void)
struct gdbarch * target_gdbarch(void)
static std::vector< const char * > arches
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
struct gdbarch * gdbarch_find_by_info(struct gdbarch_info info)
void arm_get_next_pcs_ctor(struct arm_get_next_pcs *self, struct arm_get_next_pcs_ops *ops, int byte_order, int byte_order_for_code, int has_thumb2_breakpoint, struct regcache *regcache)
static int thumb_copy_bx_blx_reg(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_ld_mem_hints(arm_insn_decode_record *thumb2_insn_r)
static void install_alu_shifted_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rd, unsigned int rn, unsigned int rm, unsigned rs)
static int arm_return_in_memory(struct gdbarch *gdbarch, struct type *type)
static int decode_thumb_32bit_ld_mem_hints(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_register_sim_regno(struct gdbarch *gdbarch, int regnum)
static void bx_write_pc(struct regcache *regs, ULONGEST val)
static void thumb_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_neon_quad_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
int arm_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR insn_addr)
static CORE_ADDR arm_cache_get_prev_sp_value(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep)
static int thumb_copy_unmodified_32bit(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, const char *iname, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_decode_svc_copro(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static gdb_byte * extend_buffer_earlier(gdb_byte *buf, CORE_ADDR endaddr, int old_len, int new_len)
static int arm_exidx_unwind_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static int thumb_copy_pc_relative_16bit(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int rd, unsigned int imm)
static struct value * arm_prologue_prev_register(frame_info_ptr this_frame, void **this_cache, int prev_regnum)
static int install_svc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_copy_load_literal(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int size)
ULONGEST arm_get_next_pcs_read_memory_unsigned_integer(CORE_ADDR memaddr, int len, int byte_order)
static void arm_show_unwind_secure_frames(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static void install_preload(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rn)
static bool arm_is_sgstubs_section(struct obj_section *sec)
static struct cmd_list_element * showarmcmdlist
static int arm_copy_preload(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int sbo_sbz(uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
static int thumb2_record_ps_dest_generic(arm_insn_decode_record *thumb2_insn_r)
static void arm_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, frame_info_ptr this_frame)
static struct arm_prologue_cache * arm_make_epilogue_frame_cache(frame_info_ptr this_frame)
static int arm_vfp_cprc_sub_candidate(struct type *t, enum arm_vfp_cprc_base_type *base_type)
static enum arm_float_model arm_fp_model
static int thumb_32bit_copy_undef(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, arm_displaced_step_copy_insn_closure *dsc)
static void print_fpu_flags(struct ui_file *file, int flags)
static int thumb2_copy_table_branch(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_copy_b(struct gdbarch *gdbarch, uint16_t insn, arm_displaced_step_copy_insn_closure *dsc)
static void thumb_process_displaced_32bit_insn(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_alu_imm(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define REG_ALLOC(REGS, LENGTH, RECORD_BUF)
void arm_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_svc(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_coproc_insn(arm_insn_decode_record *thumb2_insn_r)
static CORE_ADDR arm_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
#define MAX_IT_BLOCK_PREFIX
static void cleanup_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_get_next_pcs_syscall_next_pc(struct arm_get_next_pcs *self)
static ULONGEST arm_type_align(gdbarch *gdbarch, struct type *t)
static int arm_record_asimd_vfp_coproc(arm_insn_decode_record *arm_insn_r)
static gdb_byte * arm_find_exidx_entry(CORE_ADDR memaddr, CORE_ADDR *start)
static struct target_desc * tdesc_arm_list[ARM_FP_TYPE_INVALID][2]
struct frame_unwind arm_m_exception_unwind
static void thumb_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR prev_pc, CORE_ADDR block_addr, struct arm_prologue_cache *cache)
static int arm_record_ld_st_multiple(arm_insn_decode_record *arm_insn_r)
static int arm_breakpoint_kind_from_current_state(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR *pcptr)
static int thumb_record_ld_st_reg_offset(arm_insn_decode_record *thumb_insn_r)
static void arm_store_return_value(struct type *type, struct regcache *regs, const gdb_byte *valbuf)
static const unsigned char op_lit0
static int arm_copy_undef(struct gdbarch *gdbarch, uint32_t insn, arm_displaced_step_copy_insn_closure *dsc)
static int arm_record_ld_st_imm_offset(arm_insn_decode_record *arm_insn_r)
static const char *const fp_model_strings[]
static enum unwind_stop_reason arm_prologue_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
static unsigned int thumb2_record_decode_insn_handler(arm_insn_decode_record *thumb2_insn_r)
static CORE_ADDR thumb_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR limit, struct arm_prologue_cache *cache)
static int arm_copy_extra_ld_st(struct gdbarch *gdbarch, uint32_t insn, int unprivileged, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void set_disassembly_style_sfunc(const char *, int, struct cmd_list_element *)
ULONGEST displaced_read_reg(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int regno)
static int arm_record_vdata_transfer_insn(arm_insn_decode_record *arm_insn_r)
static int arm_record_extension_space(arm_insn_decode_record *arm_insn_r)
static int gdb_print_insn_arm(bfd_vma memaddr, disassemble_info *info)
static void branch_write_pc(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, ULONGEST val)
static const char * arm_force_mode_string
static int thumb2_record_str_single_data(arm_insn_decode_record *thumb2_insn_r)
static int arm_decode_unconditional(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_record_ldm_stm_swi(arm_insn_decode_record *thumb_insn_r)
static int arm_record_b_bl(arm_insn_decode_record *arm_insn_r)
static void arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
#define arm_debug_printf(fmt,...)
static char * arm_disassembler_options
static ULONGEST reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr)
static int thumb2_record_lmul_lmla_div(arm_insn_decode_record *thumb2_insn_r)
static int thumb_copy_pop_pc_16bit(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_record_branch(arm_insn_decode_record *thumb_insn_r)
#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF)
static const gdb_byte arm_default_thumb_le_breakpoint[]
static void arm_pseudo_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
#define ARM_INSN_SIZE_BYTES
static struct type * arm_neon_double_type(struct gdbarch *gdbarch)
static void arm_register_g_packet_guesses(struct gdbarch *gdbarch)
static enum arm_abi_kind arm_abi_global
static const gdb_byte arm_default_arm_be_breakpoint[]
static char arm_find_mapping_symbol(CORE_ADDR memaddr, CORE_ADDR *start)
static const char *const arm_register_names[]
static uint32_t arm_expand_immediate(uint32_t imm)
int arm_is_thumb(struct regcache *regcache)
static const char * arm_gnu_triplet_regexp(struct gdbarch *gdbarch)
static int arm_decode_ext_reg_ld_st(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static struct value * arm_dwarf2_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static int arm_decode_ld_st_word_ubyte(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_prologue_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static int skip_prologue_function(struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
static int coff_sym_is_thumb(int val)
static enum register_status arm_pseudo_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
static CORE_ADDR arm_normal_frame_base(frame_info_ptr this_frame, void **this_cache)
static CORE_ADDR arm_skip_cmse_entry(CORE_ADDR pc, const char *name, struct objfile *objfile)
static int arm_copy_copro_load_store(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_block_xfer(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static bool arm_is_alternative_sp_register(arm_gdbarch_tdep *tdep, int regnum)
static int arm_vfp_call_candidate(struct type *t, enum arm_vfp_cprc_base_type *base_type, int *count)
static void cleanup_alu_shifted_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_cache_init(struct arm_prologue_cache *cache, struct gdbarch *gdbarch)
static struct cmd_list_element * setarmcmdlist
static struct target_desc * tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]
static int arm_copy_unmodified(struct gdbarch *gdbarch, uint32_t insn, const char *iname, arm_displaced_step_copy_insn_closure *dsc)
static const struct @6 arm_register_aliases[]
static struct obj_section * arm_obj_section_from_vma(struct objfile *objfile, bfd_vma vma)
static struct type * arm_neon_quad_type(struct gdbarch *gdbarch)
static int thumb2_record_asimd_struct_ld_st(arm_insn_decode_record *thumb2_insn_r)
static int arm_decode_misc_memhint_neon(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
bool arm_unwind_secure_frames
static CORE_ADDR arm_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
static void cleanup_alu_reg(struct gdbarch *gdbarch, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static bool is_pacbti_pseudo(struct gdbarch *gdbarch, int regnum)
void arm_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_copy_insn_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
#define INSN_RECORDED(ARM_RECORD)
static frame_unwind arm_prologue_unwind
static void cleanup_block_load_pc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
int arm_frame_is_thumb(frame_info_ptr frame)
static int thumb2_record_ld_word(arm_insn_decode_record *thumb2_insn_r)
static int thumb_record_ld_st_stack(arm_insn_decode_record *thumb_insn_r)
static void install_alu_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rd, unsigned int rn, unsigned int rm)
static bool is_mve_pseudo(struct gdbarch *gdbarch, int regnum)
static const char * arm_register_name(struct gdbarch *gdbarch, int i)
static struct value * arm_m_exception_prev_register(frame_info_ptr this_frame, void **this_cache, int prev_regnum)
static int arm_vfp_cprc_reg_char(enum arm_vfp_cprc_base_type b)
static int arm_record_unsupported_insn(arm_insn_decode_record *arm_insn_r)
static void cleanup_branch(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_preload_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_branch_misc_cntrl(arm_insn_decode_record *thumb2_insn_r)
static int arm_record_vfp_data_proc_insn(arm_insn_decode_record *arm_insn_r)
static int thumb_copy_16bit_ldr_literal(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
static void arm_show_fallback_mode(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static int thumb_copy_svc(struct gdbarch *gdbarch, uint16_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2)
static int decode_insn(abstract_instruction_reader &reader, arm_insn_decode_record *arm_record, record_type_t record_type, uint32_t insn_size)
static CORE_ADDR arm_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader)
static void arm_show_abi(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static const char * current_fp_model
static void deallocate_reg_mem(arm_insn_decode_record *record)
static const gdb_byte arm_default_arm_le_breakpoint[]
static void arm_exidx_new_objfile(struct objfile *objfile)
#define EXTRACT_MOVW_MOVT_IMM_A(insn)
static const char *const arm_abi_strings[]
struct frame_unwind arm_exidx_unwind
static CORE_ADDR arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
std::vector< arm_mapping_symbol > arm_mapping_symbol_vec
static void arm_update_current_architecture(void)
static struct arm_stack_item * push_stack_item(struct arm_stack_item *prev, const gdb_byte *contents, int len)
static int thumb_copy_unmodified_16bit(struct gdbarch *gdbarch, uint16_t insn, const char *iname, arm_displaced_step_copy_insn_closure *dsc)
static void install_copro_load_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int writeback, unsigned int rn)
static int arm_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
#define THUMB_INSN_SIZE_BYTES
static int arm_record_ld_st_reg_offset(arm_insn_decode_record *arm_insn_r)
static void cleanup_preload(struct gdbarch *gdbarch, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_copy_pc_relative_32bit(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void cleanup_copro_load_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static bool is_s_pseudo(struct gdbarch *gdbarch, int regnum)
static int thumb2_decode_dp_shift_reg(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define MSYMBOL_SET_SPECIAL(msym)
static void install_load_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int load, int immed, int writeback, int size, int usermode, int rt, int rm, int rn)
static void cleanup_block_store_pc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
int arm_pc_is_thumb(struct gdbarch *gdbarch, CORE_ADDR memaddr)
#define MSYMBOL_IS_SPECIAL(msym)
static int arm_code_of_frame_writable(struct gdbarch *gdbarch, frame_info_ptr frame)
static int thumb2_copy_block_xfer(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_skip_bx_reg(frame_info_ptr frame, CORE_ADDR pc)
static void cleanup_alu_imm(struct gdbarch *gdbarch, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_data_proc_sreg_mimm(arm_insn_decode_record *thumb2_insn_r)
static CORE_ADDR arm_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
static int arm_m_addr_is_magic(struct gdbarch *gdbarch, CORE_ADDR addr)
static int thumb_instruction_restores_sp(unsigned short insn)
static int arm_copy_b_bl_blx(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
void _initialize_arm_tdep()
static int arm_copy_alu_shifted_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_instruction_restores_sp(unsigned int insn)
static const char * arm_fallback_mode_string
static int arm_record_strx(arm_insn_decode_record *arm_insn_r, uint32_t *record_buf, uint32_t *record_buf_mem, arm_record_strx_t str_type)
static void cleanup_load(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_ld_st_dual_ex_tbb(arm_insn_decode_record *thumb2_insn_r)
static unsigned arm_vfp_cprc_unit_length(enum arm_vfp_cprc_base_type b)
static struct arm_prologue_cache * arm_m_exception_cache(frame_info_ptr this_frame)
static int arm_record_exreg_ld_st_insn(arm_insn_decode_record *arm_insn_r)
static int arm_get_longjmp_target(frame_info_ptr frame, CORE_ADDR *pc)
static enum unwind_stop_reason arm_m_exception_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
static int thumb2_copy_b_bl_blx(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_vfp_abi_for_function(struct gdbarch *gdbarch, struct type *func_type)
static int displaced_in_arm_mode(struct regcache *regs)
static struct gdbarch * arm_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
void displaced_write_reg(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc)
static int arm_stack_frame_destroyed_p_1(struct gdbarch *gdbarch, CORE_ADDR pc)
static void load_write_pc(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, ULONGEST val)
static CORE_ADDR arm_adjust_breakpoint_address(struct gdbarch *gdbarch, CORE_ADDR bpaddr)
static const registry< bfd >::key< arm_per_bfd > arm_bfd_data_key
std::vector< CORE_ADDR > arm_software_single_step(struct regcache *regcache)
static const char ** valid_disassembly_styles
static enum gdb_osabi arm_elf_osabi_sniffer(bfd *abfd)
static void arm_stub_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static int arm_epilogue_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static int thumb_record_shift_add_sub(arm_insn_decode_record *thumb_insn_r)
static void install_b_bl_blx(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int cond, int exchange, int link, long offset)
#define ARM_BE_BREAKPOINT
static struct arm_prologue_cache * arm_make_prologue_cache(frame_info_ptr this_frame)
static int arm_m_exception_unwind_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static void set_fp_model_sfunc(const char *args, int from_tty, struct cmd_list_element *c)
static bool is_q_pseudo(struct gdbarch *gdbarch, int regnum)
static int arm_record_coproc_data_proc(arm_insn_decode_record *arm_insn_r)
static const char *const arm_mode_strings[]
static struct arm_prologue_cache * arm_exidx_fill_cache(frame_info_ptr this_frame, gdb_byte *entry)
#define THUMB_BE_BREAKPOINT
static int arm_record_media(arm_insn_decode_record *arm_insn_r)
static int thumb_record_add_sub_cmp_mov(arm_insn_decode_record *thumb_insn_r)
static void arm_show_force_mode(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
int arm_psr_thumb_bit(struct gdbarch *gdbarch)
struct frame_unwind arm_stub_unwind
static void arm_record_special_symbol(struct gdbarch *gdbarch, struct objfile *objfile, asymbol *sym)
#define IT_SCAN_THRESHOLD
static void install_bx_blx_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int link, unsigned int cond, unsigned int rm)
static void thumb_process_displaced_16bit_insn(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_media(struct gdbarch *gdbarch, uint32_t insn, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_ld_st_multiple(arm_insn_decode_record *thumb2_insn_r)
static const gdb_byte arm_default_thumb_be_breakpoint[]
CORE_ADDR arm_get_next_pcs_addr_bits_remove(struct arm_get_next_pcs *self, CORE_ADDR val)
static unsigned int thumb_expand_immediate(unsigned int imm)
static const registry< bfd >::key< arm_exidx_data > arm_exidx_data_key
static struct arm_stack_item * pop_stack_item(struct arm_stack_item *si)
static int arm_copy_unpred(struct gdbarch *gdbarch, uint32_t insn, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_miscellaneous(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
struct frame_base arm_normal_base
static int arm_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
static int insn_references_pc(uint32_t insn, uint32_t bitmask)
static int thumb2_copy_alu_imm(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define THUMB2_INSN_SIZE_BYTES
static enum return_value_convention arm_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static void arm_scan_prologue(frame_info_ptr this_frame, struct arm_prologue_cache *cache)
static int thumb2_copy_copro_load_store(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_cache_get_sp_register(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, int regnum)
static void arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
static void arm_set_abi(const char *args, int from_tty, struct cmd_list_element *c)
static enum register_status arm_neon_quad_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
#define THUMB_LE_BREAKPOINT
static int thumb2_decode_ext_reg_ld_st(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_record_data_proc_imm(arm_insn_decode_record *arm_insn_r)
static int thumb2_copy_load_reg_imm(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int writeback, int immed)
const target_desc * arm_read_mprofile_description(arm_m_profile_type m_type)
static const char * arm_abi_string
static enum register_status arm_mve_pseudo_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
static std::string arm_get_pc_address_flags(frame_info_ptr frame, CORE_ADDR pc)
static int thumb_copy_cbnz_cbz(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, unsigned int *destreg, int *offset)
static void cleanup_block_load_all(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, unsigned int rm)
static int arm_copy_bx_blx_reg(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define DISPLACED_STEPPING_ARCH_VERSION
static int arm_record_data_proc_misc_ld_str(arm_insn_decode_record *arm_insn_r)
void arm_displaced_init_closure(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, arm_displaced_step_copy_insn_closure *dsc)
static int arm_stub_unwind_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static struct value * value_of_arm_user_reg(frame_info_ptr frame, const void *baton)
static void arm_extract_return_value(struct type *type, struct regcache *regs, gdb_byte *valbuf)
static int arm_copy_ldr_str_ldrb_strb(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int load, int size, int usermode)
static void install_pc_relative(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int rd)
static void arm_m_exception_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static int thumb_copy_alu_reg(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
static void arm_cache_switch_prev_sp(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, int sp_regnum)
static void cleanup_svc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_decode_pc_relative_16bit(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void show_disassembly_style_sfunc(struct ui_file *, int, struct cmd_list_element *, const char *)
static int arm_decode_b_bl_ldmstm(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_svc_copro(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static const gdb_byte * arm_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
static void arm_write_pc(struct regcache *regcache, CORE_ADDR pc)
static int thumb_record_ld_st_imm_offset(arm_insn_decode_record *thumb_insn_r)
static int thumb2_copy_preload(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_dp_misc(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void show_fp_model(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
CORE_ADDR arm_skip_stub(frame_info_ptr frame, CORE_ADDR pc)
static bool arm_m_addr_is_lockup(CORE_ADDR addr)
static struct type * arm_register_type(struct gdbarch *gdbarch, int regnum)
static void arm_epilogue_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static CORE_ADDR arm_addr_bits_remove(struct gdbarch *gdbarch, CORE_ADDR val)
static int arm_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
static struct arm_prologue_cache * arm_make_stub_cache(frame_info_ptr this_frame)
static void alu_write_pc(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, ULONGEST val)
static void cleanup_pop_pc_16bit_all(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static struct value * arm_epilogue_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static void arm_print_float_info(struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, const char *args)
int(* sti_arm_hdl_fp_t)(arm_insn_decode_record *)
static int arm_copy_alu_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static const char * disassembly_style
static int thumb_record_misc(arm_insn_decode_record *thumb_insn_r)
int arm_get_next_pcs_is_thumb(struct arm_get_next_pcs *self)
static struct type * arm_ext_type(struct gdbarch *gdbarch)
const target_desc * arm_read_description(arm_fp_type fp_type, bool tls)
static void arm_mve_pseudo_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
static const struct frame_unwind arm_epilogue_frame_unwind
static void arm_cache_set_active_sp_value(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, CORE_ADDR val)
#define ARM_LE_BREAKPOINT
#define ARM_DISPLACED_MODIFIED_INSNS
target_desc * arm_create_target_description(arm_fp_type fp_type, bool tls)
target_desc * arm_create_mprofile_target_description(arm_m_profile_type m_type)
int arm_instruction_changes_pc(uint32_t this_instr)
int thumb2_instruction_changes_pc(unsigned short inst1, unsigned short inst2)
int condition_true(unsigned long cond, unsigned long status_reg)
int thumb_insn_size(unsigned short inst1)
int thumb_instruction_changes_pc(unsigned short inst)
#define UNMAKE_THUMB_ADDR(addr)
#define ARM_INT_REGISTER_SIZE
#define IS_AUT(instruction)
#define ARM_VFP2_REGS_SIZE
#define IS_PAC(instruction)
#define IS_PACG(instruction)
#define IS_THUMB_ADDR(addr)
#define ARM_CORE_REGS_SIZE
#define BranchDest(addr, instr)
#define ARM_FP_REGISTER_SIZE
#define IS_AUTG(instruction)
#define IS_PACBTI(instruction)
#define MAKE_THUMB_ADDR(addr)
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
bool find_reg(struct gdbarch *gdbarch, int reg, CORE_ADDR *offset_p)
bool store_would_trash(pv_t addr)
void store(pv_t addr, CORE_ADDR size, pv_t value)
enum register_status raw_read(int regnum, gdb_byte *buf)
enum register_status raw_read_part(int regnum, int offset, int len, gdb_byte *buf)
enum register_status cooked_read(int regnum, gdb_byte *buf)
void cooked_write(int regnum, const gdb_byte *buf)
void raw_write_part(int regnum, int offset, int len, const gdb_byte *buf)
void raw_write(int regnum, const gdb_byte *buf)
struct cmd_list_element * showlist
struct cmd_list_element * setlist
struct cmd_list_element * showdebuglist
struct cmd_list_element * setdebuglist
set_show_commands add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
set_show_commands add_setshow_prefix_cmd(const char *name, command_class theclass, const char *set_doc, const char *show_doc, cmd_list_element **set_subcommands_list, cmd_list_element **show_subcommands_list, cmd_list_element **set_list, cmd_list_element **show_list)
set_show_commands add_setshow_boolean_cmd(const char *name, enum command_class theclass, bool *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
int safe_read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, ULONGEST *return_value)
ULONGEST read_code_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
static void store_signed_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, LONGEST val)
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
@ RETURN_VALUE_ABI_RETURNS_ADDRESS
@ RETURN_VALUE_REGISTER_CONVENTION
@ RETURN_VALUE_STRUCT_CONVENTION
char * get_disassembler_options(struct gdbarch *gdbarch)
void set_disassembler_options(const char *prospective_options)
#define displaced_debug_printf(fmt,...)
void * dwarf2_frame_allocate_fn_data(frame_info_ptr this_frame, void **this_cache, fn_prev_register cookie, unsigned long size)
void * dwarf2_frame_get_fn_data(frame_info_ptr this_frame, void **this_cache, fn_prev_register cookie)
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, frame_info_ptr))
@ DWARF2_FRAME_REG_SAVED_VAL_EXP
ssize_t read(int fd, void *buf, size_t count)
struct value * value_of_register(int regnum, frame_info_ptr frame)
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
frame_info_ptr get_next_frame(frame_info_ptr this_frame)
int frame_relative_level(frame_info_ptr fi)
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
ULONGEST frame_unwind_register_unsigned(frame_info_ptr next_frame, int regnum)
CORE_ADDR get_frame_pc(frame_info_ptr frame)
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
enum frame_type get_frame_type(frame_info_ptr frame)
bool get_frame_pc_masked(frame_info_ptr frame)
ULONGEST get_frame_memory_unsigned(frame_info_ptr this_frame, CORE_ADDR addr, int len)
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
void set_frame_previous_pc_masked(frame_info_ptr frame)
frame_info_ptr get_current_frame(void)
CORE_ADDR get_frame_address_in_block(frame_info_ptr this_frame)
frame_info_ptr get_prev_frame(frame_info_ptr this_frame)
CORE_ADDR get_frame_base(frame_info_ptr fi)
#define FRAME_OBSTACK_ZALLOC(TYPE)
static gdb_bfd_section_range gdb_bfd_sections(bfd *abfd)
void set_gdbarch_char_signed(struct gdbarch *gdbarch, int char_signed)
void set_gdbarch_disassembler_options(struct gdbarch *gdbarch, char **disassembler_options)
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
void set_gdbarch_register_sim_regno(struct gdbarch *gdbarch, gdbarch_register_sim_regno_ftype *register_sim_regno)
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
void set_gdbarch_valid_disassembler_options(struct gdbarch *gdbarch, const disasm_options_and_args_t *valid_disassembler_options)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
void set_gdbarch_code_of_frame_writable(struct gdbarch *gdbarch, gdbarch_code_of_frame_writable_ftype *code_of_frame_writable)
void set_gdbarch_write_pc(struct gdbarch *gdbarch, gdbarch_write_pc_ftype *write_pc)
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype *get_longjmp_target)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_addr_bits_remove(struct gdbarch *gdbarch, gdbarch_addr_bits_remove_ftype *addr_bits_remove)
void set_gdbarch_elf_make_msymbol_special(struct gdbarch *gdbarch, gdbarch_elf_make_msymbol_special_ftype *elf_make_msymbol_special)
int gdbarch_addr_bit(struct gdbarch *gdbarch)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_get_pc_address_flags(struct gdbarch *gdbarch, gdbarch_get_pc_address_flags_ftype *get_pc_address_flags)
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype *skip_trampoline_code)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_wchar_signed(struct gdbarch *gdbarch, int wchar_signed)
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
void set_gdbarch_gnu_triplet_regexp(struct gdbarch *gdbarch, gdbarch_gnu_triplet_regexp_ftype *gnu_triplet_regexp)
bool gdbarch_displaced_step_copy_insn_closure_by_addr_p(struct gdbarch *gdbarch)
int gdbarch_num_regs(struct gdbarch *gdbarch)
void set_gdbarch_breakpoint_kind_from_current_state(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_current_state_ftype *breakpoint_kind_from_current_state)
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
enum bfd_endian gdbarch_byte_order_for_code(struct gdbarch *gdbarch)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_long_double_format(struct gdbarch *gdbarch, const struct floatformat **long_double_format)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
void set_gdbarch_adjust_breakpoint_address(struct gdbarch *gdbarch, gdbarch_adjust_breakpoint_address_ftype *adjust_breakpoint_address)
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *register_type)
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype *print_insn)
const struct target_desc * gdbarch_target_desc(struct gdbarch *gdbarch)
void set_gdbarch_record_special_symbol(struct gdbarch *gdbarch, gdbarch_record_special_symbol_ftype *record_special_symbol)
void set_gdbarch_coff_make_msymbol_special(struct gdbarch *gdbarch, gdbarch_coff_make_msymbol_special_ftype *coff_make_msymbol_special)
void set_gdbarch_stack_frame_destroyed_p(struct gdbarch *gdbarch, gdbarch_stack_frame_destroyed_p_ftype *stack_frame_destroyed_p)
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
CORE_ADDR gdbarch_addr_bits_remove(struct gdbarch *gdbarch, CORE_ADDR addr)
void set_gdbarch_type_align(struct gdbarch *gdbarch, gdbarch_type_align_ftype *type_align)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_print_float_info(struct gdbarch *gdbarch, gdbarch_print_float_info_ftype *print_float_info)
void set_gdbarch_double_format(struct gdbarch *gdbarch, const struct floatformat **double_format)
void set_gdbarch_float_format(struct gdbarch *gdbarch, const struct floatformat **float_format)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
void set_gdbarch_vbit_in_delta(struct gdbarch *gdbarch, int vbit_in_delta)
const displaced_step_copy_insn_closure * gdbarch_displaced_step_copy_insn_closure_by_addr(struct gdbarch *gdbarch, inferior *inf, CORE_ADDR addr)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep_base *tdep)
function_call_return_method
int field_is_static(struct field *f)
struct type * arch_composite_type(struct gdbarch *gdbarch, const char *name, enum type_code code)
const struct floatformat * floatformats_ieee_double_littlebyte_bigword[BFD_ENDIAN_UNKNOWN]
struct type * init_vector_type(struct type *elt_type, int n)
const struct floatformat * floatformats_ieee_single[BFD_ENDIAN_UNKNOWN]
struct type * arch_float_type(struct gdbarch *gdbarch, int bit, const char *name, const struct floatformat **floatformats)
const struct floatformat * floatformats_arm_ext[BFD_ENDIAN_UNKNOWN]
unsigned type_align(struct type *type)
const struct floatformat * floatformats_ieee_double[BFD_ENDIAN_UNKNOWN]
void append_composite_type_field(struct type *t, const char *name, struct type *field)
bool is_fixed_point_type(struct type *type)
struct type * check_typedef(struct type *type)
#define TYPE_IS_REFERENCE(t)
#define TYPE_FIELD_BITSIZE(thistype, n)
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t err
mach_port_t kern_return_t mach_port_t mach_msg_type_name_t msgportsPoly mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
struct inferior * current_inferior(void)
struct language_pass_by_ref_info language_pass_by_reference(struct type *type)
struct bound_minimal_symbol lookup_minimal_symbol(const char *name, const char *sfile, struct objfile *objf)
struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
struct minimal_symbol * lookup_minimal_symbol_by_pc_name(CORE_ADDR pc, const char *name, struct objfile *objf)
observable< struct objfile * > new_objfile
struct obj_section * find_pc_section(CORE_ADDR pc)
#define ALL_OBJFILE_OSECTIONS(objfile, osect)
static int in_plt_section(CORE_ADDR pc)
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
void generic_elf_osabi_sniff_abi_tag_sections(bfd *abfd, asection *sect, enum gdb_osabi *osabi)
void gdbarch_register_osabi_sniffer(enum bfd_architecture arch, enum bfd_flavour flavour, enum gdb_osabi(*sniffer_fn)(bfd *))
bool producer_is_llvm(const char *producer)
struct program_space * current_program_space
pv_t pv_constant(CORE_ADDR k)
pv_t pv_register(int reg, CORE_ADDR k)
pv_t pv_add(pv_t a, pv_t b)
pv_t pv_add_constant(pv_t v, CORE_ADDR k)
int pv_is_register(pv_t a, int r)
int pv_is_constant(pv_t a)
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
int record_full_arch_list_add_mem(CORE_ADDR addr, int len)
int record_full_arch_list_add_end(void)
unsigned int record_debug
CORE_ADDR regcache_read_pc(struct regcache *regcache)
enum register_status regcache_raw_read_signed(struct regcache *regcache, int regnum, LONGEST *val)
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
const reggroup *const float_reggroup
const reggroup *const save_reggroup
const reggroup *const all_reggroup
const reggroup *const restore_reggroup
void(* func)(remote_target *remote, char *)
void register_remote_g_packet_guess(struct gdbarch *gdbarch, int bytes, const struct target_desc *tdesc)
void(* cleanup)(struct gdbarch *, struct regcache *, arm_displaced_step_copy_insn_closure *)
int(* copy_svc_os)(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
struct arm_displaced_step_copy_insn_closure::@7::@10 block
union arm_displaced_step_copy_insn_closure::@7 u
struct arm_displaced_step_copy_insn_closure::@7::@9 branch
struct arm_displaced_step_copy_insn_closure::@7::@8 ldst
struct arm_displaced_step_copy_insn_closure::@7::@11 preload
ULONGEST tmp[DISPLACED_TEMPS]
struct arm_displaced_step_copy_insn_closure::@7::@12 svc
unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS]
std::vector< std::vector< arm_exidx_entry > > section_maps
bool operator<(const arm_exidx_entry &other) const
const gdb_byte * thumb_breakpoint
const gdb_byte * arm_breakpoint
int m_profile_psp_s_regnum
struct type * arm_ext_type
int m_profile_psp_ns_regnum
const gdb_byte * thumb2_breakpoint
int thumb2_breakpoint_size
int m_profile_msp_ns_regnum
int thumb_breakpoint_size
struct type * neon_double_type
struct type * neon_quad_type
int m_profile_msp_s_regnum
int(* arm_syscall_record)(struct regcache *regcache, unsigned long svc_number)
struct regcache * regcache
struct regcache * regcache
struct arm_mem_r * arm_mems
bool operator<(const arm_mapping_symbol &other) const
DISABLE_COPY_AND_ASSIGN(arm_per_bfd)
std::unique_ptr< bool[]> section_maps_sorted
arm_per_bfd(size_t num_sections)
std::unique_ptr< arm_mapping_symbol_vec[]> section_maps
trad_frame_saved_reg * saved_regs
gdb::optional< bool > ra_signed_state
arm_prologue_cache()=default
struct arm_stack_item * prev
CORE_ADDR value_address() const
struct minimal_symbol * minsym
struct type * builtin_int0
struct type * builtin_uint16
struct type * builtin_double
struct type * builtin_func_ptr
struct type * builtin_data_ptr
struct type * builtin_uint32
struct type * builtin_uint64
struct type * builtin_uint8
struct type * builtin_int16
struct type * builtin_void
struct type * builtin_float
const char * producer() const
struct dwarf2_frame_state_reg::@42::@43 exp
enum dwarf2_frame_reg_rule how
union dwarf2_frame_state_reg::@42 loc
LONGEST loc_bitpos() const
struct type * type() const
struct gdbarch_list * next
const char * linkage_name() const
CORE_ADDR value_address(objfile *objfile) const
struct bfd_section * the_bfd_section
auto_obstack objfile_obstack
void set_addr(LONGEST addr)
struct type * target_type() const
struct field & field(int idx) const
void set_name(const char *name)
void set_is_vector(bool is_vector)
struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
tdesc_arch_data_up tdesc_data_alloc(void)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
static const registry< gdbarch >::key< tdesc_arch_data > tdesc_data
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, tdesc_arch_data_up &&early_data, tdesc_unknown_register_ftype unk_reg_cb)
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int tdesc_has_registers(const struct target_desc *target_desc)
struct type * tdesc_register_type(struct gdbarch *gdbarch, int regno)
int tdesc_numbered_register_choices(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *const names[])
int tdesc_unnumbered_register(const struct tdesc_feature *feature, const char *name)
std::unique_ptr< tdesc_arch_data, tdesc_arch_data_deleter > tdesc_arch_data_up
void target_float_convert(const gdb_byte *from, const struct type *from_type, gdb_byte *to, const struct type *to_type)
int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
int target_has_registers()
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct gdbarch *gdbarch)
struct value * trad_frame_get_prev_register(frame_info_ptr this_frame, trad_frame_saved_reg this_saved_regs[], int regnum)
void user_reg_add(struct gdbarch *gdbarch, const char *name, user_reg_read_ftype *xread, const void *baton)
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
void gdb_printf(struct ui_file *stream, const char *format,...)
void gdb_puts(const char *linebuffer, struct ui_file *stream)
struct type * value_type(const struct value *value)
CORE_ADDR value_as_address(struct value *val)
gdb::array_view< const gdb_byte > value_contents(struct value *value)
LONGEST value_as_long(struct value *val)
LONGEST unpack_long(struct type *type, const gdb_byte *valaddr)