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xtensa-tdep.c
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1/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
2
3 Copyright (C) 2003-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "solib-svr4.h"
23#include "symtab.h"
24#include "gdbtypes.h"
25#include "gdbcore.h"
26#include "value.h"
27#include "osabi.h"
28#include "regcache.h"
29#include "reggroups.h"
30#include "regset.h"
31
32#include "dwarf2/frame.h"
33#include "frame-base.h"
34#include "frame-unwind.h"
35
36#include "arch-utils.h"
37#include "gdbarch.h"
38
39#include "command.h"
40#include "gdbcmd.h"
41
42#include "xtensa-isa.h"
43#include "xtensa-tdep.h"
44#include "xtensa-config.h"
45#include <algorithm>
46
47
48static unsigned int xtensa_debug_level = 0;
49
50#define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 gdb_printf (gdb_stdlog, "(warn ) " args)
53
54#define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 gdb_printf (gdb_stdlog, "(info ) " args)
57
58#define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 gdb_printf (gdb_stdlog, "(trace) " args)
61
62#define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 gdb_printf (gdb_stdlog, "(verb ) " args)
65
66
67/* According to the ABI, the SP must be aligned to 16-byte boundaries. */
68#define SP_ALIGNMENT 16
69
70
71/* On Windowed ABI, we use a6 through a11 for passing arguments
72 to a function called by GDB because CALL4 is used. */
73#define ARGS_NUM_REGS 6
74#define REGISTER_SIZE 4
75
76
77/* Extract the call size from the return address or PS register. */
78#define PS_CALLINC_SHIFT 16
79#define PS_CALLINC_MASK 0x00030000
80#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
82
83/* On TX, hardware can be configured without Exception Option.
84 There is no PS register in this case. Inside XT-GDB, let us treat
85 it as a virtual read-only register always holding the same value. */
86#define TX_PS 0x20
87
88/* ABI-independent macros. */
89#define ARG_NOF(tdep) \
90 (tdep->call_abi \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92#define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
96
97/* XTENSA_IS_ENTRY tests whether the first byte of an instruction
98 indicates that the instruction is an ENTRY instruction. */
99
100#define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
103
104#define XTENSA_ENTRY_LENGTH 3
105
106/* windowing_enabled() returns true, if windowing is enabled.
107 WOE must be set to 1; EXCM to 0.
108 Note: We assume that EXCM is always 0 for XEA1. */
109
110#define PS_WOE (1<<18)
111#define PS_EXC (1<<4)
112
113/* Big enough to hold the size of the largest register in bytes. */
114#define XTENSA_MAX_REGISTER_SIZE 64
115
116static int
117windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
118{
119 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
120
121 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
122 if (tdep->call_abi == CallAbiCall0Only)
123 return 0;
124
125 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
126}
127
128/* Convert a live A-register number to the corresponding AR-register
129 number. */
130static int
131arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
132{
133 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
134 int arreg;
135
136 arreg = a_regnum - tdep->a0_base;
137 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
138 arreg &= tdep->num_aregs - 1;
139
140 return arreg + tdep->ar_base;
141}
142
143/* Convert a live AR-register number to the corresponding A-register order
144 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
145static int
146areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
147{
148 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
149 int areg;
150
151 areg = ar_regnum - tdep->ar_base;
152 if (areg < 0 || areg >= tdep->num_aregs)
153 return -1;
154 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
155 return (areg > 15) ? -1 : areg;
156}
157
158/* Read Xtensa register directly from the hardware. */
159static unsigned long
161{
162 ULONGEST value;
163
165 return (unsigned long) value;
166}
167
168/* Write Xtensa register directly to the hardware. */
169static void
171{
173}
174
175/* Return the window size of the previous call to the function from which we
176 have just returned.
177
178 This function is used to extract the return value after a called function
179 has returned to the caller. On Xtensa, the register that holds the return
180 value (from the perspective of the caller) depends on what call
181 instruction was used. For now, we are assuming that the call instruction
182 precedes the current address, so we simply analyze the call instruction.
183 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
184 method to call the inferior function. */
185
186static int
187extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
188{
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 int winsize = 4;
191 int insn;
192 gdb_byte buf[4];
193
194 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
195
196 /* Read the previous instruction (should be a call[x]{4|8|12}. */
197 read_memory (pc-3, buf, 3);
198 insn = extract_unsigned_integer (buf, 3, byte_order);
199
200 /* Decode call instruction:
201 Little Endian
202 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
203 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
204 Big Endian
205 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
206 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
207
208 if (byte_order == BFD_ENDIAN_LITTLE)
209 {
210 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
211 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
212 }
213 else
214 {
215 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
216 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
217 }
218 return winsize;
219}
220
221
222/* REGISTER INFORMATION */
223
224/* Find register by name. */
225static int
227{
228 int i;
229 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
230
231 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++)
232 if (strcasecmp (tdep->regmap[i].name, name) == 0)
233 return i;
234
235 return -1;
236}
237
238/* Returns the name of a register. */
239static const char *
241{
242 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
243
244 /* Return the name stored in the register map. */
245 return tdep->regmap[regnum].name;
246}
247
248/* Return the type of a register. Create a new type, if necessary. */
249
250static struct type *
252{
253 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
254
255 /* Return signed integer for ARx and Ax registers. */
256 if ((regnum >= tdep->ar_base
257 && regnum < tdep->ar_base + tdep->num_aregs)
258 || (regnum >= tdep->a0_base
259 && regnum < tdep->a0_base + 16))
261
263 || regnum == tdep->a0_base + 1)
265
266 /* Return the stored type for all other registers. */
267 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
268 {
269 xtensa_register_t* reg = &tdep->regmap[regnum];
270
271 /* Set ctype for this register (only the first time). */
272
273 if (reg->ctype == 0)
274 {
275 struct ctype_cache *tp;
276 int size = reg->byte_size;
277
278 /* We always use the memory representation,
279 even if the register width is smaller. */
280 switch (size)
281 {
282 case 1:
284 break;
285
286 case 2:
288 break;
289
290 case 4:
292 break;
293
294 case 8:
296 break;
297
298 case 16:
300 break;
301
302 default:
303 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
304 if (tp->size == size)
305 break;
306
307 if (tp == NULL)
308 {
309 std::string name = string_printf ("int%d", size * 8);
310
311 tp = XNEW (struct ctype_cache);
312 tp->next = tdep->type_entries;
313 tdep->type_entries = tp;
314 tp->size = size;
315 tp->virtual_type
316 = arch_integer_type (gdbarch, size * 8, 1, name.c_str ());
317 }
318
319 reg->ctype = tp->virtual_type;
320 }
321 }
322 return reg->ctype;
323 }
324
325 internal_error (_("invalid register number %d"), regnum);
326 return 0;
327}
328
329
330/* Return the 'local' register number for stubs, dwarf2, etc.
331 The debugging information enumerates registers starting from 0 for A0
332 to n for An. So, we only have to add the base number for A0. */
333
334static int
336{
337 int i;
338 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
339
340 if (regnum >= 0 && regnum < 16)
341 return tdep->a0_base + regnum;
342
343 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++)
344 if (regnum == tdep->regmap[i].target_number)
345 return i;
346
347 return -1;
348}
349
350
351/* Write the bits of a masked register to the various registers.
352 Only the masked areas of these registers are modified; the other
353 fields are untouched. The size of masked registers is always less
354 than or equal to 32 bits. */
355
356static void
358 xtensa_register_t *reg, const gdb_byte *buffer)
359{
360 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4];
361 const xtensa_mask_t *mask = reg->mask;
362
363 int shift = 0; /* Shift for next mask (mod 32). */
364 int start, size; /* Start bit and size of current mask. */
365
366 unsigned int *ptr = value;
367 unsigned int regval, m, mem = 0;
368
369 int bytesize = reg->byte_size;
370 int bitsize = bytesize * 8;
371 int i, r;
372
373 DEBUGTRACE ("xtensa_register_write_masked ()\n");
374
375 /* Copy the masked register to host byte-order. */
376 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG)
377 for (i = 0; i < bytesize; i++)
378 {
379 mem >>= 8;
380 mem |= (buffer[bytesize - i - 1] << 24);
381 if ((i & 3) == 3)
382 *ptr++ = mem;
383 }
384 else
385 for (i = 0; i < bytesize; i++)
386 {
387 mem >>= 8;
388 mem |= (buffer[i] << 24);
389 if ((i & 3) == 3)
390 *ptr++ = mem;
391 }
392
393 /* We might have to shift the final value:
394 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
395 bytesize & 3 == x -> shift (4-x) * 8. */
396
397 *ptr = mem >> (((0 - bytesize) & 3) * 8);
398 ptr = value;
399 mem = *ptr;
400
401 /* Write the bits to the masked areas of the other registers. */
402 for (i = 0; i < mask->count; i++)
403 {
404 start = mask->mask[i].bit_start;
405 size = mask->mask[i].bit_size;
406 regval = mem >> shift;
407
408 if ((shift += size) > bitsize)
409 error (_("size of all masks is larger than the register"));
410
411 if (shift >= 32)
412 {
413 mem = *(++ptr);
414 shift -= 32;
415 bitsize -= 32;
416
417 if (shift > 0)
418 regval |= mem << (size - shift);
419 }
420
421 /* Make sure we have a valid register. */
422 r = mask->mask[i].reg_num;
423 if (r >= 0 && size > 0)
424 {
425 /* Don't overwrite the unmasked areas. */
426 ULONGEST old_val;
428 m = 0xffffffff >> (32 - size) << start;
429 regval <<= start;
430 regval = (regval & m) | (old_val & ~m);
432 }
433 }
434}
435
436
437/* Read a tie state or mapped registers. Read the masked areas
438 of the registers and assemble them into a single value. */
439
440static enum register_status
442 xtensa_register_t *reg, gdb_byte *buffer)
443{
444 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4];
445 const xtensa_mask_t *mask = reg->mask;
446
447 int shift = 0;
448 int start, size;
449
450 unsigned int *ptr = value;
451 unsigned int regval, mem = 0;
452
453 int bytesize = reg->byte_size;
454 int bitsize = bytesize * 8;
455 int i;
456
457 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
458 reg->name == 0 ? "" : reg->name);
459
460 /* Assemble the register from the masked areas of other registers. */
461 for (i = 0; i < mask->count; i++)
462 {
463 int r = mask->mask[i].reg_num;
464 if (r >= 0)
465 {
466 enum register_status status;
467 ULONGEST val;
468
469 status = regcache->cooked_read (r, &val);
470 if (status != REG_VALID)
471 return status;
472 regval = (unsigned int) val;
473 }
474 else
475 regval = 0;
476
477 start = mask->mask[i].bit_start;
478 size = mask->mask[i].bit_size;
479
480 regval >>= start;
481
482 if (size < 32)
483 regval &= (0xffffffff >> (32 - size));
484
485 mem |= regval << shift;
486
487 if ((shift += size) > bitsize)
488 error (_("size of all masks is larger than the register"));
489
490 if (shift >= 32)
491 {
492 *ptr++ = mem;
493 bitsize -= 32;
494 shift -= 32;
495
496 if (shift == 0)
497 mem = 0;
498 else
499 mem = regval >> (size - shift);
500 }
501 }
502
503 if (shift > 0)
504 *ptr = mem;
505
506 /* Copy value to target byte order. */
507 ptr = value;
508 mem = *ptr;
509
510 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG)
511 for (i = 0; i < bytesize; i++)
512 {
513 if ((i & 3) == 0)
514 mem = *ptr++;
515 buffer[bytesize - i - 1] = mem & 0xff;
516 mem >>= 8;
517 }
518 else
519 for (i = 0; i < bytesize; i++)
520 {
521 if ((i & 3) == 0)
522 mem = *ptr++;
523 buffer[i] = mem & 0xff;
524 mem >>= 8;
525 }
526
527 return REG_VALID;
528}
529
530
531/* Read pseudo registers. */
532
533static enum register_status
536 int regnum,
537 gdb_byte *buffer)
538{
539 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
541 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
542
543 /* Read aliases a0..a15, if this is a Windowed ABI. */
545 && (regnum >= tdep->a0_base)
546 && (regnum <= tdep->a0_base + 15))
547 {
548 ULONGEST value;
549 enum register_status status;
550
552 &value);
553 if (status != REG_VALID)
554 return status;
556 }
557
558 /* We can always read non-pseudo registers. */
559 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
560 return regcache->raw_read (regnum, buffer);
561
562 /* We have to find out how to deal with priveleged registers.
563 Let's treat them as pseudo-registers, but we cannot read/write them. */
564
565 else if (tdep->call_abi == CallAbiCall0Only
566 || regnum < tdep->a0_base)
567 {
568 buffer[0] = (gdb_byte)0;
569 buffer[1] = (gdb_byte)0;
570 buffer[2] = (gdb_byte)0;
571 buffer[3] = (gdb_byte)0;
572 return REG_VALID;
573 }
574 /* Pseudo registers. */
575 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
576 {
577 xtensa_register_t *reg = &tdep->regmap[regnum];
579 int flags = tdep->target_flags;
580
581 /* We cannot read Unknown or Unmapped registers. */
583 {
585 {
586 warning (_("cannot read register %s"),
588 return REG_VALID;
589 }
590 }
591
592 /* Some targets cannot read TIE register files. */
593 else if (type == xtRegisterTypeTieRegfile)
594 {
595 /* Use 'fetch' to get register? */
597 {
598 warning (_("cannot read register"));
599 return REG_VALID;
600 }
601
602 /* On some targets (esp. simulators), we can always read the reg. */
603 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
604 {
605 warning (_("cannot read register"));
606 return REG_VALID;
607 }
608 }
609
610 /* We can always read mapped registers. */
612 return xtensa_register_read_masked (regcache, reg, buffer);
613
614 /* Assume that we can read the register. */
615 return regcache->raw_read (regnum, buffer);
616 }
617 else
618 internal_error (_("invalid register number %d"), regnum);
619}
620
621
622/* Write pseudo registers. */
623
624static void
626 struct regcache *regcache,
627 int regnum,
628 const gdb_byte *buffer)
629{
630 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
632 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
633
634 /* Renumber register, if aliases a0..a15 on Windowed ABI. */
636 && (regnum >= tdep->a0_base)
637 && (regnum <= tdep->a0_base + 15))
638 {
639 ULONGEST value;
641 tdep->wb_regnum, &value);
643 }
644
645 /* We can always write 'core' registers.
646 Note: We might have converted Ax->ARy. */
647 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
648 regcache->raw_write (regnum, buffer);
649
650 /* We have to find out how to deal with priveleged registers.
651 Let's treat them as pseudo-registers, but we cannot read/write them. */
652
653 else if (regnum < tdep->a0_base)
654 {
655 return;
656 }
657 /* Pseudo registers. */
658 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
659 {
660 xtensa_register_t *reg = &tdep->regmap[regnum];
662 int flags = tdep->target_flags;
663
664 /* On most targets, we cannot write registers
665 of type "Unknown" or "Unmapped". */
667 {
669 {
670 warning (_("cannot write register %s"),
672 return;
673 }
674 }
675
676 /* Some targets cannot read TIE register files. */
677 else if (type == xtRegisterTypeTieRegfile)
678 {
679 /* Use 'store' to get register? */
681 {
682 warning (_("cannot write register"));
683 return;
684 }
685
686 /* On some targets (esp. simulators), we can always write
687 the register. */
688 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
689 {
690 warning (_("cannot write register"));
691 return;
692 }
693 }
694
695 /* We can always write mapped registers. */
697 {
699 return;
700 }
701
702 /* Assume that we can write the register. */
703 regcache->raw_write (regnum, buffer);
704 }
705 else
706 internal_error (_("invalid register number %d"), regnum);
707}
708
713
714static void
716{
717 int i;
718
722
723 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
724 xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i).release (),
726}
727
728static void
730{
731 /* Xtensa-specific groups. */
735
736 for (int i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
738}
739
740static int
742{
743 int i;
744
745 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
746 if (group == xtensa_cp[i])
747 return i;
748
749 return -1;
750}
751
752#define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
753 | XTENSA_REGISTER_FLAGS_WRITABLE \
754 | XTENSA_REGISTER_FLAGS_VOLATILE)
755
756#define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
757 | XTENSA_REGISTER_FLAGS_WRITABLE)
758
759static int
761 int regnum,
762 const struct reggroup *group)
763{
764 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
765 xtensa_register_t* reg = &tdep->regmap[regnum];
768 int cp_number;
769
770 if (group == save_reggroup)
771 /* Every single register should be included into the list of registers
772 to be watched for changes while using -data-list-changed-registers. */
773 return 1;
774
775 /* First, skip registers that are not visible to this target
776 (unknown and unmapped registers when not using ISS). */
777
779 return 0;
780 if (group == all_reggroup)
781 return 1;
782 if (group == xtensa_ar_reggroup)
783 return rg & xtRegisterGroupAddrReg;
784 if (group == xtensa_user_reggroup)
785 return rg & xtRegisterGroupUser;
786 if (group == float_reggroup)
787 return rg & xtRegisterGroupFloat;
788 if (group == general_reggroup)
789 return rg & xtRegisterGroupGeneral;
790 if (group == system_reggroup)
791 return rg & xtRegisterGroupState;
792 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
793 return rg & xtRegisterGroupVectra;
794 if (group == restore_reggroup)
796 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
797 cp_number = xtensa_coprocessor_register_group (group);
798 if (cp_number >= 0)
799 return rg & (xtRegisterGroupCP0 << cp_number);
800 else
801 return 1;
802}
803
804
805/* Supply register REGNUM from the buffer specified by GREGS and LEN
806 in the general-purpose register set REGSET to register cache
807 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
808
809static void
811 struct regcache *rc,
812 int regnum,
813 const void *gregs,
814 size_t len)
815{
816 const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs;
817 struct gdbarch *gdbarch = rc->arch ();
818 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
819 int i;
820
821 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
822
823 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
824 rc->raw_supply (gdbarch_pc_regnum (gdbarch), (char *) &regs->pc);
825 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
826 rc->raw_supply (gdbarch_ps_regnum (gdbarch), (char *) &regs->ps);
827 if (regnum == tdep->wb_regnum || regnum == -1)
828 rc->raw_supply (tdep->wb_regnum,
829 (char *) &regs->windowbase);
830 if (regnum == tdep->ws_regnum || regnum == -1)
831 rc->raw_supply (tdep->ws_regnum,
832 (char *) &regs->windowstart);
833 if (regnum == tdep->lbeg_regnum || regnum == -1)
834 rc->raw_supply (tdep->lbeg_regnum,
835 (char *) &regs->lbeg);
836 if (regnum == tdep->lend_regnum || regnum == -1)
837 rc->raw_supply (tdep->lend_regnum,
838 (char *) &regs->lend);
839 if (regnum == tdep->lcount_regnum || regnum == -1)
840 rc->raw_supply (tdep->lcount_regnum,
841 (char *) &regs->lcount);
842 if (regnum == tdep->sar_regnum || regnum == -1)
843 rc->raw_supply (tdep->sar_regnum,
844 (char *) &regs->sar);
845 if (regnum >=tdep->ar_base
846 && regnum < tdep->ar_base
847 + tdep->num_aregs)
848 rc->raw_supply
849 (regnum, (char *) &regs->ar[regnum - tdep->ar_base]);
850 else if (regnum == -1)
851 {
852 for (i = 0; i < tdep->num_aregs; ++i)
853 rc->raw_supply (tdep->ar_base + i,
854 (char *) &regs->ar[i]);
855 }
856}
857
858
859/* Xtensa register set. */
860
861static struct regset
863{
864 NULL,
866};
867
868
869/* Iterate over supported core file register note sections. */
870
871static void
874 void *cb_data,
875 const struct regcache *regcache)
876{
877 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
878
879 cb (".reg", sizeof (xtensa_elf_gregset_t), sizeof (xtensa_elf_gregset_t),
880 &xtensa_gregset, NULL, cb_data);
881}
882
883
884/* Handling frames. */
885
886/* Number of registers to save in case of Windowed ABI. */
887#define XTENSA_NUM_SAVED_AREGS 12
888
889/* Frame cache part for Windowed ABI. */
891{
892 int wb; /* WINDOWBASE of the previous frame. */
893 int callsize; /* Call size of this frame. */
894 int ws; /* WINDOWSTART of the previous frame. It keeps track of
895 life windows only. If there is no bit set for the
896 window, that means it had been already spilled
897 because of window overflow. */
898
899 /* Addresses of spilled A-registers.
900 AREGS[i] == -1, if corresponding AR is alive. */
903
904/* Call0 ABI Definitions. */
905
906#define C0_MAXOPDS 3 /* Maximum number of operands for prologue
907 analysis. */
908#define C0_CLESV 12 /* Callee-saved registers are here and up. */
909#define C0_SP 1 /* Register used as SP. */
910#define C0_FP 15 /* Register used as FP. */
911#define C0_RA 0 /* Register used as return address. */
912#define C0_ARGS 2 /* Register used as first arg/retval. */
913#define C0_NARGS 6 /* Number of A-regs for args/retvals. */
914
915/* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
916 A-register where the current content of the reg came from (in terms
917 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
918 mean that the original content of the register was saved to the stack.
919 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
920 know where SP will end up until the entire prologue has been analyzed. */
922#define C0_CONST -1 /* fr_reg value if register contains a constant. */
923#define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
924#define C0_NOSTK -1 /* to_stk value if register has not been stored. */
925
926extern xtensa_isa xtensa_default_isa;
928typedef struct xtensa_c0reg
930 int fr_reg; /* original register from which register content
931 is derived, or C0_CONST, or C0_INEXP. */
932 int fr_ofs; /* constant offset from reg, or immediate value. */
933 int to_stk; /* offset from original SP to register (4-byte aligned),
934 or C0_NOSTK if register has not been saved. */
936
937/* Frame cache part for Call0 ABI. */
938typedef struct xtensa_call0_frame_cache
940 int c0_frmsz; /* Stack frame size. */
941 int c0_hasfp; /* Current frame uses frame pointer. */
942 int fp_regnum; /* A-register used as FP. */
943 int c0_fp; /* Actual value of frame pointer. */
944 int c0_fpalign; /* Dynamic adjustment for the stack
945 pointer. It's an AND mask. Zero,
946 if alignment was not adjusted. */
947 int c0_old_sp; /* In case of dynamic adjustment, it is
948 a register holding unaligned sp.
949 C0_INEXP, when undefined. */
950 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
951 stack offset. C0_NOSTK otherwise. */
953 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
956typedef struct xtensa_frame_cache
958 CORE_ADDR base; /* Stack pointer of this frame. */
959 CORE_ADDR pc; /* PC of this frame at the function entry point. */
960 CORE_ADDR ra; /* The raw return address of this frame. */
961 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
962 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
963 int call0; /* It's a call0 framework (else windowed). */
964 union
966 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
967 xtensa_call0_frame_cache_t c0; /* call0 == true. */
968 };
970
971
972static struct xtensa_frame_cache *
973xtensa_alloc_frame_cache (int windowed)
974{
976 int i;
977
978 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
979
981
982 cache->base = 0;
983 cache->pc = 0;
984 cache->ra = 0;
985 cache->ps = 0;
986 cache->prev_sp = 0;
987 cache->call0 = !windowed;
988 if (cache->call0)
989 {
990 cache->c0.c0_frmsz = -1;
991 cache->c0.c0_hasfp = 0;
992 cache->c0.fp_regnum = -1;
993 cache->c0.c0_fp = -1;
994 cache->c0.c0_fpalign = 0;
995 cache->c0.c0_old_sp = C0_INEXP;
996 cache->c0.c0_sp_ofs = C0_NOSTK;
997
998 for (i = 0; i < C0_NREGS; i++)
999 {
1000 cache->c0.c0_rt[i].fr_reg = i;
1001 cache->c0.c0_rt[i].fr_ofs = 0;
1002 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1003 }
1004 }
1005 else
1006 {
1007 cache->wd.wb = 0;
1008 cache->wd.ws = 0;
1009 cache->wd.callsize = -1;
1010
1011 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1012 cache->wd.aregs[i] = -1;
1013 }
1014 return cache;
1015}
1016
1017
1018static CORE_ADDR
1019xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1020{
1021 return address & ~15;
1022}
1023
1024
1025static CORE_ADDR
1026xtensa_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
1027{
1028 gdb_byte buf[8];
1029 CORE_ADDR pc;
1030
1031 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1032 host_address_to_string (next_frame.get ()));
1033
1034 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1035 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1036
1037 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1038
1039 return pc;
1040}
1041
1042
1043static struct frame_id
1044xtensa_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame)
1045{
1046 CORE_ADDR pc, fp;
1047 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1048
1049 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1050
1051 pc = get_frame_pc (this_frame);
1053 (this_frame, tdep->a0_base + 1);
1054
1055 /* Make dummy frame ID unique by adding a constant. */
1056 return frame_id_build (fp + SP_ALIGNMENT, pc);
1057}
1058
1059/* Returns true, if instruction to execute next is unique to Xtensa Window
1060 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1061
1062static int
1063xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1064{
1065 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1066 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1067 unsigned int code;
1068
1069 if (byte_order == BFD_ENDIAN_BIG)
1070 {
1071 /* Check, if this is L32E or S32E. */
1072 code = insn & 0xf000ff00;
1073 if ((code == 0x00009000) || (code == 0x00009400))
1074 return 1;
1075 /* Check, if this is RFWU or RFWO. */
1076 code = insn & 0xffffff00;
1077 return ((code == 0x00430000) || (code == 0x00530000));
1078 }
1079 else
1080 {
1081 /* Check, if this is L32E or S32E. */
1082 code = insn & 0x00ff000f;
1083 if ((code == 0x090000) || (code == 0x490000))
1084 return 1;
1085 /* Check, if this is RFWU or RFWO. */
1086 code = insn & 0x00ffffff;
1087 return ((code == 0x00003400) || (code == 0x00003500));
1088 }
1089}
1090
1091/* Returns the best guess about which register is a frame pointer
1092 for the function containing CURRENT_PC. */
1094#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1095#define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1096
1097static unsigned int
1098xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1099{
1100#define RETURN_FP goto done
1101
1102 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1103 unsigned int fp_regnum = tdep->a0_base + 1;
1104 CORE_ADDR start_addr;
1105 xtensa_isa isa;
1106 xtensa_insnbuf ins, slot;
1107 gdb_byte ibuf[XTENSA_ISA_BSZ];
1108 CORE_ADDR ia, bt, ba;
1109 xtensa_format ifmt;
1110 int ilen, islots, is;
1111 xtensa_opcode opc;
1112 const char *opcname;
1113
1114 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1115 if (start_addr == 0)
1116 return fp_regnum;
1117
1118 isa = xtensa_default_isa;
1119 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1120 ins = xtensa_insnbuf_alloc (isa);
1121 slot = xtensa_insnbuf_alloc (isa);
1122 ba = 0;
1123
1124 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1125 {
1126 if (ia + xtensa_isa_maxlength (isa) > bt)
1127 {
1128 ba = ia;
1129 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1130 ? ba + XTENSA_ISA_BSZ : current_pc;
1131 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1132 RETURN_FP;
1133 }
1134
1135 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1136 ifmt = xtensa_format_decode (isa, ins);
1137 if (ifmt == XTENSA_UNDEFINED)
1138 RETURN_FP;
1139 ilen = xtensa_format_length (isa, ifmt);
1140 if (ilen == XTENSA_UNDEFINED)
1141 RETURN_FP;
1142 islots = xtensa_format_num_slots (isa, ifmt);
1143 if (islots == XTENSA_UNDEFINED)
1144 RETURN_FP;
1145
1146 for (is = 0; is < islots; ++is)
1147 {
1148 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1149 RETURN_FP;
1150
1151 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1152 if (opc == XTENSA_UNDEFINED)
1153 RETURN_FP;
1154
1155 opcname = xtensa_opcode_name (isa, opc);
1156
1157 if (strcasecmp (opcname, "mov.n") == 0
1158 || strcasecmp (opcname, "or") == 0)
1159 {
1160 unsigned int register_operand;
1161
1162 /* Possible candidate for setting frame pointer
1163 from A1. This is what we are looking for. */
1164
1165 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1166 is, slot, &register_operand) != 0)
1167 RETURN_FP;
1168 if (xtensa_operand_decode (isa, opc, 1, &register_operand) != 0)
1169 RETURN_FP;
1170 if (register_operand == 1) /* Mov{.n} FP A1. */
1171 {
1172 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1173 &register_operand) != 0)
1174 RETURN_FP;
1175 if (xtensa_operand_decode (isa, opc, 0,
1176 &register_operand) != 0)
1177 RETURN_FP;
1178
1179 fp_regnum
1180 = tdep->a0_base + register_operand;
1181 RETURN_FP;
1182 }
1183 }
1184
1185 if (
1186 /* We have problems decoding the memory. */
1187 opcname == NULL
1188 || strcasecmp (opcname, "ill") == 0
1189 || strcasecmp (opcname, "ill.n") == 0
1190 /* Hit planted breakpoint. */
1191 || strcasecmp (opcname, "break") == 0
1192 || strcasecmp (opcname, "break.n") == 0
1193 /* Flow control instructions finish prologue. */
1194 || xtensa_opcode_is_branch (isa, opc) > 0
1195 || xtensa_opcode_is_jump (isa, opc) > 0
1196 || xtensa_opcode_is_loop (isa, opc) > 0
1197 || xtensa_opcode_is_call (isa, opc) > 0
1198 || strcasecmp (opcname, "simcall") == 0
1199 || strcasecmp (opcname, "syscall") == 0)
1200 /* Can not continue analysis. */
1201 RETURN_FP;
1202 }
1203 }
1204done:
1205 xtensa_insnbuf_free(isa, slot);
1206 xtensa_insnbuf_free(isa, ins);
1207 return fp_regnum;
1208}
1209
1210/* The key values to identify the frame using "cache" are
1211
1212 cache->base = SP (or best guess about FP) of this frame;
1213 cache->pc = entry-PC (entry point of the frame function);
1214 cache->prev_sp = SP of the previous frame. */
1215
1216static void
1218 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1219
1220static void
1222 xtensa_frame_cache_t *cache,
1223 CORE_ADDR pc);
1224
1225static struct xtensa_frame_cache *
1226xtensa_frame_cache (frame_info_ptr this_frame, void **this_cache)
1227{
1228 xtensa_frame_cache_t *cache;
1229 CORE_ADDR ra, wb, ws, pc, sp, ps;
1230 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1231 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1232 unsigned int fp_regnum;
1233 int windowed, ps_regnum;
1234
1235 if (*this_cache)
1236 return (struct xtensa_frame_cache *) *this_cache;
1237
1239 ps_regnum = gdbarch_ps_regnum (gdbarch);
1240 ps = (ps_regnum >= 0
1241 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1242
1243 windowed = windowing_enabled (gdbarch, ps);
1244
1245 /* Get pristine xtensa-frame. */
1246 cache = xtensa_alloc_frame_cache (windowed);
1247 *this_cache = cache;
1248
1249 if (windowed)
1250 {
1251 LONGEST op1;
1252 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1253
1254 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1255 wb = get_frame_register_unsigned (this_frame,
1256 tdep->wb_regnum);
1257 ws = get_frame_register_unsigned (this_frame,
1258 tdep->ws_regnum);
1259
1260 if (safe_read_memory_integer (pc, 1, byte_order, &op1)
1261 && XTENSA_IS_ENTRY (gdbarch, op1))
1262 {
1263 int callinc = CALLINC (ps);
1265 (this_frame, tdep->a0_base + callinc * 4);
1266
1267 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1268 cache->wd.callsize = 0;
1269 cache->wd.wb = wb;
1270 cache->wd.ws = ws;
1272 (this_frame, tdep->a0_base + 1);
1273
1274 /* This only can be the outermost frame since we are
1275 just about to execute ENTRY. SP hasn't been set yet.
1276 We can assume any frame size, because it does not
1277 matter, and, let's fake frame base in cache. */
1278 cache->base = cache->prev_sp - 16;
1279
1280 cache->pc = pc;
1281 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1282 cache->ps = (ps & ~PS_CALLINC_MASK)
1283 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1284
1285 return cache;
1286 }
1287 else
1288 {
1290 ra = get_frame_register_unsigned (this_frame,
1291 tdep->a0_base);
1292 cache->wd.callsize = WINSIZE (ra);
1293 cache->wd.wb = (wb - cache->wd.callsize / 4)
1294 & (tdep->num_aregs / 4 - 1);
1295 cache->wd.ws = ws & ~(1 << wb);
1296
1297 cache->pc = get_frame_func (this_frame);
1298 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1299 cache->ps = (ps & ~PS_CALLINC_MASK)
1300 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1301 }
1302
1303 if (cache->wd.ws == 0)
1304 {
1305 int i;
1306
1307 /* Set A0...A3. */
1309 (this_frame, tdep->a0_base + 1) - 16;
1310
1311 for (i = 0; i < 4; i++, sp += 4)
1312 {
1313 cache->wd.aregs[i] = sp;
1314 }
1315
1316 if (cache->wd.callsize > 4)
1317 {
1318 /* Set A4...A7/A11. */
1319 /* Get the SP of the frame previous to the previous one.
1320 To achieve this, we have to dereference SP twice. */
1321 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1322 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1323 sp -= cache->wd.callsize * 4;
1324
1325 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1326 {
1327 cache->wd.aregs[i] = sp;
1328 }
1329 }
1330 }
1331
1332 if ((cache->prev_sp == 0) && ( ra != 0 ))
1333 /* If RA is equal to 0 this frame is an outermost frame. Leave
1334 cache->prev_sp unchanged marking the boundary of the frame stack. */
1335 {
1336 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1337 {
1338 /* Register window overflow already happened.
1339 We can read caller's SP from the proper spill location. */
1341 (this_frame, tdep->a0_base + 1);
1342 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1343 }
1344 else
1345 {
1346 /* Read caller's frame SP directly from the previous window. */
1347 int regnum = arreg_number
1348 (gdbarch, tdep->a0_base + 1,
1349 cache->wd.wb);
1350
1352 }
1353 }
1354 }
1356 {
1357 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1358
1359 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1360 /* Everything was set already, including cache->base. */
1361 return cache;
1362 }
1363 else /* Call0 framework. */
1364 {
1365 call0_frame_cache (this_frame, cache, pc);
1366 fp_regnum = cache->c0.fp_regnum;
1367 }
1368
1369 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1370
1371 return cache;
1372}
1374static int xtensa_session_once_reported = 1;
1375
1376/* Report a problem with prologue analysis while doing backtracing.
1377 But, do it only once to avoid annoying repeated messages. */
1378
1379static void
1380warning_once (void)
1381{
1383 warning (_("\
1384\nUnrecognised function prologue. Stack trace cannot be resolved. \
1385This message will not be repeated in this session.\n"));
1386
1388}
1389
1390
1391static void
1393 void **this_cache,
1394 struct frame_id *this_id)
1395{
1396 struct xtensa_frame_cache *cache =
1397 xtensa_frame_cache (this_frame, this_cache);
1398
1399 if (cache->prev_sp == 0)
1400 return;
1401
1402 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1403}
1404
1405static struct value *
1407 void **this_cache,
1408 int regnum)
1409{
1410 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1411 struct xtensa_frame_cache *cache;
1412 ULONGEST saved_reg = 0;
1413 int done = 1;
1414 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1415
1416 if (*this_cache == NULL)
1417 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1418 cache = (struct xtensa_frame_cache *) *this_cache;
1419
1421 saved_reg = cache->ra;
1422 else if (regnum == tdep->a0_base + 1)
1423 saved_reg = cache->prev_sp;
1424 else if (!cache->call0)
1425 {
1426 if (regnum == tdep->ws_regnum)
1427 saved_reg = cache->wd.ws;
1428 else if (regnum == tdep->wb_regnum)
1429 saved_reg = cache->wd.wb;
1430 else if (regnum == gdbarch_ps_regnum (gdbarch))
1431 saved_reg = cache->ps;
1432 else
1433 done = 0;
1434 }
1435 else
1436 done = 0;
1437
1438 if (done)
1439 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1440
1441 if (!cache->call0) /* Windowed ABI. */
1442 {
1443 /* Convert A-register numbers to AR-register numbers,
1444 if we deal with A-register. */
1445 if (regnum >= tdep->a0_base
1446 && regnum <= tdep->a0_base + 15)
1447 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1448
1449 /* Check, if we deal with AR-register saved on stack. */
1450 if (regnum >= tdep->ar_base
1451 && regnum <= (tdep->ar_base
1452 + tdep->num_aregs))
1453 {
1454 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1455
1456 if (areg >= 0
1457 && areg < XTENSA_NUM_SAVED_AREGS
1458 && cache->wd.aregs[areg] != -1)
1459 return frame_unwind_got_memory (this_frame, regnum,
1460 cache->wd.aregs[areg]);
1461 }
1462 }
1463 else /* Call0 ABI. */
1464 {
1465 int reg = (regnum >= tdep->ar_base
1466 && regnum <= (tdep->ar_base
1467 + C0_NREGS))
1468 ? regnum - tdep->ar_base : regnum;
1469
1470 if (reg < C0_NREGS)
1471 {
1472 CORE_ADDR spe;
1473 int stkofs;
1474
1475 /* If register was saved in the prologue, retrieve it. */
1476 stkofs = cache->c0.c0_rt[reg].to_stk;
1477 if (stkofs != C0_NOSTK)
1478 {
1479 /* Determine SP on entry based on FP. */
1480 spe = cache->c0.c0_fp
1481 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1482
1483 return frame_unwind_got_memory (this_frame, regnum,
1484 spe + stkofs);
1485 }
1486 }
1487 }
1488
1489 /* All other registers have been either saved to
1490 the stack or are still alive in the processor. */
1491
1492 return frame_unwind_got_register (this_frame, regnum, regnum);
1493}
1494
1495
1496static const struct frame_unwind
1498{
1499 "xtensa prologue",
1504 NULL,
1506};
1507
1508static CORE_ADDR
1509xtensa_frame_base_address (frame_info_ptr this_frame, void **this_cache)
1510{
1511 struct xtensa_frame_cache *cache =
1512 xtensa_frame_cache (this_frame, this_cache);
1513
1514 return cache->base;
1515}
1516
1517static const struct frame_base
1519{
1524};
1525
1526
1527static void
1529 struct regcache *regcache,
1530 void *dst)
1531{
1532 struct gdbarch *gdbarch = regcache->arch ();
1533 bfd_byte *valbuf = (bfd_byte *) dst;
1534 int len = type->length ();
1535 ULONGEST pc, wb;
1536 int callsize, areg;
1537 int offset = 0;
1538
1539 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1540
1541 gdb_assert(len > 0);
1542
1543 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1544 if (tdep->call_abi != CallAbiCall0Only)
1545 {
1546 /* First, we have to find the caller window in the register file. */
1548 callsize = extract_call_winsize (gdbarch, pc);
1549
1550 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1551 if (len > (callsize > 8 ? 8 : 16))
1552 internal_error (_("cannot extract return value of %d bytes long"),
1553 len);
1554
1555 /* Get the register offset of the return
1556 register (A2) in the caller window. */
1558 (regcache, tdep->wb_regnum, &wb);
1559 areg = arreg_number (gdbarch,
1560 tdep->a0_base + 2 + callsize, wb);
1561 }
1562 else
1563 {
1564 /* No windowing hardware - Call0 ABI. */
1565 areg = tdep->a0_base + C0_ARGS;
1566 }
1567
1568 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1569
1570 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1571 offset = 4 - len;
1572
1573 for (; len > 0; len -= 4, areg++, valbuf += 4)
1574 {
1575 if (len < 4)
1576 regcache->raw_read_part (areg, offset, len, valbuf);
1577 else
1578 regcache->raw_read (areg, valbuf);
1579 }
1580}
1581
1582
1583static void
1585 struct regcache *regcache,
1586 const void *dst)
1587{
1588 struct gdbarch *gdbarch = regcache->arch ();
1589 const bfd_byte *valbuf = (const bfd_byte *) dst;
1590 unsigned int areg;
1591 ULONGEST pc, wb;
1592 int callsize;
1593 int len = type->length ();
1594 int offset = 0;
1595
1596 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1597
1598 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1599 if (tdep->call_abi != CallAbiCall0Only)
1600 {
1602 (regcache, tdep->wb_regnum, &wb);
1604 callsize = extract_call_winsize (gdbarch, pc);
1605
1606 if (len > (callsize > 8 ? 8 : 16))
1607 internal_error (_("unimplemented for this length: %s"),
1608 pulongest (type->length ()));
1609 areg = arreg_number (gdbarch,
1610 tdep->a0_base + 2 + callsize, wb);
1611
1612 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1613 callsize, (int) wb);
1614 }
1615 else
1616 {
1617 areg = tdep->a0_base + C0_ARGS;
1618 }
1619
1620 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1621 offset = 4 - len;
1622
1623 for (; len > 0; len -= 4, areg++, valbuf += 4)
1624 {
1625 if (len < 4)
1626 regcache->raw_write_part (areg, offset, len, valbuf);
1627 else
1628 regcache->raw_write (areg, valbuf);
1629 }
1630}
1631
1632
1635 struct value *function,
1636 struct type *valtype,
1637 struct regcache *regcache,
1638 gdb_byte *readbuf,
1639 const gdb_byte *writebuf)
1640{
1641 /* Structures up to 16 bytes are returned in registers. */
1642
1643 int struct_return = ((valtype->code () == TYPE_CODE_STRUCT
1644 || valtype->code () == TYPE_CODE_UNION
1645 || valtype->code () == TYPE_CODE_ARRAY)
1646 && valtype->length () > 16);
1647
1648 if (struct_return)
1650
1651 DEBUGTRACE ("xtensa_return_value(...)\n");
1652
1653 if (writebuf != NULL)
1654 {
1655 xtensa_store_return_value (valtype, regcache, writebuf);
1656 }
1657
1658 if (readbuf != NULL)
1659 {
1660 gdb_assert (!struct_return);
1661 xtensa_extract_return_value (valtype, regcache, readbuf);
1662 }
1664}
1665
1666
1667/* DUMMY FRAME */
1668
1669static CORE_ADDR
1671 struct value *function,
1672 struct regcache *regcache,
1673 CORE_ADDR bp_addr,
1674 int nargs,
1675 struct value **args,
1676 CORE_ADDR sp,
1677 function_call_return_method return_method,
1678 CORE_ADDR struct_addr)
1679{
1680 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1681 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1682 int size, onstack_size;
1683 gdb_byte *buf = (gdb_byte *) alloca (16);
1684 CORE_ADDR ra, ps;
1685 struct argument_info
1686 {
1687 const bfd_byte *contents;
1688 int length;
1689 int onstack; /* onstack == 0 => in reg */
1690 int align; /* alignment */
1691 union
1692 {
1693 int offset; /* stack offset if on stack. */
1694 int regno; /* regno if in register. */
1695 } u;
1696 };
1697
1698 struct argument_info *arg_info =
1699 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1700
1701 CORE_ADDR osp = sp;
1702
1703 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1704
1705 if (xtensa_debug_level > 3)
1706 {
1707 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1708 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1709 "struct_addr=0x%x\n",
1710 (int) sp, (int) return_method, (int) struct_addr);
1711
1712 for (int i = 0; i < nargs; i++)
1713 {
1714 struct value *arg = args[i];
1715 struct type *arg_type = check_typedef (value_type (arg));
1716 gdb_printf (gdb_stdlog, "%2d: %s %3s ", i,
1717 host_address_to_string (arg),
1718 pulongest (arg_type->length ()));
1719 switch (arg_type->code ())
1720 {
1721 case TYPE_CODE_INT:
1722 gdb_printf (gdb_stdlog, "int");
1723 break;
1724 case TYPE_CODE_STRUCT:
1725 gdb_printf (gdb_stdlog, "struct");
1726 break;
1727 default:
1728 gdb_printf (gdb_stdlog, "%3d", arg_type->code ());
1729 break;
1730 }
1731 gdb_printf (gdb_stdlog, " %s\n",
1732 host_address_to_string (value_contents (arg).data ()));
1733 }
1734 }
1735
1736 /* First loop: collect information.
1737 Cast into type_long. (This shouldn't happen often for C because
1738 GDB already does this earlier.) It's possible that GDB could
1739 do it all the time but it's harmless to leave this code here. */
1740
1741 size = 0;
1742 onstack_size = 0;
1743
1744 if (return_method == return_method_struct)
1746
1747 for (int i = 0; i < nargs; i++)
1748 {
1749 struct argument_info *info = &arg_info[i];
1750 struct value *arg = args[i];
1751 struct type *arg_type = check_typedef (value_type (arg));
1752
1753 switch (arg_type->code ())
1754 {
1755 case TYPE_CODE_INT:
1756 case TYPE_CODE_BOOL:
1757 case TYPE_CODE_CHAR:
1758 case TYPE_CODE_RANGE:
1759 case TYPE_CODE_ENUM:
1760
1761 /* Cast argument to long if necessary as the mask does it too. */
1762 if (arg_type->length ()
1763 < builtin_type (gdbarch)->builtin_long->length ())
1764 {
1765 arg_type = builtin_type (gdbarch)->builtin_long;
1766 arg = value_cast (arg_type, arg);
1767 }
1768 /* Aligment is equal to the type length for the basic types. */
1769 info->align = arg_type->length ();
1770 break;
1771
1772 case TYPE_CODE_FLT:
1773
1774 /* Align doubles correctly. */
1775 if (arg_type->length ()
1776 == builtin_type (gdbarch)->builtin_double->length ())
1777 info->align = builtin_type (gdbarch)->builtin_double->length ();
1778 else
1779 info->align = builtin_type (gdbarch)->builtin_long->length ();
1780 break;
1781
1782 case TYPE_CODE_STRUCT:
1783 default:
1784 info->align = builtin_type (gdbarch)->builtin_long->length ();
1785 break;
1786 }
1787 info->length = arg_type->length ();
1788 info->contents = value_contents (arg).data ();
1789
1790 /* Align size and onstack_size. */
1791 size = (size + info->align - 1) & ~(info->align - 1);
1792 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1793
1794 if (size + info->length > REGISTER_SIZE * ARG_NOF (tdep))
1795 {
1796 info->onstack = 1;
1797 info->u.offset = onstack_size;
1798 onstack_size += info->length;
1799 }
1800 else
1801 {
1802 info->onstack = 0;
1803 info->u.regno = ARG_1ST (tdep) + size / REGISTER_SIZE;
1804 }
1805 size += info->length;
1806 }
1807
1808 /* Adjust the stack pointer and align it. */
1809 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1810
1811 /* Simulate MOVSP, if Windowed ABI. */
1812 if ((tdep->call_abi != CallAbiCall0Only)
1813 && (sp != osp))
1814 {
1815 read_memory (osp - 16, buf, 16);
1816 write_memory (sp - 16, buf, 16);
1817 }
1818
1819 /* Second Loop: Load arguments. */
1820
1821 if (return_method == return_method_struct)
1822 {
1823 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1824 regcache->cooked_write (ARG_1ST (tdep), buf);
1825 }
1826
1827 for (int i = 0; i < nargs; i++)
1828 {
1829 struct argument_info *info = &arg_info[i];
1830
1831 if (info->onstack)
1832 {
1833 int n = info->length;
1834 CORE_ADDR offset = sp + info->u.offset;
1835
1836 /* Odd-sized structs are aligned to the lower side of a memory
1837 word in big-endian mode and require a shift. This only
1838 applies for structures smaller than one word. */
1839
1840 if (n < REGISTER_SIZE
1841 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1842 offset += (REGISTER_SIZE - n);
1843
1844 write_memory (offset, info->contents, info->length);
1845
1846 }
1847 else
1848 {
1849 int n = info->length;
1850 const bfd_byte *cp = info->contents;
1851 int r = info->u.regno;
1852
1853 /* Odd-sized structs are aligned to the lower side of registers in
1854 big-endian mode and require a shift. The odd-sized leftover will
1855 be at the end. Note that this is only true for structures smaller
1856 than REGISTER_SIZE; for larger odd-sized structures the excess
1857 will be left-aligned in the register on both endiannesses. */
1858
1859 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1860 {
1861 ULONGEST v;
1862 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1863 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1864
1865 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1866 regcache->cooked_write (r, buf);
1867
1868 cp += REGISTER_SIZE;
1869 n -= REGISTER_SIZE;
1870 r++;
1871 }
1872 else
1873 while (n > 0)
1874 {
1875 regcache->cooked_write (r, cp);
1876
1877 cp += REGISTER_SIZE;
1878 n -= REGISTER_SIZE;
1879 r++;
1880 }
1881 }
1882 }
1883
1884 /* Set the return address of dummy frame to the dummy address.
1885 The return address for the current function (in A0) is
1886 saved in the dummy frame, so we can safely overwrite A0 here. */
1887
1888 if (tdep->call_abi != CallAbiCall0Only)
1889 {
1890 ULONGEST val;
1891
1892 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1894 ps = (unsigned long) val & ~0x00030000;
1896 (regcache, tdep->a0_base + 4, ra);
1899 ps | 0x00010000);
1900
1901 /* All the registers have been saved. After executing
1902 dummy call, they all will be restored. So it's safe
1903 to modify WINDOWSTART register to make it look like there
1904 is only one register window corresponding to WINDOWEBASE. */
1905
1906 regcache->raw_read (tdep->wb_regnum, buf);
1908 (regcache, tdep->ws_regnum,
1909 1 << extract_unsigned_integer (buf, 4, byte_order));
1910 }
1911 else
1912 {
1913 /* Simulate CALL0: write RA into A0 register. */
1915 (regcache, tdep->a0_base, bp_addr);
1916 }
1917
1918 /* Set new stack pointer and return it. */
1920 tdep->a0_base + 1, sp);
1921 /* Make dummy frame ID unique by adding a constant. */
1922 return sp + SP_ALIGNMENT;
1923}
1924
1925/* Implement the breakpoint_kind_from_pc gdbarch method. */
1926
1927static int
1928xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1929{
1930 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1931
1933 return 2;
1934 else
1935 return 4;
1936}
1937
1938/* Return a breakpoint for the current location of PC. We always use
1939 the density version if we have density instructions (regardless of the
1940 current instruction at PC), and use regular instructions otherwise. */
1942#define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1943#define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1944#define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1945#define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1946
1947/* Implement the sw_breakpoint_from_kind gdbarch method. */
1948
1949static const gdb_byte *
1950xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1951{
1952 *size = kind;
1953
1954 if (kind == 4)
1955 {
1956 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1957 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1958
1959 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1960 return big_breakpoint;
1961 else
1962 return little_breakpoint;
1963 }
1964 else
1965 {
1966 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1967 static unsigned char density_little_breakpoint[]
1969
1970 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1971 return density_big_breakpoint;
1972 else
1973 return density_little_breakpoint;
1974 }
1975}
1976
1977/* Call0 ABI support routines. */
1978
1979/* Return true, if PC points to "ret" or "ret.n". */
1980
1981static int
1982call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
1983{
1984#define RETURN_RET goto done
1985 xtensa_isa isa;
1986 xtensa_insnbuf ins, slot;
1987 gdb_byte ibuf[XTENSA_ISA_BSZ];
1988 CORE_ADDR ia, bt, ba;
1989 xtensa_format ifmt;
1990 int ilen, islots, is;
1991 xtensa_opcode opc;
1992 const char *opcname;
1993 int found_ret = 0;
1994
1995 isa = xtensa_default_isa;
1996 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1997 ins = xtensa_insnbuf_alloc (isa);
1998 slot = xtensa_insnbuf_alloc (isa);
1999 ba = 0;
2000
2001 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2002 {
2003 if (ia + xtensa_isa_maxlength (isa) > bt)
2004 {
2005 ba = ia;
2006 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2007 ? ba + XTENSA_ISA_BSZ : finish_pc;
2008 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2009 RETURN_RET;
2010 }
2011
2012 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2013 ifmt = xtensa_format_decode (isa, ins);
2014 if (ifmt == XTENSA_UNDEFINED)
2015 RETURN_RET;
2016 ilen = xtensa_format_length (isa, ifmt);
2017 if (ilen == XTENSA_UNDEFINED)
2018 RETURN_RET;
2019 islots = xtensa_format_num_slots (isa, ifmt);
2020 if (islots == XTENSA_UNDEFINED)
2021 RETURN_RET;
2022
2023 for (is = 0; is < islots; ++is)
2024 {
2025 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2026 RETURN_RET;
2027
2028 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2029 if (opc == XTENSA_UNDEFINED)
2030 RETURN_RET;
2031
2032 opcname = xtensa_opcode_name (isa, opc);
2033
2034 if ((strcasecmp (opcname, "ret.n") == 0)
2035 || (strcasecmp (opcname, "ret") == 0))
2036 {
2037 found_ret = 1;
2038 RETURN_RET;
2039 }
2040 }
2041 }
2042 done:
2043 xtensa_insnbuf_free(isa, slot);
2044 xtensa_insnbuf_free(isa, ins);
2045 return found_ret;
2046}
2047
2048/* Call0 opcode class. Opcodes are preclassified according to what they
2049 mean for Call0 prologue analysis, and their number of significant operands.
2050 The purpose of this is to simplify prologue analysis by separating
2051 instruction decoding (libisa) from the semantics of prologue analysis. */
2055 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2056 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2057 c0opc_flow, /* Flow control insn. */
2058 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2059 c0opc_break, /* Debugger software breakpoints. */
2060 c0opc_add, /* Adding two registers. */
2061 c0opc_addi, /* Adding a register and an immediate. */
2062 c0opc_and, /* Bitwise "and"-ing two registers. */
2063 c0opc_sub, /* Subtracting a register from a register. */
2064 c0opc_mov, /* Moving a register to a register. */
2065 c0opc_movi, /* Moving an immediate to a register. */
2066 c0opc_l32r, /* Loading a literal. */
2067 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2068 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2069 c0opc_l32e, /* L32E instruction. */
2070 c0opc_s32e, /* S32E instruction. */
2071 c0opc_rfwo, /* RFWO instruction. */
2072 c0opc_rfwu, /* RFWU instruction. */
2073 c0opc_NrOf /* Number of opcode classifications. */
2074};
2075
2076/* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2077
2078static int
2079rwx_special_register (const char *opcname)
2080{
2081 char ch = *opcname++;
2082
2083 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2084 return 0;
2085 if (*opcname++ != 's')
2086 return 0;
2087 if (*opcname++ != 'r')
2088 return 0;
2089 if (*opcname++ != '.')
2090 return 0;
2091
2092 return 1;
2093}
2094
2095/* Classify an opcode based on what it means for Call0 prologue analysis. */
2096
2098call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2099{
2100 const char *opcname;
2102
2103 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2104
2105 /* Get opcode name and handle special classifications. */
2106
2107 opcname = xtensa_opcode_name (isa, opc);
2108
2109 if (opcname == NULL
2110 || strcasecmp (opcname, "ill") == 0
2111 || strcasecmp (opcname, "ill.n") == 0)
2112 opclass = c0opc_illegal;
2113 else if (strcasecmp (opcname, "break") == 0
2114 || strcasecmp (opcname, "break.n") == 0)
2115 opclass = c0opc_break;
2116 else if (strcasecmp (opcname, "entry") == 0)
2117 opclass = c0opc_entry;
2118 else if (strcasecmp (opcname, "rfwo") == 0)
2119 opclass = c0opc_rfwo;
2120 else if (strcasecmp (opcname, "rfwu") == 0)
2121 opclass = c0opc_rfwu;
2122 else if (xtensa_opcode_is_branch (isa, opc) > 0
2123 || xtensa_opcode_is_jump (isa, opc) > 0
2124 || xtensa_opcode_is_loop (isa, opc) > 0
2125 || xtensa_opcode_is_call (isa, opc) > 0
2126 || strcasecmp (opcname, "simcall") == 0
2127 || strcasecmp (opcname, "syscall") == 0)
2128 opclass = c0opc_flow;
2129
2130 /* Also, classify specific opcodes that need to be tracked. */
2131 else if (strcasecmp (opcname, "add") == 0
2132 || strcasecmp (opcname, "add.n") == 0)
2133 opclass = c0opc_add;
2134 else if (strcasecmp (opcname, "and") == 0)
2135 opclass = c0opc_and;
2136 else if (strcasecmp (opcname, "addi") == 0
2137 || strcasecmp (opcname, "addi.n") == 0
2138 || strcasecmp (opcname, "addmi") == 0)
2139 opclass = c0opc_addi;
2140 else if (strcasecmp (opcname, "sub") == 0)
2141 opclass = c0opc_sub;
2142 else if (strcasecmp (opcname, "mov.n") == 0
2143 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2144 opclass = c0opc_mov;
2145 else if (strcasecmp (opcname, "movi") == 0
2146 || strcasecmp (opcname, "movi.n") == 0)
2147 opclass = c0opc_movi;
2148 else if (strcasecmp (opcname, "l32r") == 0)
2149 opclass = c0opc_l32r;
2150 else if (strcasecmp (opcname, "s32i") == 0
2151 || strcasecmp (opcname, "s32i.n") == 0)
2152 opclass = c0opc_s32i;
2153 else if (strcasecmp (opcname, "l32e") == 0)
2154 opclass = c0opc_l32e;
2155 else if (strcasecmp (opcname, "s32e") == 0)
2156 opclass = c0opc_s32e;
2157 else if (rwx_special_register (opcname))
2158 opclass = c0opc_rwxsr;
2159
2160 return opclass;
2161}
2162
2163/* Tracks register movement/mutation for a given operation, which may
2164 be within a bundle. Updates the destination register tracking info
2165 accordingly. The pc is needed only for pc-relative load instructions
2166 (eg. l32r). The SP register number is needed to identify stores to
2167 the stack frame. Returns 0, if analysis was successful, non-zero
2168 otherwise. */
2169
2170static int
2172 xtensa_insn_kind opclass, int nods, unsigned odv[],
2173 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2174{
2175 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2176 unsigned litbase, litaddr, litval;
2177 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2178
2179 switch (opclass)
2180 {
2181 case c0opc_addi:
2182 /* 3 operands: dst, src, imm. */
2183 gdb_assert (nods == 3);
2184 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2185 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2186 break;
2187 case c0opc_add:
2188 /* 3 operands: dst, src1, src2. */
2189 gdb_assert (nods == 3);
2190 if (src[odv[1]].fr_reg == C0_CONST)
2191 {
2192 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2193 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2194 }
2195 else if (src[odv[2]].fr_reg == C0_CONST)
2196 {
2197 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2198 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2199 }
2200 else dst[odv[0]].fr_reg = C0_INEXP;
2201 break;
2202 case c0opc_and:
2203 /* 3 operands: dst, src1, src2. */
2204 gdb_assert (nods == 3);
2205 if (cache->c0.c0_fpalign == 0)
2206 {
2207 /* Handle dynamic stack alignment. */
2208 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2209 {
2210 if (src[odv[2]].fr_reg == C0_CONST)
2211 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2212 break;
2213 }
2214 else if ((src[odv[0]].fr_reg == spreg)
2215 && (src[odv[2]].fr_reg == spreg))
2216 {
2217 if (src[odv[1]].fr_reg == C0_CONST)
2218 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2219 break;
2220 }
2221 /* else fall through. */
2222 }
2223 if (src[odv[1]].fr_reg == C0_CONST)
2224 {
2225 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2226 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2227 }
2228 else if (src[odv[2]].fr_reg == C0_CONST)
2229 {
2230 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2231 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2232 }
2233 else dst[odv[0]].fr_reg = C0_INEXP;
2234 break;
2235 case c0opc_sub:
2236 /* 3 operands: dst, src1, src2. */
2237 gdb_assert (nods == 3);
2238 if (src[odv[2]].fr_reg == C0_CONST)
2239 {
2240 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2241 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2242 }
2243 else dst[odv[0]].fr_reg = C0_INEXP;
2244 break;
2245 case c0opc_mov:
2246 /* 2 operands: dst, src [, src]. */
2247 gdb_assert (nods == 2);
2248 /* First, check if it's a special case of saving unaligned SP
2249 to a spare register in case of dynamic stack adjustment.
2250 But, only do it one time. The second time could be initializing
2251 frame pointer. We don't want to overwrite the first one. */
2252 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2253 cache->c0.c0_old_sp = odv[0];
2254
2255 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2256 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2257 break;
2258 case c0opc_movi:
2259 /* 2 operands: dst, imm. */
2260 gdb_assert (nods == 2);
2261 dst[odv[0]].fr_reg = C0_CONST;
2262 dst[odv[0]].fr_ofs = odv[1];
2263 break;
2264 case c0opc_l32r:
2265 /* 2 operands: dst, literal offset. */
2266 gdb_assert (nods == 2);
2267 /* litbase = xtensa_get_litbase (pc); can be also used. */
2268 litbase = (tdep->litbase_regnum == -1)
2270 (tdep->litbase_regnum);
2271 litaddr = litbase & 1
2272 ? (litbase & ~1) + (signed)odv[1]
2273 : (pc + 3 + (signed)odv[1]) & ~3;
2274 litval = read_memory_integer (litaddr, 4, byte_order);
2275 dst[odv[0]].fr_reg = C0_CONST;
2276 dst[odv[0]].fr_ofs = litval;
2277 break;
2278 case c0opc_s32i:
2279 /* 3 operands: value, base, offset. */
2280 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2281 /* First, check if it's a spill for saved unaligned SP,
2282 when dynamic stack adjustment was applied to this frame. */
2283 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2284 && (odv[1] == spreg) /* SP usage indicates spill. */
2285 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2286 cache->c0.c0_sp_ofs = odv[2];
2287
2288 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2289 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2290 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2291 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2292 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2293 {
2294 /* ISA encoding guarantees alignment. But, check it anyway. */
2295 gdb_assert ((odv[2] & 3) == 0);
2296 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2297 }
2298 break;
2299 /* If we end up inside Window Overflow / Underflow interrupt handler
2300 report an error because these handlers should have been handled
2301 already in a different way. */
2302 case c0opc_l32e:
2303 case c0opc_s32e:
2304 case c0opc_rfwo:
2305 case c0opc_rfwu:
2306 return 1;
2307 default:
2308 return 1;
2309 }
2310 return 0;
2311}
2312
2313/* Analyze prologue of the function at start address to determine if it uses
2314 the Call0 ABI, and if so track register moves and linear modifications
2315 in the prologue up to the PC or just beyond the prologue, whichever is
2316 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2317 prologue. The prologue may overlap non-prologue instructions but is
2318 guaranteed to end by the first flow-control instruction (jump, branch,
2319 call or return). Since an optimized function may move information around
2320 and change the stack frame arbitrarily during the prologue, the information
2321 is guaranteed valid only at the point in the function indicated by the PC.
2322 May be used to skip the prologue or identify the ABI, w/o tracking.
2323
2324 Returns: Address of first instruction after prologue, or PC (whichever
2325 is first), or 0, if decoding failed (in libisa).
2326 Input args:
2327 start Start address of function/prologue.
2328 pc Program counter to stop at. Use 0 to continue to end of prologue.
2329 If 0, avoids infinite run-on in corrupt code memory by bounding
2330 the scan to the end of the function if that can be determined.
2331 nregs Number of general registers to track.
2332 InOut args:
2333 cache Xtensa frame cache.
2334
2335 Note that these may produce useful results even if decoding fails
2336 because they begin with default assumptions that analysis may change. */
2337
2338static CORE_ADDR
2340 CORE_ADDR start, CORE_ADDR pc,
2341 int nregs, xtensa_frame_cache_t *cache)
2342{
2343 CORE_ADDR ia; /* Current insn address in prologue. */
2344 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2345 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2346 gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2347 xtensa_isa isa; /* libisa ISA handle. */
2348 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2349 xtensa_format ifmt; /* libisa instruction format. */
2350 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2351 xtensa_opcode opc; /* Opcode in current slot. */
2352 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2353 int nods; /* Opcode number of operands. */
2354 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2355 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2356 int j; /* General loop counter. */
2357 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2358 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2359 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2360
2361 struct symtab_and_line prologue_sal;
2362
2363 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2364 (int)start, (int)pc);
2365
2366 /* Try to limit the scan to the end of the function if a non-zero pc
2367 arg was not supplied to avoid probing beyond the end of valid memory.
2368 If memory is full of garbage that classifies as c0opc_uninteresting.
2369 If this fails (eg. if no symbols) pc ends up 0 as it was.
2370 Initialize the Call0 frame and register tracking info.
2371 Assume it's Call0 until an 'entry' instruction is encountered.
2372 Assume we may be in the prologue until we hit a flow control instr. */
2373
2374 rtmp = NULL;
2375 body_pc = UINT_MAX;
2376 end_pc = 0;
2377
2378 /* Find out, if we have an information about the prologue from DWARF. */
2379 prologue_sal = find_pc_line (start, 0);
2380 if (prologue_sal.line != 0) /* Found debug info. */
2381 body_pc = prologue_sal.end;
2382
2383 /* If we are going to analyze the prologue in general without knowing about
2384 the current PC, make the best assumption for the end of the prologue. */
2385 if (pc == 0)
2386 {
2387 find_pc_partial_function (start, 0, NULL, &end_pc);
2388 body_pc = std::min (end_pc, body_pc);
2389 }
2390 else
2391 body_pc = std::min (pc, body_pc);
2392
2393 cache->call0 = 1;
2394 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2395
2396 isa = xtensa_default_isa;
2397 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2398 ins = xtensa_insnbuf_alloc (isa);
2399 slot = xtensa_insnbuf_alloc (isa);
2400
2401 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2402 {
2403 /* (Re)fill instruction buffer from memory if necessary, but do not
2404 read memory beyond PC to be sure we stay within text section
2405 (this protection only works if a non-zero pc is supplied). */
2406
2407 if (ia + xtensa_isa_maxlength (isa) > bt)
2408 {
2409 ba = ia;
2410 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2411 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2412 error (_("Unable to read target memory ..."));
2413 }
2414
2415 /* Decode format information. */
2416
2417 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2418 ifmt = xtensa_format_decode (isa, ins);
2419 if (ifmt == XTENSA_UNDEFINED)
2420 {
2421 fail = 1;
2422 goto done;
2423 }
2424 ilen = xtensa_format_length (isa, ifmt);
2425 if (ilen == XTENSA_UNDEFINED)
2426 {
2427 fail = 1;
2428 goto done;
2429 }
2430 islots = xtensa_format_num_slots (isa, ifmt);
2431 if (islots == XTENSA_UNDEFINED)
2432 {
2433 fail = 1;
2434 goto done;
2435 }
2436
2437 /* Analyze a bundle or a single instruction, using a snapshot of
2438 the register tracking info as input for the entire bundle so that
2439 register changes do not take effect within this bundle. */
2440
2441 for (j = 0; j < nregs; ++j)
2442 rtmp[j] = cache->c0.c0_rt[j];
2443
2444 for (is = 0; is < islots; ++is)
2445 {
2446 /* Decode a slot and classify the opcode. */
2447
2448 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2449 if (fail)
2450 goto done;
2451
2452 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2453 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2454 (unsigned)ia, opc);
2455 if (opc == XTENSA_UNDEFINED)
2456 opclass = c0opc_illegal;
2457 else
2458 opclass = call0_classify_opcode (isa, opc);
2459
2460 /* Decide whether to track this opcode, ignore it, or bail out. */
2461
2462 switch (opclass)
2463 {
2464 case c0opc_illegal:
2465 case c0opc_break:
2466 fail = 1;
2467 goto done;
2468
2470 continue;
2471
2472 case c0opc_flow: /* Flow control instructions stop analysis. */
2473 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2474 goto done;
2475
2476 case c0opc_entry:
2477 cache->call0 = 0;
2478 ia += ilen; /* Skip over 'entry' insn. */
2479 goto done;
2480
2481 default:
2482 cache->call0 = 1;
2483 }
2484
2485 /* Only expected opcodes should get this far. */
2486
2487 /* Extract and decode the operands. */
2488 nods = xtensa_opcode_num_operands (isa, opc);
2489 if (nods == XTENSA_UNDEFINED)
2490 {
2491 fail = 1;
2492 goto done;
2493 }
2494
2495 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2496 {
2497 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2498 is, slot, &odv[j]);
2499 if (fail)
2500 goto done;
2501
2502 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2503 if (fail)
2504 goto done;
2505 }
2506
2507 /* Check operands to verify use of 'mov' assembler macro. */
2508 if (opclass == c0opc_mov && nods == 3)
2509 {
2510 if (odv[2] == odv[1])
2511 {
2512 nods = 2;
2513 if ((odv[0] == 1) && (odv[1] != 1))
2514 /* OR A1, An, An , where n != 1.
2515 This means we are inside epilogue already. */
2516 goto done;
2517 }
2518 else
2519 {
2520 opclass = c0opc_uninteresting;
2521 continue;
2522 }
2523 }
2524
2525 /* Track register movement and modification for this operation. */
2526 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2527 opclass, nods, odv, ia, 1, cache);
2528 if (fail)
2529 goto done;
2530 }
2531 }
2532done:
2533 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2534 (unsigned)ia, fail ? "failed" : "succeeded");
2535 xtensa_insnbuf_free(isa, slot);
2536 xtensa_insnbuf_free(isa, ins);
2537 return fail ? XTENSA_ISA_BADPC : ia;
2538}
2539
2540/* Initialize frame cache for the current frame in CALL0 ABI. */
2541
2542static void
2544 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2545{
2546 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2547 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2548 CORE_ADDR start_pc; /* The beginning of the function. */
2549 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2550 CORE_ADDR sp, fp, ra;
2551 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2552 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2553
2555 (this_frame, tdep->a0_base + 1);
2556 fp = sp; /* Assume FP == SP until proven otherwise. */
2557
2558 /* Find the beginning of the prologue of the function containing the PC
2559 and analyze it up to the PC or the end of the prologue. */
2560
2561 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2562 {
2563 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2564
2565 if (body_pc == XTENSA_ISA_BADPC)
2566 {
2567 warning_once ();
2568 ra = 0;
2569 goto finish_frame_analysis;
2570 }
2571 }
2572
2573 /* Get the frame information and FP (if used) at the current PC.
2574 If PC is in the prologue, the prologue analysis is more reliable
2575 than DWARF info. We don't not know for sure, if PC is in the prologue,
2576 but we do know no calls have yet taken place, so we can almost
2577 certainly rely on the prologue analysis. */
2578
2579 if (body_pc <= pc)
2580 {
2581 /* Prologue analysis was successful up to the PC.
2582 It includes the cases when PC == START_PC. */
2583 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2584 /* c0_hasfp == true means there is a frame pointer because
2585 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2586 was derived from SP. Otherwise, it would be C0_FP. */
2587 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2588 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2589 fp_regnum += tdep->a0_base;
2590 }
2591 else /* No data from the prologue analysis. */
2592 {
2593 c0_hasfp = 0;
2594 fp_regnum = tdep->a0_base + C0_SP;
2595 c0_frmsz = 0;
2596 start_pc = pc;
2597 }
2598
2599 if (cache->c0.c0_fpalign)
2600 {
2601 /* This frame has a special prologue with a dynamic stack adjustment
2602 to force an alignment, which is bigger than standard 16 bytes. */
2603
2604 CORE_ADDR unaligned_sp;
2605
2606 if (cache->c0.c0_old_sp == C0_INEXP)
2607 /* This can't be. Prologue code should be consistent.
2608 Unaligned stack pointer should be saved in a spare register. */
2609 {
2610 warning_once ();
2611 ra = 0;
2612 goto finish_frame_analysis;
2613 }
2614
2615 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2616 /* Saved unaligned value of SP is kept in a register. */
2617 unaligned_sp = get_frame_register_unsigned
2618 (this_frame, tdep->a0_base + cache->c0.c0_old_sp);
2619 else
2620 /* Get the value from stack. */
2621 unaligned_sp = (CORE_ADDR)
2622 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2623
2624 prev_sp = unaligned_sp + c0_frmsz;
2625 }
2626 else
2627 prev_sp = fp + c0_frmsz;
2628
2629 /* Frame size from debug info or prologue tracking does not account for
2630 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2631 if (c0_hasfp)
2632 {
2633 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2634
2635 /* Update the stack frame size. */
2636 c0_frmsz += fp - sp;
2637 }
2638
2639 /* Get the return address (RA) from the stack if saved,
2640 or try to get it from a register. */
2641
2642 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2643 if (to_stk != C0_NOSTK)
2644 ra = (CORE_ADDR)
2645 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2646 4, byte_order);
2647
2648 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2649 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2650 {
2651 /* Special case for terminating backtrace at a function that wants to
2652 be seen as the outermost one. Such a function will clear it's RA (A0)
2653 register to 0 in the prologue instead of saving its original value. */
2654 ra = 0;
2655 }
2656 else
2657 {
2658 /* RA was copied to another register or (before any function call) may
2659 still be in the original RA register. This is not always reliable:
2660 even in a leaf function, register tracking stops after prologue, and
2661 even in prologue, non-prologue instructions (not tracked) may overwrite
2662 RA or any register it was copied to. If likely in prologue or before
2663 any call, use retracking info and hope for the best (compiler should
2664 have saved RA in stack if not in a leaf function). If not in prologue,
2665 too bad. */
2666
2667 int i;
2668 for (i = 0;
2669 (i < C0_NREGS)
2670 && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2671 ++i);
2672 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2673 i = C0_RA;
2674 if (i < C0_NREGS)
2675 {
2677 (this_frame,
2678 tdep->a0_base + cache->c0.c0_rt[i].fr_reg);
2679 }
2680 else ra = 0;
2681 }
2682
2683 finish_frame_analysis:
2684 cache->pc = start_pc;
2685 cache->ra = ra;
2686 /* RA == 0 marks the outermost frame. Do not go past it. */
2687 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2688 cache->c0.fp_regnum = fp_regnum;
2689 cache->c0.c0_frmsz = c0_frmsz;
2690 cache->c0.c0_hasfp = c0_hasfp;
2691 cache->c0.c0_fp = fp;
2692}
2694static CORE_ADDR a0_saved;
2695static CORE_ADDR a7_saved;
2696static CORE_ADDR a11_saved;
2697static int a0_was_saved;
2698static int a7_was_saved;
2699static int a11_was_saved;
2700
2701/* Simulate L32E instruction: AT <-- ref (AS + offset). */
2702static void
2703execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2704{
2705 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2706 int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb);
2707 int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb);
2708 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2709 unsigned int spilled_value
2711
2712 if ((at == 0) && !a0_was_saved)
2713 {
2715 a0_was_saved = 1;
2716 }
2717 else if ((at == 7) && !a7_was_saved)
2718 {
2720 a7_was_saved = 1;
2721 }
2722 else if ((at == 11) && !a11_was_saved)
2723 {
2725 a11_was_saved = 1;
2726 }
2727
2728 xtensa_write_register (atreg, spilled_value);
2729}
2730
2731/* Simulate S32E instruction: AT --> ref (AS + offset). */
2732static void
2733execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2734{
2735 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2736 int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb);
2737 int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb);
2738 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2739 ULONGEST spilled_value = xtensa_read_register (atreg);
2740
2743 spilled_value);
2744}
2746#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2753};
2754
2755/* Execute instruction stream from current PC until hitting RFWU or RFWO.
2756 Return type of Xtensa Window Interrupt Handler on success. */
2758execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2759{
2760 xtensa_isa isa;
2761 xtensa_insnbuf ins, slot;
2762 gdb_byte ibuf[XTENSA_ISA_BSZ];
2763 CORE_ADDR ia, bt, ba;
2764 xtensa_format ifmt;
2765 int ilen, islots, is;
2766 xtensa_opcode opc;
2767 int insn_num = 0;
2768 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2769 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2770
2771 uint32_t at, as, offset;
2772
2773 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2774 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2775
2776 isa = xtensa_default_isa;
2777 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2778 ins = xtensa_insnbuf_alloc (isa);
2779 slot = xtensa_insnbuf_alloc (isa);
2780 ba = 0;
2781 ia = current_pc;
2782 bt = ia;
2783
2784 a0_was_saved = 0;
2785 a7_was_saved = 0;
2786 a11_was_saved = 0;
2787
2788 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2789 {
2790 if (ia + xtensa_isa_maxlength (isa) > bt)
2791 {
2792 ba = ia;
2793 bt = (ba + XTENSA_ISA_BSZ);
2794 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2795 return xtNoExceptionHandler;
2796 }
2797 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2798 ifmt = xtensa_format_decode (isa, ins);
2799 if (ifmt == XTENSA_UNDEFINED)
2800 return xtNoExceptionHandler;
2801 ilen = xtensa_format_length (isa, ifmt);
2802 if (ilen == XTENSA_UNDEFINED)
2803 return xtNoExceptionHandler;
2804 islots = xtensa_format_num_slots (isa, ifmt);
2805 if (islots == XTENSA_UNDEFINED)
2806 return xtNoExceptionHandler;
2807 for (is = 0; is < islots; ++is)
2808 {
2809 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2810 return xtNoExceptionHandler;
2811 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2812 if (opc == XTENSA_UNDEFINED)
2813 return xtNoExceptionHandler;
2814 switch (call0_classify_opcode (isa, opc))
2815 {
2816 case c0opc_illegal:
2817 case c0opc_flow:
2818 case c0opc_entry:
2819 case c0opc_break:
2820 /* We expect none of them here. */
2821 return xtNoExceptionHandler;
2822 case c0opc_l32e:
2824 break;
2825 case c0opc_s32e:
2827 break;
2828 case c0opc_rfwo: /* RFWO. */
2829 /* Here, we return from WindowOverflow handler and,
2830 if we stopped at the very beginning, which means
2831 A0 was saved, we have to restore it now. */
2832 if (a0_was_saved)
2833 {
2834 int arreg = arreg_number (gdbarch,
2835 tdep->a0_base,
2836 wb);
2838 }
2839 return xtWindowOverflow;
2840 case c0opc_rfwu: /* RFWU. */
2841 /* Here, we return from WindowUnderflow handler.
2842 Let's see if either A7 or A11 has to be restored. */
2843 if (WindowUnderflow12)
2844 {
2845 if (a11_was_saved)
2846 {
2847 int arreg = arreg_number (gdbarch,
2848 tdep->a0_base + 11,
2849 wb);
2851 }
2852 }
2853 else if (a7_was_saved)
2854 {
2855 int arreg = arreg_number (gdbarch,
2856 tdep->a0_base + 7,
2857 wb);
2859 }
2860 return xtWindowUnderflow;
2861 default: /* Simply skip this insns. */
2862 continue;
2863 }
2864
2865 /* Decode arguments for L32E / S32E and simulate their execution. */
2866 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2867 return xtNoExceptionHandler;
2868 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2869 return xtNoExceptionHandler;
2870 if (xtensa_operand_decode (isa, opc, 0, &at))
2871 return xtNoExceptionHandler;
2872 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2873 return xtNoExceptionHandler;
2874 if (xtensa_operand_decode (isa, opc, 1, &as))
2875 return xtNoExceptionHandler;
2876 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2877 return xtNoExceptionHandler;
2878 if (xtensa_operand_decode (isa, opc, 2, &offset))
2879 return xtNoExceptionHandler;
2880
2881 (*func) (gdbarch, at, as, offset, wb);
2882 }
2883
2884 ia += ilen;
2885 }
2886 return xtNoExceptionHandler;
2887}
2888
2889/* Handle Window Overflow / Underflow exception frames. */
2890
2891static void
2893 xtensa_frame_cache_t *cache,
2894 CORE_ADDR pc)
2895{
2896 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2897 CORE_ADDR ps, wb, ws, ra;
2898 int epc1_regnum, i, regnum;
2900 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2901
2902 /* Read PS, WB, and WS from the hardware. Note that PS register
2903 must be present, if Windowed ABI is supported. */
2905 wb = xtensa_read_register (tdep->wb_regnum);
2906 ws = xtensa_read_register (tdep->ws_regnum);
2907
2908 /* Execute all the remaining instructions from Window Interrupt Handler
2909 by simulating them on the remote protocol level. On return, set the
2910 type of Xtensa Window Interrupt Handler, or report an error. */
2911 eh_type = execute_code (gdbarch, pc, wb);
2912 if (eh_type == xtNoExceptionHandler)
2913 error (_("\
2914Unable to decode Xtensa Window Interrupt Handler's code."));
2915
2916 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2917 cache->call0 = 0; /* It's Windowed ABI. */
2918
2919 /* All registers for the cached frame will be alive. */
2920 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2921 cache->wd.aregs[i] = -1;
2922
2923 if (eh_type == xtWindowOverflow)
2924 cache->wd.ws = ws ^ (1 << wb);
2925 else /* eh_type == xtWindowUnderflow. */
2926 cache->wd.ws = ws | (1 << wb);
2927
2928 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2930 cache->wd.wb);
2932 cache->wd.callsize = WINSIZE (ra);
2933 cache->prev_sp = xtensa_read_register (regnum + 1);
2934 /* Set regnum to a frame pointer of the frame being cached. */
2937 tdep->a0_base + regnum,
2938 cache->wd.wb);
2939 cache->base = get_frame_register_unsigned (this_frame, regnum);
2940
2941 /* Read PC of interrupted function from EPC1 register. */
2942 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2943 if (epc1_regnum < 0)
2944 error(_("Unable to read Xtensa register EPC1"));
2945 cache->ra = xtensa_read_register (epc1_regnum);
2946 cache->pc = get_frame_func (this_frame);
2947}
2948
2949
2950/* Skip function prologue.
2951
2952 Return the pc of the first instruction after prologue. GDB calls this to
2953 find the address of the first line of the function or (if there is no line
2954 number information) to skip the prologue for planting breakpoints on
2955 function entries. Use debug info (if present) or prologue analysis to skip
2956 the prologue to achieve reliable debugging behavior. For windowed ABI,
2957 only the 'entry' instruction is skipped. It is not strictly necessary to
2958 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2959 backtrace at any point in the prologue, however certain potential hazards
2960 are avoided and a more "normal" debugging experience is ensured by
2961 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2962 For example, if we don't skip the prologue:
2963 - Some args may not yet have been saved to the stack where the debug
2964 info expects to find them (true anyway when only 'entry' is skipped);
2965 - Software breakpoints ('break' instrs) may not have been unplanted
2966 when the prologue analysis is done on initializing the frame cache,
2967 and breaks in the prologue will throw off the analysis.
2968
2969 If we have debug info ( line-number info, in particular ) we simply skip
2970 the code associated with the first function line effectively skipping
2971 the prologue code. It works even in cases like
2972
2973 int main()
2974 { int local_var = 1;
2975 ....
2976 }
2977
2978 because, for this source code, both Xtensa compilers will generate two
2979 separate entries ( with the same line number ) in dwarf line-number
2980 section to make sure there is a boundary between the prologue code and
2981 the rest of the function.
2982
2983 If there is no debug info, we need to analyze the code. */
2984
2985/* #define DONT_SKIP_PROLOGUE */
2986
2987static CORE_ADDR
2988xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2989{
2990 struct symtab_and_line prologue_sal;
2991 CORE_ADDR body_pc;
2992
2993 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2994
2995#if DONT_SKIP_PROLOGUE
2996 return start_pc;
2997#endif
2998
2999 /* Try to find first body line from debug info. */
3000
3001 prologue_sal = find_pc_line (start_pc, 0);
3002 if (prologue_sal.line != 0) /* Found debug info. */
3003 {
3004 /* In Call0, it is possible to have a function with only one instruction
3005 ('ret') resulting from a one-line optimized function that does nothing.
3006 In that case, prologue_sal.end may actually point to the start of the
3007 next function in the text section, causing a breakpoint to be set at
3008 the wrong place. Check, if the end address is within a different
3009 function, and if so return the start PC. We know we have symbol
3010 information. */
3011
3012 CORE_ADDR end_func;
3013
3014 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3015 if ((tdep->call_abi == CallAbiCall0Only)
3016 && call0_ret (start_pc, prologue_sal.end))
3017 return start_pc;
3018
3019 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3020 if (end_func != start_pc)
3021 return start_pc;
3022
3023 return prologue_sal.end;
3024 }
3025
3026 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3027 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3029 return body_pc != 0 ? body_pc : start_pc;
3030}
3031
3032/* Verify the current configuration. */
3033static void
3035{
3036 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3037 string_file log;
3038
3039 /* Verify that we got a reasonable number of AREGS. */
3040 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3041 log.printf (_("\
3042\n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3043 tdep->num_aregs);
3044
3045 /* Verify that certain registers exist. */
3046
3047 if (tdep->pc_regnum == -1)
3048 log.printf (_("\n\tpc_regnum: No PC register"));
3049 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3050 log.printf (_("\n\tps_regnum: No PS register"));
3051
3053 {
3054 if (tdep->wb_regnum == -1)
3055 log.printf (_("\n\twb_regnum: No WB register"));
3056 if (tdep->ws_regnum == -1)
3057 log.printf (_("\n\tws_regnum: No WS register"));
3058 if (tdep->ar_base == -1)
3059 log.printf (_("\n\tar_base: No AR registers"));
3060 }
3061
3062 if (tdep->a0_base == -1)
3063 log.printf (_("\n\ta0_base: No Ax registers"));
3064
3065 if (!log.empty ())
3066 internal_error (_("the following are invalid: %s"), log.c_str ());
3067}
3068
3069
3070/* Derive specific register numbers from the array of registers. */
3071
3072static void
3074{
3076 int n, max_size = 4;
3077
3078 tdep->num_regs = 0;
3079 tdep->num_nopriv_regs = 0;
3080
3081/* Special registers 0..255 (core). */
3082#define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3083/* User registers 0..255. */
3084#define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3085
3086 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3087 {
3088 if (rmap->target_number == 0x0020)
3089 tdep->pc_regnum = n;
3090 else if (rmap->target_number == 0x0100)
3091 tdep->ar_base = n;
3092 else if (rmap->target_number == 0x0000)
3093 tdep->a0_base = n;
3094 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3095 tdep->wb_regnum = n;
3096 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3097 tdep->ws_regnum = n;
3098 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3099 tdep->debugcause_regnum = n;
3100 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3101 tdep->exccause_regnum = n;
3102 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3103 tdep->excvaddr_regnum = n;
3104 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3105 tdep->lbeg_regnum = n;
3106 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3107 tdep->lend_regnum = n;
3108 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3109 tdep->lcount_regnum = n;
3110 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3111 tdep->sar_regnum = n;
3112 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3113 tdep->litbase_regnum = n;
3114 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3115 tdep->ps_regnum = n;
3116 else if (rmap->target_number == XTENSA_DBREGN_UREG(231))
3117 tdep->threadptr_regnum = n;
3118#if 0
3119 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3120 tdep->interrupt_regnum = n;
3121 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3122 tdep->interrupt2_regnum = n;
3123 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3124 tdep->cpenable_regnum = n;
3125#endif
3126
3127 if (rmap->byte_size > max_size)
3128 max_size = rmap->byte_size;
3129 if (rmap->mask != 0 && tdep->num_regs == 0)
3130 tdep->num_regs = n;
3132 && tdep->num_nopriv_regs == 0)
3133 tdep->num_nopriv_regs = n;
3134 }
3135 if (tdep->num_regs == 0)
3136 tdep->num_regs = tdep->num_nopriv_regs;
3137
3138 /* Number of pseudo registers. */
3139 tdep->num_pseudo_regs = n - tdep->num_regs;
3140
3141 /* Empirically determined maximum sizes. */
3142 tdep->max_register_raw_size = max_size;
3143 tdep->max_register_virtual_size = max_size;
3144}
3145
3146/* Module "constructor" function. */
3147
3149
3150static struct gdbarch *
3152{
3153 struct gdbarch *gdbarch;
3154
3155 DEBUGTRACE ("gdbarch_init()\n");
3156
3157 if (!xtensa_default_isa)
3158 xtensa_default_isa = xtensa_isa_init (0, 0);
3159
3160 /* We have to set the byte order before we call gdbarch_alloc. */
3161 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3162
3164 gdbarch = gdbarch_alloc (&info, tdep);
3165 xtensa_derive_tdep (tdep);
3166
3167 /* Verify our configuration. */
3170
3171 set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3173
3174 /* Pseudo-Register read/write. */
3177
3178 /* Set target information. */
3184
3185 /* Renumber registers for known formats (stabs and dwarf2). */
3188
3189 /* We provide our own function to get register information. */
3192
3193 /* To call functions from GDB using dummy frame. */
3195
3197
3199
3200 /* Advance PC across any prologue instructions to reach "real" code. */
3202
3203 /* Stack grows downward. */
3205
3206 /* Set breakpoints. */
3211
3212 /* After breakpoint instruction or illegal instruction, pc still
3213 points at break instruction, so don't decrement. */
3215
3216 /* We don't skip args. */
3218
3220
3222
3224
3225 /* Frame handling. */
3229
3231
3234
3237
3240
3241 /* Hook in the ABI-specific overrides, if they have been registered. */
3243
3244 return gdbarch;
3245}
3246
3247static void
3248xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3249{
3250 error (_("xtensa_dump_tdep(): not implemented"));
3251}
3252
3254void
3256{
3259
3260 add_setshow_zuinteger_cmd ("xtensa",
3263 _("Set Xtensa debugging."),
3264 _("Show Xtensa debugging."), _("\
3265When non-zero, Xtensa-specific debugging is enabled. \
3266Can be 1, 2, 3, or 4 indicating the level of debugging."),
3267 NULL,
3268 NULL,
3270}
int regnum
const char *const name
int code
Definition ada-lex.l:688
static std::vector< const char * > arches
Definition arch-utils.c:685
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep)
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition arch-utils.c:177
struct_return
Definition arm-tdep.h:84
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
Definition blockframe.c:373
frame_info * get() const
Definition frame-info.h:120
enum register_status raw_read(int regnum, gdb_byte *buf)
Definition regcache.c:605
enum register_status raw_read_part(int regnum, int offset, int len, gdb_byte *buf)
Definition regcache.c:1013
enum register_status cooked_read(int regnum, gdb_byte *buf)
Definition regcache.c:692
gdbarch * arch() const
Definition regcache.c:230
void raw_supply(int regnum, const void *buf) override
Definition regcache.c:1053
void cooked_write(int regnum, const gdb_byte *buf)
Definition regcache.c:861
void raw_write_part(int regnum, int offset, int len, const gdb_byte *buf)
Definition regcache.c:1023
void raw_write(int regnum, const gdb_byte *buf)
Definition regcache.c:827
const char * c_str() const
Definition ui-file.h:218
bool empty() const
Definition ui-file.h:220
void printf(const char *,...) ATTRIBUTE_PRINTF(2
Definition ui-file.c:40
struct cmd_list_element * showdebuglist
Definition cli-cmds.c:165
struct cmd_list_element * setdebuglist
Definition cli-cmds.c:163
set_show_commands add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
@ class_maintenance
Definition command.h:65
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition corefile.c:346
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition corefile.c:305
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition corefile.c:369
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition corefile.c:237
int safe_read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, LONGEST *return_value)
Definition corefile.c:263
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition corefile.c:295
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition defs.h:561
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition findvar.c:153
#define UINT_MAX
Definition defs.h:453
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition defs.h:526
return_value_convention
Definition defs.h:258
@ RETURN_VALUE_REGISTER_CONVENTION
Definition defs.h:261
@ RETURN_VALUE_STRUCT_CONVENTION
Definition defs.h:268
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition frame.c:1361
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition frame-base.c:93
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
struct value * frame_unwind_got_memory(frame_info_ptr frame, int regnum, CORE_ADDR addr)
struct value * frame_unwind_got_register(frame_info_ptr frame, int regnum, int new_regnum)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
Definition frame.c:1351
CORE_ADDR get_frame_pc(frame_info_ptr frame)
Definition frame.c:2592
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition frame.c:713
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition frame.c:2907
void frame_unwind_register(frame_info_ptr next_frame, int regnum, gdb_byte *buf)
Definition frame.c:1195
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
Definition frame.c:1050
@ NORMAL_FRAME
Definition frame.h:179
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition frame.h:608
@ fp_regnum
Definition frv-tdep.h:36
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype *stab_reg_to_regnum)
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2023
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype *unwind_pc)
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition gdbarch.c:2050
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition gdbarch.c:1370
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_wchar_bit(struct gdbarch *gdbarch, int wchar_bit)
Definition gdbarch.c:1649
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition gdbarch.c:2848
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
Definition gdbarch.c:2439
void set_gdbarch_wchar_signed(struct gdbarch *gdbarch, int wchar_signed)
Definition gdbarch.c:1667
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition gdbarch.c:3508
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition gdbarch.c:1899
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition gdbarch.c:2016
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition gdbarch.c:2033
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *register_type)
int gdbarch_ps_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2040
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition gdbarch.c:1927
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition gdbarch.c:1910
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype *dummy_id)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype *iterate_over_regset_sections)
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition gdbarch.c:2947
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, struct gdbarch_tdep_base *tdep)
Definition gdbarch.c:264
void() iterate_over_regset_sections_cb(const char *sect_name, int supply_size, int collect_size, const struct regset *regset, const char *human_name, void *cb_data)
Definition gdbarch.h:102
static int gdbarch_num_cooked_regs(gdbarch *arch)
Definition gdbarch.h:377
function_call_return_method
Definition gdbarch.h:112
@ return_method_struct
Definition gdbarch.h:124
struct type * arch_integer_type(struct gdbarch *gdbarch, int bit, int unsigned_p, const char *name)
Definition gdbtypes.c:5836
struct type * check_typedef(struct type *type)
Definition gdbtypes.c:3010
mach_port_t kern_return_t mach_port_t mach_msg_type_name_t msgportsPoly mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
Definition gnu-nat.c:1862
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition gnu-nat.c:1791
size_t size
Definition go32-nat.c:241
info(c)
Definition gdbarch.py:184
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition osabi.c:382
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:643
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:790
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:671
struct regcache * get_current_regcache(void)
Definition regcache.c:426
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:819
const reggroup *const general_reggroup
Definition reggroups.c:251
const reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition reggroups.c:34
const reggroup *const system_reggroup
Definition reggroups.c:253
const reggroup *const float_reggroup
Definition reggroups.c:252
const reggroup *const save_reggroup
Definition reggroups.c:256
const reggroup *const all_reggroup
Definition reggroups.c:255
void reggroup_add(struct gdbarch *gdbarch, const reggroup *group)
Definition reggroups.c:124
const reggroup *const restore_reggroup
Definition reggroups.c:257
const reggroup *const vector_reggroup
Definition reggroups.c:254
@ USER_REGGROUP
Definition reggroups.h:32
void(* func)(remote_target *remote, char *)
constexpr gdb_byte little_breakpoint[]
constexpr gdb_byte big_breakpoint[]
void set_solib_svr4_fetch_link_map_offsets(struct gdbarch *gdbarch, struct link_map_offsets *(*flmo)(void))
struct link_map_offsets * svr4_ilp32_fetch_link_map_offsets(void)
struct type * builtin_uint16
Definition gdbtypes.h:2284
struct type * builtin_double
Definition gdbtypes.h:2258
struct type * builtin_uint128
Definition gdbtypes.h:2292
struct type * builtin_long
Definition gdbtypes.h:2249
struct type * builtin_data_ptr
Definition gdbtypes.h:2303
struct type * builtin_uint32
Definition gdbtypes.h:2288
struct type * builtin_uint64
Definition gdbtypes.h:2290
struct type * builtin_int
Definition gdbtypes.h:2248
struct type * builtin_uint8
Definition gdbtypes.h:2282
struct type * virtual_type
struct ctype_cache * next
CORE_ADDR pc
Definition symtab.h:2272
CORE_ADDR end
Definition symtab.h:2273
type_code code() const
Definition gdbtypes.h:927
ULONGEST length() const
Definition gdbtypes.h:954
Definition value.c:181
xtensa_c0reg_t c0_rt[C0_NREGS]
xtensa_elf_greg_t ar[64]
Definition xtensa.h:40
xtensa_elf_greg_t lcount
Definition xtensa.h:34
xtensa_elf_greg_t ps
Definition xtensa.h:31
xtensa_elf_greg_t pc
Definition xtensa.h:30
xtensa_elf_greg_t lbeg
Definition xtensa.h:32
xtensa_elf_greg_t windowstart
Definition xtensa.h:36
xtensa_elf_greg_t lend
Definition xtensa.h:33
xtensa_elf_greg_t sar
Definition xtensa.h:35
xtensa_elf_greg_t windowbase
Definition xtensa.h:37
xtensa_call0_frame_cache_t c0
xtensa_windowed_frame_cache_t wd
unsigned int isa_use_density_instructions
unsigned int num_pseudo_regs
unsigned int num_aregs
unsigned int target_flags
unsigned int num_nopriv_regs
xtensa_register_t * regmap
unsigned int isa_use_exceptions
unsigned int num_regs
unsigned int isa_use_windowed_registers
struct ctype_cache * type_entries
struct type * ctype
xtensa_register_group_t group
unsigned int target_number
xtensa_register_type_t type
const char * name
const xtensa_mask_t * mask
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
Definition symtab.c:3297
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition target.c:1771
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition utils.c:1865
#define gdb_stdlog
Definition utils.h:196
struct value * value_cast(struct type *type, struct value *arg2)
Definition valops.c:408
struct type * value_type(const struct value *value)
Definition value.c:1109
gdb::array_view< const gdb_byte > value_contents(struct value *value)
Definition value.c:1464
static xtensa_register_t rmap[]
static xtensa_insn_kind call0_classify_opcode(xtensa_isa isa, xtensa_opcode opc)
static int rwx_special_register(const char *opcname)
xtensa_exception_handler_t
@ xtNoExceptionHandler
@ xtWindowOverflow
@ xtWindowUnderflow
static void xtensa_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buffer)
static const char * xtensa_register_name(struct gdbarch *gdbarch, int regnum)
static struct xtensa_frame_cache * xtensa_alloc_frame_cache(int windowed)
#define SAVE_REST_VALID
struct xtensa_windowed_frame_cache xtensa_windowed_frame_cache_t
static enum return_value_convention xtensa_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static int xtensa_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
struct xtensa_call0_frame_cache xtensa_call0_frame_cache_t
static void xtensa_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
#define DEBUGVERB(args...)
Definition xtensa-tdep.c:62
static unsigned int xtensa_debug_level
Definition xtensa-tdep.c:48
static struct gdbarch * xtensa_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
#define XTENSA_ISA_BADPC
static int call0_ret(CORE_ADDR start_pc, CORE_ADDR finish_pc)
static unsigned int xtensa_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR current_pc)
#define SAVE_REST_FLAGS
static CORE_ADDR xtensa_frame_align(struct gdbarch *gdbarch, CORE_ADDR address)
#define XTENSA_NUM_SAVED_AREGS
static int extract_call_winsize(struct gdbarch *gdbarch, CORE_ADDR pc)
#define TX_PS
Definition xtensa-tdep.c:86
#define DEBUGTRACE(args...)
Definition xtensa-tdep.c:58
#define BIG_BREAKPOINT
static void xtensa_init_reggroups(void)
static const reggroup * xtensa_ar_reggroup
#define RETURN_FP
static const reggroup * xtensa_user_reggroup
static CORE_ADDR a11_saved
#define C0_RA
static void call0_frame_cache(frame_info_ptr this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static CORE_ADDR a7_saved
#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
static CORE_ADDR call0_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR pc, int nregs, xtensa_frame_cache_t *cache)
#define C0_NOSTK
#define XTENSA_MAX_REGISTER_SIZE
#define LITTLE_BREAKPOINT
#define ARG_NOF(tdep)
Definition xtensa-tdep.c:89
#define DENSITY_BIG_BREAKPOINT
static unsigned long xtensa_read_register(int regnum)
#define C0_INEXP
static void xtensa_add_reggroups(struct gdbarch *gdbarch)
static int xtensa_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
static void xtensa_window_interrupt_frame_cache(frame_info_ptr this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static CORE_ADDR a0_saved
#define XTENSA_DBREGN_UREG(n)
void _initialize_xtensa_tdep()
static void xtensa_write_register(int regnum, ULONGEST value)
#define C0_MAXOPDS
static void xtensa_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
static const reggroup * xtensa_cp[XTENSA_MAX_COPROCESSOR]
#define CALLINC(ps)
Definition xtensa-tdep.c:80
static struct value * xtensa_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static void xtensa_store_return_value(struct type *type, struct regcache *regcache, const void *dst)
static int a7_was_saved
static int call0_track_op(struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], xtensa_insn_kind opclass, int nods, unsigned odv[], CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
#define PS_CALLINC_SHIFT
Definition xtensa-tdep.c:78
xtensa_insn_kind
@ c0opc_sub
@ c0opc_s32e
@ c0opc_add
@ c0opc_movi
@ c0opc_l32e
@ c0opc_addi
@ c0opc_mov
@ c0opc_l32r
@ c0opc_rwxsr
@ c0opc_entry
@ c0opc_rfwu
@ c0opc_uninteresting
@ c0opc_flow
@ c0opc_illegal
@ c0opc_and
@ c0opc_break
@ c0opc_s32i
@ c0opc_NrOf
@ c0opc_rfwo
static int areg_number(struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
static xtensa_exception_handler_t execute_code(struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
xtensa_gdbarch_tdep xtensa_tdep
static void execute_l32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
static const struct frame_unwind xtensa_unwind
static int arreg_number(struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
#define XTENSA_DBREGN_SREG(n)
static void execute_s32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
#define C0_SP
static CORE_ADDR xtensa_frame_base_address(frame_info_ptr this_frame, void **this_cache)
static CORE_ADDR xtensa_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
#define ARG_1ST(tdep)
Definition xtensa-tdep.c:92
#define DEBUGINFO(args...)
Definition xtensa-tdep.c:54
struct xtensa_c0reg xtensa_c0reg_t
static const struct frame_base xtensa_frame_base
static struct regset xtensa_gregset
static int xtensa_find_register_by_name(struct gdbarch *gdbarch, const char *name)
static int xtensa_coprocessor_register_group(const struct reggroup *group)
static const gdb_byte * xtensa_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
struct xtensa_frame_cache xtensa_frame_cache_t
static int windowing_enabled(struct gdbarch *gdbarch, unsigned int ps)
#define XTENSA_ISA_BSZ
static int xtensa_session_once_reported
static const reggroup * xtensa_vectra_reggroup
#define WINSIZE(ra)
Definition xtensa-tdep.c:81
static int a11_was_saved
static void xtensa_derive_tdep(xtensa_gdbarch_tdep *tdep)
static void xtensa_verify_config(struct gdbarch *gdbarch)
#define REGISTER_SIZE
Definition xtensa-tdep.c:74
static void xtensa_supply_gregset(const struct regset *regset, struct regcache *rc, int regnum, const void *gregs, size_t len)
static struct frame_id xtensa_dummy_id(struct gdbarch *gdbarch, frame_info_ptr this_frame)
#define C0_FP
#define XTENSA_IS_ENTRY(gdbarch, op1)
static enum register_status xtensa_register_read_masked(readable_regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer)
static enum register_status xtensa_pseudo_register_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buffer)
static void xtensa_extract_return_value(struct type *type, struct regcache *regcache, void *dst)
#define SP_ALIGNMENT
Definition xtensa-tdep.c:68
#define C0_ARGS
xtensa_isa xtensa_default_isa
static struct type * xtensa_register_type(struct gdbarch *gdbarch, int regnum)
static CORE_ADDR xtensa_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
#define PS_EXC
static int xtensa_reg_to_regnum(struct gdbarch *gdbarch, int regnum)
#define RETURN_RET
#define PS_WOE
#define DENSITY_LITTLE_BREAKPOINT
static void xtensa_register_write_masked(struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer)
static CORE_ADDR xtensa_unwind_pc(struct gdbarch *gdbarch, frame_info_ptr next_frame)
#define C0_CONST
static void xtensa_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
static void warning_once(void)
static int xtensa_window_interrupt_insn(struct gdbarch *gdbarch, CORE_ADDR pc)
static int a0_was_saved
#define WB_SHIFT
#define XTENSA_MAX_COPROCESSOR
Definition xtensa-tdep.h:51
xtensa_register_group_t
Definition xtensa-tdep.h:54
@ xtRegisterGroupUser
Definition xtensa-tdep.h:63
@ xtRegisterGroupState
Definition xtensa-tdep.h:60
@ xtRegisterGroupFloat
Definition xtensa-tdep.h:64
@ xtRegisterGroupVectra
Definition xtensa-tdep.h:65
@ xtRegisterGroupCP0
Definition xtensa-tdep.h:69
@ xtRegisterGroupAddrReg
Definition xtensa-tdep.h:57
@ xtRegisterGroupGeneral
Definition xtensa-tdep.h:62
@ CallAbiCall0Only
xtensa_register_type_t
Definition xtensa-tdep.h:35
@ xtRegisterTypeUnknown
Definition xtensa-tdep.h:45
@ xtRegisterTypeMapped
Definition xtensa-tdep.h:41
@ xtRegisterTypeTieRegfile
Definition xtensa-tdep.h:39
@ xtRegisterTypeUnmapped
Definition xtensa-tdep.h:42
@ xtRegisterTypeTieState
Definition xtensa-tdep.h:40
@ xtTargetFlagsNonVisibleRegs
Definition xtensa-tdep.h:85
@ xtTargetFlagsUseFetchStore
Definition xtensa-tdep.h:86
#define XTENSA_REGISTER_FLAGS_PRIVILEGED
#define C0_NREGS
Definition xtensa.h:46