18#ifndef NAT_AARCH64_HW_POINT_H
19#define NAT_AARCH64_HW_POINT_H
33#define AARCH64_HBP_MAX_NUM 16
34#define AARCH64_HWP_MAX_NUM 16
48#define AARCH64_HBP_ALIGNMENT 4
49#define AARCH64_HWP_ALIGNMENT 8
54#define AARCH64_HWP_MAX_LEN_PER_REG 8
57#define AARCH64_DEBUG_ARCH_V8 0x6
58#define AARCH64_DEBUG_ARCH_V8_1 0x7
59#define AARCH64_DEBUG_ARCH_V8_2 0x8
60#define AARCH64_DEBUG_ARCH_V8_4 0x9
61#define AARCH64_DEBUG_ARCH_V8_8 0xa
63#define AARCH64_DEBUG_ARCH_V8_9 0xb
74#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
75#define DR_CONTROL_MASK(ctrl) (((ctrl) >> 5) & 0xff)
112 int len,
int is_insert, ptid_t ptid,
115 int len,
int is_insert, ptid_t ptid,
124 const char *
func, CORE_ADDR addr,
125 int len,
enum target_hw_bp_type
type);
void aarch64_show_debug_reg_state(struct aarch64_debug_reg_state *state, const char *func, CORE_ADDR addr, int len, enum target_hw_bp_type type)
#define AARCH64_HBP_MAX_NUM
int aarch64_region_ok_for_watchpoint(CORE_ADDR addr, int len)
unsigned int aarch64_watchpoint_length(unsigned int ctrl)
#define AARCH64_HWP_MAX_NUM
int aarch64_handle_breakpoint(enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert, ptid_t ptid, struct aarch64_debug_reg_state *state)
int aarch64_handle_watchpoint(enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert, ptid_t ptid, struct aarch64_debug_reg_state *state)
bool aarch64_any_set_debug_regs_state(aarch64_debug_reg_state *state, bool watchpoint)
void aarch64_notify_debug_reg_change(ptid_t ptid, int is_watchpoint, unsigned int idx)
unsigned int aarch64_watchpoint_offset(unsigned int ctrl)
bool is_watchpoint(const struct breakpoint *bpt)
void(* func)(remote_target *remote, char *)
unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]
CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]
unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]
unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]
CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]
unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]
CORE_ADDR dr_addr_orig_wp[AARCH64_HWP_MAX_NUM]