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i387-tdep.c
Go to the documentation of this file.
1/* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "gdbcore.h"
23#include "inferior.h"
24#include "language.h"
25#include "regcache.h"
26#include "target-float.h"
27#include "value.h"
28
29#include "i386-tdep.h"
30#include "i387-tdep.h"
31#include "gdbsupport/x86-xstate.h"
32
33/* Print the floating point number specified by RAW. */
34
35static void
37 const gdb_byte *raw, struct ui_file *file)
38{
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct type *type = i387_ext_type (gdbarch);
44 std::string str = target_float_to_string (raw, type, " %-+27.19g");
45 gdb_printf (file, "%s", str.c_str ());
46}
47
48/* Print the classification for the register contents RAW. */
49
50static void
52 const gdb_byte *raw, struct ui_file *file)
53{
54 int sign;
55 int integer;
56 unsigned int exponent;
57 unsigned long fraction[2];
58
59 sign = raw[9] & 0x80;
60 integer = raw[7] & 0x80;
61 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
62 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
63 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
64 | (raw[5] << 8) | raw[4]);
65
66 if (exponent == 0x7fff && integer)
67 {
68 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
69 /* Infinity. */
70 gdb_printf (file, " %cInf", (sign ? '-' : '+'));
71 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
72 /* Real Indefinite (QNaN). */
73 gdb_puts (" Real Indefinite (QNaN)", file);
74 else if (fraction[1] & 0x40000000)
75 /* QNaN. */
76 gdb_puts (" QNaN", file);
77 else
78 /* SNaN. */
79 gdb_puts (" SNaN", file);
80 }
81 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
82 /* Normal. */
83 print_i387_value (gdbarch, raw, file);
84 else if (exponent == 0x0000)
85 {
86 /* Denormal or zero. */
87 print_i387_value (gdbarch, raw, file);
88
89 if (integer)
90 /* Pseudo-denormal. */
91 gdb_puts (" Pseudo-denormal", file);
92 else if (fraction[0] || fraction[1])
93 /* Denormal. */
94 gdb_puts (" Denormal", file);
95 }
96 else
97 /* Unsupported. */
98 gdb_puts (" Unsupported", file);
99}
100
101/* Print the status word STATUS. If STATUS_P is false, then STATUS
102 was unavailable. */
103
104static void
106 unsigned int status, struct ui_file *file)
107{
108 gdb_printf (file, "Status Word: ");
109 if (!status_p)
110 {
111 gdb_printf (file, "%s\n", _("<unavailable>"));
112 return;
113 }
114
115 gdb_printf (file, "%s", hex_string_custom (status, 4));
116 gdb_puts (" ", file);
117 gdb_printf (file, " %s", (status & 0x0001) ? "IE" : " ");
118 gdb_printf (file, " %s", (status & 0x0002) ? "DE" : " ");
119 gdb_printf (file, " %s", (status & 0x0004) ? "ZE" : " ");
120 gdb_printf (file, " %s", (status & 0x0008) ? "OE" : " ");
121 gdb_printf (file, " %s", (status & 0x0010) ? "UE" : " ");
122 gdb_printf (file, " %s", (status & 0x0020) ? "PE" : " ");
123 gdb_puts (" ", file);
124 gdb_printf (file, " %s", (status & 0x0080) ? "ES" : " ");
125 gdb_puts (" ", file);
126 gdb_printf (file, " %s", (status & 0x0040) ? "SF" : " ");
127 gdb_puts (" ", file);
128 gdb_printf (file, " %s", (status & 0x0100) ? "C0" : " ");
129 gdb_printf (file, " %s", (status & 0x0200) ? "C1" : " ");
130 gdb_printf (file, " %s", (status & 0x0400) ? "C2" : " ");
131 gdb_printf (file, " %s", (status & 0x4000) ? "C3" : " ");
132
133 gdb_puts ("\n", file);
134
135 gdb_printf (file,
136 " TOP: %d\n", ((status >> 11) & 7));
137}
138
139/* Print the control word CONTROL. If CONTROL_P is false, then
140 CONTROL was unavailable. */
141
142static void
144 unsigned int control, struct ui_file *file)
145{
146 gdb_printf (file, "Control Word: ");
147 if (!control_p)
148 {
149 gdb_printf (file, "%s\n", _("<unavailable>"));
150 return;
151 }
152
153 gdb_printf (file, "%s", hex_string_custom (control, 4));
154 gdb_puts (" ", file);
155 gdb_printf (file, " %s", (control & 0x0001) ? "IM" : " ");
156 gdb_printf (file, " %s", (control & 0x0002) ? "DM" : " ");
157 gdb_printf (file, " %s", (control & 0x0004) ? "ZM" : " ");
158 gdb_printf (file, " %s", (control & 0x0008) ? "OM" : " ");
159 gdb_printf (file, " %s", (control & 0x0010) ? "UM" : " ");
160 gdb_printf (file, " %s", (control & 0x0020) ? "PM" : " ");
161
162 gdb_puts ("\n", file);
163
164 gdb_puts (" PC: ", file);
165 switch ((control >> 8) & 3)
166 {
167 case 0:
168 gdb_puts ("Single Precision (24-bits)\n", file);
169 break;
170 case 1:
171 gdb_puts ("Reserved\n", file);
172 break;
173 case 2:
174 gdb_puts ("Double Precision (53-bits)\n", file);
175 break;
176 case 3:
177 gdb_puts ("Extended Precision (64-bits)\n", file);
178 break;
179 }
180
181 gdb_puts (" RC: ", file);
182 switch ((control >> 10) & 3)
183 {
184 case 0:
185 gdb_puts ("Round to nearest\n", file);
186 break;
187 case 1:
188 gdb_puts ("Round down\n", file);
189 break;
190 case 2:
191 gdb_puts ("Round up\n", file);
192 break;
193 case 3:
194 gdb_puts ("Round toward zero\n", file);
195 break;
196 }
197}
198
199/* Print out the i387 floating point state. Note that we ignore FRAME
200 in the code below. That's OK since floating-point registers are
201 never saved on the stack. */
202
203void
205 frame_info_ptr frame, const char *args)
206{
207 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
208 ULONGEST fctrl;
209 int fctrl_p;
210 ULONGEST fstat;
211 int fstat_p;
212 ULONGEST ftag;
213 int ftag_p;
214 ULONGEST fiseg;
215 int fiseg_p;
216 ULONGEST fioff;
217 int fioff_p;
218 ULONGEST foseg;
219 int foseg_p;
220 ULONGEST fooff;
221 int fooff_p;
222 ULONGEST fop;
223 int fop_p;
224 int fpreg;
225 int top;
226
227 gdb_assert (gdbarch == get_frame_arch (frame));
228
229 fctrl_p = read_frame_register_unsigned (frame,
230 I387_FCTRL_REGNUM (tdep), &fctrl);
231 fstat_p = read_frame_register_unsigned (frame,
232 I387_FSTAT_REGNUM (tdep), &fstat);
233 ftag_p = read_frame_register_unsigned (frame,
234 I387_FTAG_REGNUM (tdep), &ftag);
235 fiseg_p = read_frame_register_unsigned (frame,
236 I387_FISEG_REGNUM (tdep), &fiseg);
237 fioff_p = read_frame_register_unsigned (frame,
238 I387_FIOFF_REGNUM (tdep), &fioff);
239 foseg_p = read_frame_register_unsigned (frame,
240 I387_FOSEG_REGNUM (tdep), &foseg);
241 fooff_p = read_frame_register_unsigned (frame,
242 I387_FOOFF_REGNUM (tdep), &fooff);
243 fop_p = read_frame_register_unsigned (frame,
244 I387_FOP_REGNUM (tdep), &fop);
245
246 if (fstat_p)
247 {
248 top = ((fstat >> 11) & 7);
249
250 for (fpreg = 7; fpreg >= 0; fpreg--)
251 {
252 struct value *regval;
253 int regnum;
254 int i;
255 int tag = -1;
256
257 gdb_printf (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
258
259 if (ftag_p)
260 {
261 tag = (ftag >> (fpreg * 2)) & 3;
262
263 switch (tag)
264 {
265 case 0:
266 gdb_puts ("Valid ", file);
267 break;
268 case 1:
269 gdb_puts ("Zero ", file);
270 break;
271 case 2:
272 gdb_puts ("Special ", file);
273 break;
274 case 3:
275 gdb_puts ("Empty ", file);
276 break;
277 }
278 }
279 else
280 gdb_puts ("Unknown ", file);
281
282 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
283 regval = get_frame_register_value (frame, regnum);
284
285 if (regval->entirely_available ())
286 {
287 const gdb_byte *raw = regval->contents ().data ();
288
289 gdb_puts ("0x", file);
290 for (i = 9; i >= 0; i--)
291 gdb_printf (file, "%02x", raw[i]);
292
293 if (tag != -1 && tag != 3)
294 print_i387_ext (gdbarch, raw, file);
295 }
296 else
297 gdb_printf (file, "%s", _("<unavailable>"));
298
299 gdb_puts ("\n", file);
300 }
301 }
302
303 gdb_puts ("\n", file);
304 print_i387_status_word (fstat_p, fstat, file);
305 print_i387_control_word (fctrl_p, fctrl, file);
306 gdb_printf (file, "Tag Word: %s\n",
307 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
308 gdb_printf (file, "Instruction Pointer: %s:",
309 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
310 gdb_printf (file, "%s\n",
311 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
312 gdb_printf (file, "Operand Pointer: %s:",
313 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
314 gdb_printf (file, "%s\n",
315 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
316 gdb_printf (file, "Opcode: %s\n",
317 fop_p
318 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
319 : _("<unavailable>"));
320}
321
322
323/* Return nonzero if a value of type TYPE stored in register REGNUM
324 needs any special handling. */
325
326int
328 struct type *type)
329{
331 {
332 /* Floating point registers must be converted unless we are
333 accessing them in their hardware type or TYPE is not float. */
334 if (type == i387_ext_type (gdbarch)
335 || type->code () != TYPE_CODE_FLT)
336 return 0;
337 else
338 return 1;
339 }
340
341 return 0;
342}
343
344/* Read a value of type TYPE from register REGNUM in frame FRAME, and
345 return its contents in TO. */
346
347int
349 struct type *type, gdb_byte *to,
350 int *optimizedp, int *unavailablep)
351{
352 struct gdbarch *gdbarch = get_frame_arch (frame);
353 gdb_byte from[I386_MAX_REGISTER_SIZE];
354
355 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
356
357 /* We only support floating-point values. */
358 if (type->code () != TYPE_CODE_FLT)
359 {
360 warning (_("Cannot convert floating-point register value "
361 "to non-floating-point type."));
362 *optimizedp = *unavailablep = 0;
363 return 0;
364 }
365
366 /* Convert to TYPE. */
367 if (!get_frame_register_bytes (frame, regnum, 0,
368 gdb::make_array_view (from,
370 regnum)),
371 optimizedp, unavailablep))
372 return 0;
373
375 *optimizedp = *unavailablep = 0;
376 return 1;
377}
378
379/* Write the contents FROM of a value of type TYPE into register
380 REGNUM in frame FRAME. */
381
382void
384 struct type *type, const gdb_byte *from)
385{
386 struct gdbarch *gdbarch = get_frame_arch (frame);
387 gdb_byte to[I386_MAX_REGISTER_SIZE];
388
389 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
390
391 /* We only support floating-point values. */
392 if (type->code () != TYPE_CODE_FLT)
393 {
394 warning (_("Cannot convert non-floating-point type "
395 "to floating-point register value."));
396 return;
397 }
398
399 /* Convert from TYPE. */
401 put_frame_register (frame, regnum, to);
402}
403
404
405/* Handle FSAVE and FXSAVE formats. */
406
407/* At fsave_offset[REGNUM] you'll find the offset to the location in
408 the data structure used by the "fsave" instruction where GDB
409 register REGNUM is stored. */
410
411static int fsave_offset[] =
412{
413 28 + 0 * 10, /* %st(0) ... */
414 28 + 1 * 10,
415 28 + 2 * 10,
416 28 + 3 * 10,
417 28 + 4 * 10,
418 28 + 5 * 10,
419 28 + 6 * 10,
420 28 + 7 * 10, /* ... %st(7). */
421 0, /* `fctrl' (16 bits). */
422 4, /* `fstat' (16 bits). */
423 8, /* `ftag' (16 bits). */
424 16, /* `fiseg' (16 bits). */
425 12, /* `fioff'. */
426 24, /* `foseg' (16 bits). */
427 20, /* `fooff'. */
428 18 /* `fop' (bottom 11 bits). */
429};
430
431#define FSAVE_ADDR(tdep, fsave, regnum) \
432 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
433
434
435/* Fill register REGNUM in REGCACHE with the appropriate value from
436 *FSAVE. This function masks off any of the reserved bits in
437 *FSAVE. */
438
439void
440i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
441{
442 struct gdbarch *gdbarch = regcache->arch ();
443 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
444 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
445 const gdb_byte *regs = (const gdb_byte *) fsave;
446 int i;
447
448 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
449
450 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
451 if (regnum == -1 || regnum == i)
452 {
453 if (fsave == NULL)
454 {
455 regcache->raw_supply (i, NULL);
456 continue;
457 }
458
459 /* Most of the FPU control registers occupy only 16 bits in the
460 fsave area. Give those a special treatment. */
461 if (i >= I387_FCTRL_REGNUM (tdep)
462 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
463 {
464 gdb_byte val[4];
465
466 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
467 val[2] = val[3] = 0;
468 if (i == I387_FOP_REGNUM (tdep))
469 val[1] &= ((1 << 3) - 1);
470 regcache->raw_supply (i, val);
471 }
472 else
473 regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i));
474 }
475
476 /* Provide dummy values for the SSE registers. */
477 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
478 if (regnum == -1 || regnum == i)
479 regcache->raw_supply (i, NULL);
480 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
481 {
482 gdb_byte buf[4];
483
484 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
486 }
487}
488
489/* Fill register REGNUM (if it is a floating-point register) in *FSAVE
490 with the value from REGCACHE. If REGNUM is -1, do this for all
491 registers. This function doesn't touch any of the reserved bits in
492 *FSAVE. */
493
494void
495i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
496{
497 gdbarch *arch = regcache->arch ();
498 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
499 gdb_byte *regs = (gdb_byte *) fsave;
500 int i;
501
502 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
503
504 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
505 if (regnum == -1 || regnum == i)
506 {
507 /* Most of the FPU control registers occupy only 16 bits in
508 the fsave area. Give those a special treatment. */
509 if (i >= I387_FCTRL_REGNUM (tdep)
510 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
511 {
512 gdb_byte buf[4];
513
514 regcache->raw_collect (i, buf);
515
516 if (i == I387_FOP_REGNUM (tdep))
517 {
518 /* The opcode occupies only 11 bits. Make sure we
519 don't touch the other bits. */
520 buf[1] &= ((1 << 3) - 1);
521 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
522 }
523 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
524 }
525 else
526 regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i));
527 }
528}
529
530
531/* At fxsave_offset[REGNUM] you'll find the offset to the location in
532 the data structure used by the "fxsave" instruction where GDB
533 register REGNUM is stored. */
534
535static int fxsave_offset[] =
536{
537 32, /* %st(0) through ... */
538 48,
539 64,
540 80,
541 96,
542 112,
543 128,
544 144, /* ... %st(7) (80 bits each). */
545 0, /* `fctrl' (16 bits). */
546 2, /* `fstat' (16 bits). */
547 4, /* `ftag' (16 bits). */
548 12, /* `fiseg' (16 bits). */
549 8, /* `fioff'. */
550 20, /* `foseg' (16 bits). */
551 16, /* `fooff'. */
552 6, /* `fop' (bottom 11 bits). */
553 160 + 0 * 16, /* %xmm0 through ... */
554 160 + 1 * 16,
555 160 + 2 * 16,
556 160 + 3 * 16,
557 160 + 4 * 16,
558 160 + 5 * 16,
559 160 + 6 * 16,
560 160 + 7 * 16,
561 160 + 8 * 16,
562 160 + 9 * 16,
563 160 + 10 * 16,
564 160 + 11 * 16,
565 160 + 12 * 16,
566 160 + 13 * 16,
567 160 + 14 * 16,
568 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
569};
570
571#define FXSAVE_ADDR(tdep, fxsave, regnum) \
572 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
573
574/* We made an unfortunate choice in putting %mxcsr after the SSE
575 registers %xmm0-%xmm7 instead of before, since it makes supporting
576 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
577 don't include the offset for %mxcsr here above. */
578
579#define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
580
581static int i387_tag (const gdb_byte *raw);
582
583
584/* Fill register REGNUM in REGCACHE with the appropriate
585 floating-point or SSE register value from *FXSAVE. This function
586 masks off any of the reserved bits in *FXSAVE. */
587
588void
589i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
590{
591 gdbarch *arch = regcache->arch ();
592 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
593 const gdb_byte *regs = (const gdb_byte *) fxsave;
594 int i;
595
596 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
597 gdb_assert (tdep->num_xmm_regs > 0);
598
599 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
600 if (regnum == -1 || regnum == i)
601 {
602 if (regs == NULL)
603 {
604 regcache->raw_supply (i, NULL);
605 continue;
606 }
607
608 /* Most of the FPU control registers occupy only 16 bits in
609 the fxsave area. Give those a special treatment. */
610 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
611 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
612 {
613 gdb_byte val[4];
614
615 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
616 val[2] = val[3] = 0;
617 if (i == I387_FOP_REGNUM (tdep))
618 val[1] &= ((1 << 3) - 1);
619 else if (i== I387_FTAG_REGNUM (tdep))
620 {
621 /* The fxsave area contains a simplified version of
622 the tag word. We have to look at the actual 80-bit
623 FP data to recreate the traditional i387 tag word. */
624
625 unsigned long ftag = 0;
626 int fpreg;
627 int top;
628
629 top = ((FXSAVE_ADDR (tdep, regs,
630 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
631 top &= 0x7;
632
633 for (fpreg = 7; fpreg >= 0; fpreg--)
634 {
635 int tag;
636
637 if (val[0] & (1 << fpreg))
638 {
639 int thisreg = (fpreg + 8 - top) % 8
640 + I387_ST0_REGNUM (tdep);
641 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
642 }
643 else
644 tag = 3; /* Empty */
645
646 ftag |= tag << (2 * fpreg);
647 }
648 val[0] = ftag & 0xff;
649 val[1] = (ftag >> 8) & 0xff;
650 }
651 regcache->raw_supply (i, val);
652 }
653 else
654 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
655 }
656
657 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
658 {
659 if (regs == NULL)
660 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL);
661 else
663 FXSAVE_MXCSR_ADDR (regs));
664 }
665}
666
667/* Fill register REGNUM (if it is a floating-point or SSE register) in
668 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
669 all registers. This function doesn't touch any of the reserved
670 bits in *FXSAVE. */
671
672void
673i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
674{
675 gdbarch *arch = regcache->arch ();
676 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
677 gdb_byte *regs = (gdb_byte *) fxsave;
678 int i;
679
680 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
681 gdb_assert (tdep->num_xmm_regs > 0);
682
683 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
684 if (regnum == -1 || regnum == i)
685 {
686 /* Most of the FPU control registers occupy only 16 bits in
687 the fxsave area. Give those a special treatment. */
688 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
689 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
690 {
691 gdb_byte buf[4];
692
693 regcache->raw_collect (i, buf);
694
695 if (i == I387_FOP_REGNUM (tdep))
696 {
697 /* The opcode occupies only 11 bits. Make sure we
698 don't touch the other bits. */
699 buf[1] &= ((1 << 3) - 1);
700 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
701 }
702 else if (i == I387_FTAG_REGNUM (tdep))
703 {
704 /* Converting back is much easier. */
705
706 unsigned short ftag;
707 int fpreg;
708
709 ftag = (buf[1] << 8) | buf[0];
710 buf[0] = 0;
711 buf[1] = 0;
712
713 for (fpreg = 7; fpreg >= 0; fpreg--)
714 {
715 int tag = (ftag >> (fpreg * 2)) & 3;
716
717 if (tag != 3)
718 buf[0] |= (1 << fpreg);
719 }
720 }
721 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
722 }
723 else
724 regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i));
725 }
726
727 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
729 FXSAVE_MXCSR_ADDR (regs));
730}
731
732/* `xstate_bv' is at byte offset 512. */
733#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
734
735/* At xsave_avxh_offset[REGNUM] you'll find the relative offset within
736 the AVX region of the XSAVE extended state where the upper 128bits
737 of GDB register YMM0 + REGNUM is stored. */
738
739static int xsave_avxh_offset[] =
740{
741 0 * 16, /* Upper 128bit of %ymm0 through ... */
742 1 * 16,
743 2 * 16,
744 3 * 16,
745 4 * 16,
746 5 * 16,
747 6 * 16,
748 7 * 16,
749 8 * 16,
750 9 * 16,
751 10 * 16,
752 11 * 16,
753 12 * 16,
754 13 * 16,
755 14 * 16,
756 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
757};
758
759#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
760 (xsave + (tdep)->xsave_layout.avx_offset \
761 + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
762
763/* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset
764 within the ZMM region of the XSAVE extended state where the second
765 128bits of GDB register YMM16 + REGNUM is stored. */
766
768{
769 16 + 0 * 64, /* %ymm16 through... */
770 16 + 1 * 64,
771 16 + 2 * 64,
772 16 + 3 * 64,
773 16 + 4 * 64,
774 16 + 5 * 64,
775 16 + 6 * 64,
776 16 + 7 * 64,
777 16 + 8 * 64,
778 16 + 9 * 64,
779 16 + 10 * 64,
780 16 + 11 * 64,
781 16 + 12 * 64,
782 16 + 13 * 64,
783 16 + 14 * 64,
784 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
785};
786
787#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
788 (xsave + (tdep)->xsave_layout.zmm_offset \
789 + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
790
791/* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset
792 within the ZMM region of the XSAVE extended state where the first
793 128bits of GDB register XMM16 + REGNUM is stored. */
794
796{
797 0 * 64, /* %xmm16 through... */
798 1 * 64,
799 2 * 64,
800 3 * 64,
801 4 * 64,
802 5 * 64,
803 6 * 64,
804 7 * 64,
805 8 * 64,
806 9 * 64,
807 10 * 64,
808 11 * 64,
809 12 * 64,
810 13 * 64,
811 14 * 64,
812 15 * 64 /* ... %xmm31 (128 bits each). */
813};
814
815#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
816 (xsave + (tdep)->xsave_layout.zmm_offset \
817 + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
818
819/* At xsave_bndregs_offset[REGNUM] you'll find the relative offset
820 within the BNDREGS region of the XSAVE extended state where the GDB
821 register BND0R + REGNUM is stored. */
822
823static int xsave_bndregs_offset[] = {
824 0 * 16, /* bnd0r...bnd3r registers. */
825 1 * 16,
826 2 * 16,
827 3 * 16
828};
829
830#define XSAVE_BNDREGS_ADDR(tdep, xsave, regnum) \
831 (xsave + (tdep)->xsave_layout.bndregs_offset \
832 + xsave_bndregs_offset[regnum - I387_BND0R_REGNUM (tdep)])
833
834static int xsave_bndcfg_offset[] = {
835 0 * 8, /* bndcfg ... bndstatus. */
836 1 * 8,
837};
838
839#define XSAVE_BNDCFG_ADDR(tdep, xsave, regnum) \
840 (xsave + (tdep)->xsave_layout.bndcfg_offset \
841 + xsave_bndcfg_offset[regnum - I387_BNDCFGU_REGNUM (tdep)])
842
843/* At xsave_avx512_k_offset[REGNUM] you'll find the relative offset
844 within the K region of the XSAVE extended state where the AVX512
845 opmask register K0 + REGNUM is stored. */
846
848{
849 0 * 8, /* %k0 through... */
850 1 * 8,
851 2 * 8,
852 3 * 8,
853 4 * 8,
854 5 * 8,
855 6 * 8,
856 7 * 8 /* %k7 (64 bits each). */
857};
858
859#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
860 (xsave + (tdep)->xsave_layout.k_offset \
861 + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
862
863
864/* At xsave_avx512_zmm0_h_offset[REGNUM] you find the relative offset
865 within the ZMM_H region of the XSAVE extended state where the upper
866 256bits of the GDB register ZMM0 + REGNUM is stored. */
867
869{
870 0 * 32, /* Upper 256bit of %zmmh0 through... */
871 1 * 32,
872 2 * 32,
873 3 * 32,
874 4 * 32,
875 5 * 32,
876 6 * 32,
877 7 * 32,
878 8 * 32,
879 9 * 32,
880 10 * 32,
881 11 * 32,
882 12 * 32,
883 13 * 32,
884 14 * 32,
885 15 * 32 /* Upper 256bit of... %zmmh15 (256 bits each). */
886};
887
888#define XSAVE_AVX512_ZMM0_H_ADDR(tdep, xsave, regnum) \
889 (xsave + (tdep)->xsave_layout.zmm_h_offset \
890 + xsave_avx512_zmm0_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
891
892/* At xsave_avx512_zmm16_h_offset[REGNUM] you find the relative offset
893 within the ZMM_H region of the XSAVE extended state where the upper
894 256bits of the GDB register ZMM16 + REGNUM is stored. */
895
897{
898 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
899 32 + 1 * 64,
900 32 + 2 * 64,
901 32 + 3 * 64,
902 32 + 4 * 64,
903 32 + 5 * 64,
904 32 + 6 * 64,
905 32 + 7 * 64,
906 32 + 8 * 64,
907 32 + 9 * 64,
908 32 + 10 * 64,
909 32 + 11 * 64,
910 32 + 12 * 64,
911 32 + 13 * 64,
912 32 + 14 * 64,
913 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
914};
915
916#define XSAVE_AVX512_ZMM16_H_ADDR(tdep, xsave, regnum) \
917 (xsave + (tdep)->xsave_layout.zmm_offset \
918 + xsave_avx512_zmm16_h_offset[regnum - I387_ZMM16H_REGNUM (tdep)])
919
920/* At xsave_pkeys_offset[REGNUM] you'll find the relative offset
921 within the PKEYS region of the XSAVE extended state where the PKRU
922 register is stored. */
923
924static int xsave_pkeys_offset[] =
925{
926 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
927 instructions and applications). */
928};
929
930#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
931 (xsave + (tdep)->xsave_layout.pkru_offset \
932 + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
933
934
935/* See i387-tdep.h. */
936
937bool
938i387_guess_xsave_layout (uint64_t xcr0, size_t xsave_size,
939 x86_xsave_layout &layout)
940{
941 if (HAS_PKRU (xcr0) && xsave_size == 2696)
942 {
943 /* Intel CPUs supporting PKRU. */
944 layout.avx_offset = 576;
945 layout.bndregs_offset = 960;
946 layout.bndcfg_offset = 1024;
947 layout.k_offset = 1088;
948 layout.zmm_h_offset = 1152;
949 layout.zmm_offset = 1664;
950 layout.pkru_offset = 2688;
951 }
952 else if (HAS_PKRU (xcr0) && xsave_size == 2440)
953 {
954 /* AMD CPUs supporting PKRU. */
955 layout.avx_offset = 576;
956 layout.k_offset = 832;
957 layout.zmm_h_offset = 896;
958 layout.zmm_offset = 1408;
959 layout.pkru_offset = 2432;
960 }
961 else if (HAS_AVX512 (xcr0) && xsave_size == 2688)
962 {
963 /* Intel CPUs supporting AVX512. */
964 layout.avx_offset = 576;
965 layout.bndregs_offset = 960;
966 layout.bndcfg_offset = 1024;
967 layout.k_offset = 1088;
968 layout.zmm_h_offset = 1152;
969 layout.zmm_offset = 1664;
970 }
971 else if (HAS_MPX (xcr0) && xsave_size == 1088)
972 {
973 /* Intel CPUs supporting MPX. */
974 layout.avx_offset = 576;
975 layout.bndregs_offset = 960;
976 layout.bndcfg_offset = 1024;
977 }
978 else if (HAS_AVX (xcr0) && xsave_size == 832)
979 {
980 /* Intel and AMD CPUs supporting AVX. */
981 layout.avx_offset = 576;
982 }
983 else
984 return false;
985
986 layout.sizeof_xsave = xsave_size;
987 return true;
988}
989
990/* See i387-tdep.h. */
991
992x86_xsave_layout
994{
995 x86_xsave_layout layout;
996
997 if (HAS_PKRU (xcr0))
998 {
999 /* Intel CPUs supporting PKRU. */
1000 layout.avx_offset = 576;
1001 layout.bndregs_offset = 960;
1002 layout.bndcfg_offset = 1024;
1003 layout.k_offset = 1088;
1004 layout.zmm_h_offset = 1152;
1005 layout.zmm_offset = 1664;
1006 layout.pkru_offset = 2688;
1007 layout.sizeof_xsave = 2696;
1008 }
1009 else if (HAS_AVX512 (xcr0))
1010 {
1011 /* Intel CPUs supporting AVX512. */
1012 layout.avx_offset = 576;
1013 layout.bndregs_offset = 960;
1014 layout.bndcfg_offset = 1024;
1015 layout.k_offset = 1088;
1016 layout.zmm_h_offset = 1152;
1017 layout.zmm_offset = 1664;
1018 layout.sizeof_xsave = 2688;
1019 }
1020 else if (HAS_MPX (xcr0))
1021 {
1022 /* Intel CPUs supporting MPX. */
1023 layout.avx_offset = 576;
1024 layout.bndregs_offset = 960;
1025 layout.bndcfg_offset = 1024;
1026 layout.sizeof_xsave = 1088;
1027 }
1028 else if (HAS_AVX (xcr0))
1029 {
1030 /* Intel and AMD CPUs supporting AVX. */
1031 layout.avx_offset = 576;
1032 layout.sizeof_xsave = 832;
1033 }
1034
1035 return layout;
1036}
1037
1038/* Extract from XSAVE a bitset of the features that are available on the
1039 target, but which have not yet been enabled. */
1040
1041ULONGEST
1042i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave)
1043{
1044 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1045 const gdb_byte *regs = (const gdb_byte *) xsave;
1046 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1047
1048 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
1049 ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1050 8, byte_order);
1051
1052 /* Clear part in vector registers if its bit in xstat_bv is zero. */
1053 ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0;
1054
1055 return clear_bv;
1056}
1057
1058/* Similar to i387_supply_fxsave, but use XSAVE extended state. */
1059
1060void
1062 const void *xsave)
1063{
1064 struct gdbarch *gdbarch = regcache->arch ();
1065 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1066 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1067 const gdb_byte *regs = (const gdb_byte *) xsave;
1068 int i;
1069 /* In 64-bit mode the split between "low" and "high" ZMM registers is at
1070 ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all.
1071 Precalculate the number to be used for the split point, with the all
1072 registers in the "low" portion outside of 64-bit mode. */
1073 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1074 + std::min (tdep->num_zmm_regs, 16);
1075 ULONGEST clear_bv;
1076 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
1077 enum
1078 {
1079 none = 0x0,
1080 x87 = 0x1,
1081 sse = 0x2,
1082 avxh = 0x4,
1083 bndregs = 0x8,
1084 bndcfg = 0x10,
1085 avx512_k = 0x20,
1086 avx512_zmm0_h = 0x40,
1087 avx512_zmm16_h = 0x80,
1088 avx512_ymmh_avx512 = 0x100,
1089 avx512_xmm_avx512 = 0x200,
1090 pkeys = 0x400,
1091 all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h
1092 | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1093 } regclass;
1094
1095 gdb_assert (regs != NULL);
1096 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1097 gdb_assert (tdep->num_xmm_regs > 0);
1098
1099 if (regnum == -1)
1100 regclass = all;
1101 else if (regnum >= I387_PKRU_REGNUM (tdep)
1102 && regnum < I387_PKEYSEND_REGNUM (tdep))
1103 regclass = pkeys;
1104 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1105 && regnum < I387_ZMM16H_REGNUM (tdep))
1106 regclass = avx512_zmm0_h;
1107 else if (regnum >= I387_ZMM16H_REGNUM (tdep)
1108 && regnum < I387_ZMMENDH_REGNUM (tdep))
1109 regclass = avx512_zmm16_h;
1110 else if (regnum >= I387_K0_REGNUM (tdep)
1111 && regnum < I387_KEND_REGNUM (tdep))
1112 regclass = avx512_k;
1113 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1115 regclass = avx512_ymmh_avx512;
1116 else if (regnum >= I387_XMM16_REGNUM (tdep)
1118 regclass = avx512_xmm_avx512;
1119 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1120 && regnum < I387_YMMENDH_REGNUM (tdep))
1121 regclass = avxh;
1122 else if (regnum >= I387_BND0R_REGNUM (tdep)
1123 && regnum < I387_BNDCFGU_REGNUM (tdep))
1124 regclass = bndregs;
1125 else if (regnum >= I387_BNDCFGU_REGNUM (tdep)
1126 && regnum < I387_MPXEND_REGNUM (tdep))
1127 regclass = bndcfg;
1128 else if (regnum >= I387_XMM0_REGNUM (tdep)
1129 && regnum < I387_MXCSR_REGNUM (tdep))
1130 regclass = sse;
1131 else if (regnum >= I387_ST0_REGNUM (tdep)
1132 && regnum < I387_FCTRL_REGNUM (tdep))
1133 regclass = x87;
1134 else
1135 regclass = none;
1136
1137 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
1138
1139 /* With the delayed xsave mechanism, in between the program
1140 starting, and the program accessing the vector registers for the
1141 first time, the register's values are invalid. The kernel
1142 initializes register states to zero when they are set the first
1143 time in a program. This means that from the user-space programs'
1144 perspective, it's the same as if the registers have always been
1145 zero from the start of the program. Therefore, the debugger
1146 should provide the same illusion to the user. */
1147
1148 switch (regclass)
1149 {
1150 case none:
1151 break;
1152
1153 case pkeys:
1154 if ((clear_bv & X86_XSTATE_PKRU))
1155 regcache->raw_supply (regnum, zero);
1156 else
1158 return;
1159
1160 case avx512_zmm0_h:
1161 if ((clear_bv & X86_XSTATE_ZMM_H))
1162 regcache->raw_supply (regnum, zero);
1163 else
1165 XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum));
1166 return;
1167
1168 case avx512_zmm16_h:
1169 if ((clear_bv & X86_XSTATE_ZMM))
1170 regcache->raw_supply (regnum, zero);
1171 else
1173 XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum));
1174 return;
1175
1176 case avx512_k:
1177 if ((clear_bv & X86_XSTATE_K))
1178 regcache->raw_supply (regnum, zero);
1179 else
1181 return;
1182
1183 case avx512_ymmh_avx512:
1184 if ((clear_bv & X86_XSTATE_ZMM))
1185 regcache->raw_supply (regnum, zero);
1186 else
1188 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1189 return;
1190
1191 case avx512_xmm_avx512:
1192 if ((clear_bv & X86_XSTATE_ZMM))
1193 regcache->raw_supply (regnum, zero);
1194 else
1196 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1197 return;
1198
1199 case avxh:
1200 if ((clear_bv & X86_XSTATE_AVX))
1201 regcache->raw_supply (regnum, zero);
1202 else
1204 return;
1205
1206 case bndcfg:
1207 if ((clear_bv & X86_XSTATE_BNDCFG))
1208 regcache->raw_supply (regnum, zero);
1209 else
1211 return;
1212
1213 case bndregs:
1214 if ((clear_bv & X86_XSTATE_BNDREGS))
1215 regcache->raw_supply (regnum, zero);
1216 else
1218 return;
1219
1220 case sse:
1221 if ((clear_bv & X86_XSTATE_SSE))
1222 regcache->raw_supply (regnum, zero);
1223 else
1224 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1225 return;
1226
1227 case x87:
1228 if ((clear_bv & X86_XSTATE_X87))
1229 regcache->raw_supply (regnum, zero);
1230 else
1231 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1232 return;
1233
1234 case all:
1235 /* Handle PKEYS registers. */
1236 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1237 {
1238 if ((clear_bv & X86_XSTATE_PKRU))
1239 {
1240 for (i = I387_PKRU_REGNUM (tdep);
1241 i < I387_PKEYSEND_REGNUM (tdep);
1242 i++)
1243 regcache->raw_supply (i, zero);
1244 }
1245 else
1246 {
1247 for (i = I387_PKRU_REGNUM (tdep);
1248 i < I387_PKEYSEND_REGNUM (tdep);
1249 i++)
1250 regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i));
1251 }
1252 }
1253
1254 /* Handle the upper halves of the low 8/16 ZMM registers. */
1255 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1256 {
1257 if ((clear_bv & X86_XSTATE_ZMM_H))
1258 {
1259 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1260 regcache->raw_supply (i, zero);
1261 }
1262 else
1263 {
1264 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1265 regcache->raw_supply (i,
1266 XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i));
1267 }
1268 }
1269
1270 /* Handle AVX512 OpMask registers. */
1271 if ((tdep->xcr0 & X86_XSTATE_K))
1272 {
1273 if ((clear_bv & X86_XSTATE_K))
1274 {
1275 for (i = I387_K0_REGNUM (tdep);
1276 i < I387_KEND_REGNUM (tdep);
1277 i++)
1278 regcache->raw_supply (i, zero);
1279 }
1280 else
1281 {
1282 for (i = I387_K0_REGNUM (tdep);
1283 i < I387_KEND_REGNUM (tdep);
1284 i++)
1285 regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i));
1286 }
1287 }
1288
1289 /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */
1290 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1291 {
1292 if ((clear_bv & X86_XSTATE_ZMM))
1293 {
1294 for (i = I387_ZMM16H_REGNUM (tdep);
1295 i < I387_ZMMENDH_REGNUM (tdep); i++)
1296 regcache->raw_supply (i, zero);
1297 for (i = I387_YMM16H_REGNUM (tdep);
1298 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1299 i++)
1300 regcache->raw_supply (i, zero);
1301 for (i = I387_XMM16_REGNUM (tdep);
1302 i < I387_XMM_AVX512_END_REGNUM (tdep);
1303 i++)
1304 regcache->raw_supply (i, zero);
1305 }
1306 else
1307 {
1308 for (i = I387_ZMM16H_REGNUM (tdep);
1309 i < I387_ZMMENDH_REGNUM (tdep); i++)
1310 regcache->raw_supply (i,
1311 XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i));
1312 for (i = I387_YMM16H_REGNUM (tdep);
1313 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1314 i++)
1315 regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1316 for (i = I387_XMM16_REGNUM (tdep);
1317 i < I387_XMM_AVX512_END_REGNUM (tdep);
1318 i++)
1319 regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1320 }
1321 }
1322 /* Handle the upper YMM registers. */
1323 if ((tdep->xcr0 & X86_XSTATE_AVX))
1324 {
1325 if ((clear_bv & X86_XSTATE_AVX))
1326 {
1327 for (i = I387_YMM0H_REGNUM (tdep);
1328 i < I387_YMMENDH_REGNUM (tdep);
1329 i++)
1330 regcache->raw_supply (i, zero);
1331 }
1332 else
1333 {
1334 for (i = I387_YMM0H_REGNUM (tdep);
1335 i < I387_YMMENDH_REGNUM (tdep);
1336 i++)
1337 regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i));
1338 }
1339 }
1340
1341 /* Handle the MPX registers. */
1342 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1343 {
1344 if (clear_bv & X86_XSTATE_BNDREGS)
1345 {
1346 for (i = I387_BND0R_REGNUM (tdep);
1347 i < I387_BNDCFGU_REGNUM (tdep); i++)
1348 regcache->raw_supply (i, zero);
1349 }
1350 else
1351 {
1352 for (i = I387_BND0R_REGNUM (tdep);
1353 i < I387_BNDCFGU_REGNUM (tdep); i++)
1354 regcache->raw_supply (i, XSAVE_BNDREGS_ADDR (tdep, regs, i));
1355 }
1356 }
1357
1358 /* Handle the MPX registers. */
1359 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1360 {
1361 if (clear_bv & X86_XSTATE_BNDCFG)
1362 {
1363 for (i = I387_BNDCFGU_REGNUM (tdep);
1364 i < I387_MPXEND_REGNUM (tdep); i++)
1365 regcache->raw_supply (i, zero);
1366 }
1367 else
1368 {
1369 for (i = I387_BNDCFGU_REGNUM (tdep);
1370 i < I387_MPXEND_REGNUM (tdep); i++)
1371 regcache->raw_supply (i, XSAVE_BNDCFG_ADDR (tdep, regs, i));
1372 }
1373 }
1374
1375 /* Handle the XMM registers. */
1376 if ((tdep->xcr0 & X86_XSTATE_SSE))
1377 {
1378 if ((clear_bv & X86_XSTATE_SSE))
1379 {
1380 for (i = I387_XMM0_REGNUM (tdep);
1381 i < I387_MXCSR_REGNUM (tdep);
1382 i++)
1383 regcache->raw_supply (i, zero);
1384 }
1385 else
1386 {
1387 for (i = I387_XMM0_REGNUM (tdep);
1388 i < I387_MXCSR_REGNUM (tdep); i++)
1389 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1390 }
1391 }
1392
1393 /* Handle the x87 registers. */
1394 if ((tdep->xcr0 & X86_XSTATE_X87))
1395 {
1396 if ((clear_bv & X86_XSTATE_X87))
1397 {
1398 for (i = I387_ST0_REGNUM (tdep);
1399 i < I387_FCTRL_REGNUM (tdep);
1400 i++)
1401 regcache->raw_supply (i, zero);
1402 }
1403 else
1404 {
1405 for (i = I387_ST0_REGNUM (tdep);
1406 i < I387_FCTRL_REGNUM (tdep);
1407 i++)
1408 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1409 }
1410 }
1411 break;
1412 }
1413
1414 /* Only handle x87 control registers. */
1415 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1416 if (regnum == -1 || regnum == i)
1417 {
1418 if (clear_bv & X86_XSTATE_X87)
1419 {
1420 if (i == I387_FCTRL_REGNUM (tdep))
1421 {
1422 gdb_byte buf[4];
1423
1424 store_unsigned_integer (buf, 4, byte_order,
1425 I387_FCTRL_INIT_VAL);
1426 regcache->raw_supply (i, buf);
1427 }
1428 else if (i == I387_FTAG_REGNUM (tdep))
1429 {
1430 gdb_byte buf[4];
1431
1432 store_unsigned_integer (buf, 4, byte_order, 0xffff);
1433 regcache->raw_supply (i, buf);
1434 }
1435 else
1436 regcache->raw_supply (i, zero);
1437 }
1438 /* Most of the FPU control registers occupy only 16 bits in
1439 the xsave extended state. Give those a special treatment. */
1440 else if (i != I387_FIOFF_REGNUM (tdep)
1441 && i != I387_FOOFF_REGNUM (tdep))
1442 {
1443 gdb_byte val[4];
1444
1445 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1446 val[2] = val[3] = 0;
1447 if (i == I387_FOP_REGNUM (tdep))
1448 val[1] &= ((1 << 3) - 1);
1449 else if (i == I387_FTAG_REGNUM (tdep))
1450 {
1451 /* The fxsave area contains a simplified version of
1452 the tag word. We have to look at the actual 80-bit
1453 FP data to recreate the traditional i387 tag word. */
1454
1455 unsigned long ftag = 0;
1456 int fpreg;
1457 int top;
1458
1459 top = ((FXSAVE_ADDR (tdep, regs,
1460 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1461 top &= 0x7;
1462
1463 for (fpreg = 7; fpreg >= 0; fpreg--)
1464 {
1465 int tag;
1466
1467 if (val[0] & (1 << fpreg))
1468 {
1469 int thisreg = (fpreg + 8 - top) % 8
1470 + I387_ST0_REGNUM (tdep);
1471 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1472 }
1473 else
1474 tag = 3; /* Empty */
1475
1476 ftag |= tag << (2 * fpreg);
1477 }
1478 val[0] = ftag & 0xff;
1479 val[1] = (ftag >> 8) & 0xff;
1480 }
1481 regcache->raw_supply (i, val);
1482 }
1483 else
1484 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1485 }
1486
1487 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1488 {
1489 /* The MXCSR register is placed into the xsave buffer if either the
1490 AVX or SSE features are enabled. */
1491 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1492 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1493 {
1494 gdb_byte buf[4];
1495
1496 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
1497 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
1498 }
1499 else
1501 FXSAVE_MXCSR_ADDR (regs));
1502 }
1503}
1504
1505/* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1506
1507void
1509 void *xsave, int gcore)
1510{
1511 struct gdbarch *gdbarch = regcache->arch ();
1512 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1513 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
1514 gdb_byte *p, *regs = (gdb_byte *) xsave;
1515 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1516 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1517 unsigned int i;
1518 /* See the comment in i387_supply_xsave(). */
1519 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1520 + std::min (tdep->num_zmm_regs, 16);
1521 enum
1522 {
1523 x87_ctrl_or_mxcsr = 0x1,
1524 x87 = 0x2,
1525 sse = 0x4,
1526 avxh = 0x8,
1527 bndregs = 0x10,
1528 bndcfg = 0x20,
1529 avx512_k = 0x40,
1530 avx512_zmm0_h = 0x80,
1531 avx512_zmm16_h = 0x100,
1532 avx512_ymmh_avx512 = 0x200,
1533 avx512_xmm_avx512 = 0x400,
1534 pkeys = 0x800,
1535 all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h
1536 | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1537 } regclass;
1538
1539 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1540 gdb_assert (tdep->num_xmm_regs > 0);
1541
1542 if (regnum == -1)
1543 regclass = all;
1544 else if (regnum >= I387_PKRU_REGNUM (tdep)
1545 && regnum < I387_PKEYSEND_REGNUM (tdep))
1546 regclass = pkeys;
1547 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1548 && regnum < I387_ZMM16H_REGNUM (tdep))
1549 regclass = avx512_zmm0_h;
1550 else if (regnum >= I387_ZMM16H_REGNUM (tdep)
1551 && regnum < I387_ZMMENDH_REGNUM (tdep))
1552 regclass = avx512_zmm16_h;
1553 else if (regnum >= I387_K0_REGNUM (tdep)
1554 && regnum < I387_KEND_REGNUM (tdep))
1555 regclass = avx512_k;
1556 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1558 regclass = avx512_ymmh_avx512;
1559 else if (regnum >= I387_XMM16_REGNUM (tdep)
1561 regclass = avx512_xmm_avx512;
1562 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1563 && regnum < I387_YMMENDH_REGNUM (tdep))
1564 regclass = avxh;
1565 else if (regnum >= I387_BND0R_REGNUM (tdep)
1566 && regnum < I387_BNDCFGU_REGNUM (tdep))
1567 regclass = bndregs;
1568 else if (regnum >= I387_BNDCFGU_REGNUM (tdep)
1569 && regnum < I387_MPXEND_REGNUM (tdep))
1570 regclass = bndcfg;
1571 else if (regnum >= I387_XMM0_REGNUM (tdep)
1572 && regnum < I387_MXCSR_REGNUM (tdep))
1573 regclass = sse;
1574 else if (regnum >= I387_ST0_REGNUM (tdep)
1575 && regnum < I387_FCTRL_REGNUM (tdep))
1576 regclass = x87;
1577 else if ((regnum >= I387_FCTRL_REGNUM (tdep)
1578 && regnum < I387_XMM0_REGNUM (tdep))
1579 || regnum == I387_MXCSR_REGNUM (tdep))
1580 regclass = x87_ctrl_or_mxcsr;
1581 else
1582 internal_error (_("invalid i387 regnum %d"), regnum);
1583
1584 if (gcore)
1585 {
1586 /* Clear XSAVE extended state. */
1587 memset (regs, 0, tdep->xsave_layout.sizeof_xsave);
1588
1589 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1590 if (tdep->xsave_xcr0_offset != -1)
1591 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1592 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1593 }
1594
1595 /* The supported bits in `xstat_bv' are 8 bytes. */
1596 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1597 8, byte_order);
1598 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1599
1600 /* The XSAVE buffer was filled lazily by the kernel. Only those
1601 features that are enabled were written into the buffer, disabled
1602 features left the buffer uninitialised. In order to identify if any
1603 registers have changed we will be comparing the register cache
1604 version to the version in the XSAVE buffer, it is important then that
1605 at this point we initialise to the default values any features in
1606 XSAVE that are not yet initialised.
1607
1608 This could be made more efficient, we know which features (from
1609 REGNUM) we will be potentially updating, and could limit ourselves to
1610 only clearing that feature. However, the extra complexity does not
1611 seem justified at this point. */
1612 if (clear_bv)
1613 {
1614 if ((clear_bv & X86_XSTATE_PKRU))
1615 for (i = I387_PKRU_REGNUM (tdep);
1616 i < I387_PKEYSEND_REGNUM (tdep); i++)
1617 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1618
1619 if ((clear_bv & X86_XSTATE_BNDREGS))
1620 for (i = I387_BND0R_REGNUM (tdep);
1621 i < I387_BNDCFGU_REGNUM (tdep); i++)
1622 memset (XSAVE_BNDREGS_ADDR (tdep, regs, i), 0, 16);
1623
1624 if ((clear_bv & X86_XSTATE_BNDCFG))
1625 for (i = I387_BNDCFGU_REGNUM (tdep);
1626 i < I387_MPXEND_REGNUM (tdep); i++)
1627 memset (XSAVE_BNDCFG_ADDR (tdep, regs, i), 0, 8);
1628
1629 if ((clear_bv & X86_XSTATE_ZMM_H))
1630 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1631 memset (XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i), 0, 32);
1632
1633 if ((clear_bv & X86_XSTATE_K))
1634 for (i = I387_K0_REGNUM (tdep);
1635 i < I387_KEND_REGNUM (tdep); i++)
1636 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1637
1638 if ((clear_bv & X86_XSTATE_ZMM))
1639 {
1640 for (i = I387_ZMM16H_REGNUM (tdep); i < I387_ZMMENDH_REGNUM (tdep);
1641 i++)
1642 memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32);
1643 for (i = I387_YMM16H_REGNUM (tdep);
1644 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1645 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1646 for (i = I387_XMM16_REGNUM (tdep);
1647 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1648 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1649 }
1650
1651 if ((clear_bv & X86_XSTATE_AVX))
1652 for (i = I387_YMM0H_REGNUM (tdep);
1653 i < I387_YMMENDH_REGNUM (tdep); i++)
1654 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1655
1656 if ((clear_bv & X86_XSTATE_SSE))
1657 for (i = I387_XMM0_REGNUM (tdep);
1658 i < I387_MXCSR_REGNUM (tdep); i++)
1659 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1660
1661 /* The mxcsr register is written into the xsave buffer if either AVX
1662 or SSE is enabled, so only clear it if both of those features
1663 require clearing. */
1664 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1665 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1666 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order,
1667 I387_MXCSR_INIT_VAL);
1668
1669 if ((clear_bv & X86_XSTATE_X87))
1670 {
1671 for (i = I387_ST0_REGNUM (tdep);
1672 i < I387_FCTRL_REGNUM (tdep); i++)
1673 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1674
1675 for (i = I387_FCTRL_REGNUM (tdep);
1676 i < I387_XMM0_REGNUM (tdep); i++)
1677 {
1678 if (i == I387_FCTRL_REGNUM (tdep))
1679 store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2,
1680 byte_order, I387_FCTRL_INIT_VAL);
1681 else
1682 memset (FXSAVE_ADDR (tdep, regs, i), 0,
1684 }
1685 }
1686 }
1687
1688 if (regclass == all)
1689 {
1690 /* Check if any PKEYS registers are changed. */
1691 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1692 for (i = I387_PKRU_REGNUM (tdep);
1693 i < I387_PKEYSEND_REGNUM (tdep); i++)
1694 {
1695 regcache->raw_collect (i, raw);
1696 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1697 if (memcmp (raw, p, 4) != 0)
1698 {
1699 xstate_bv |= X86_XSTATE_PKRU;
1700 memcpy (p, raw, 4);
1701 }
1702 }
1703
1704 /* Check if any ZMMH registers are changed. */
1705 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1706 for (i = I387_ZMM16H_REGNUM (tdep);
1707 i < I387_ZMMENDH_REGNUM (tdep); i++)
1708 {
1709 regcache->raw_collect (i, raw);
1710 p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i);
1711 if (memcmp (raw, p, 32) != 0)
1712 {
1713 xstate_bv |= X86_XSTATE_ZMM;
1714 memcpy (p, raw, 32);
1715 }
1716 }
1717
1718 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1719 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1720 {
1721 regcache->raw_collect (i, raw);
1722 p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i);
1723 if (memcmp (raw, p, 32) != 0)
1724 {
1725 xstate_bv |= X86_XSTATE_ZMM_H;
1726 memcpy (p, raw, 32);
1727 }
1728 }
1729
1730 /* Check if any K registers are changed. */
1731 if ((tdep->xcr0 & X86_XSTATE_K))
1732 for (i = I387_K0_REGNUM (tdep);
1733 i < I387_KEND_REGNUM (tdep); i++)
1734 {
1735 regcache->raw_collect (i, raw);
1736 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1737 if (memcmp (raw, p, 8) != 0)
1738 {
1739 xstate_bv |= X86_XSTATE_K;
1740 memcpy (p, raw, 8);
1741 }
1742 }
1743
1744 /* Check if any XMM or upper YMM registers are changed. */
1745 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1746 {
1747 for (i = I387_YMM16H_REGNUM (tdep);
1748 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1749 {
1750 regcache->raw_collect (i, raw);
1751 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1752 if (memcmp (raw, p, 16) != 0)
1753 {
1754 xstate_bv |= X86_XSTATE_ZMM;
1755 memcpy (p, raw, 16);
1756 }
1757 }
1758 for (i = I387_XMM16_REGNUM (tdep);
1759 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1760 {
1761 regcache->raw_collect (i, raw);
1762 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1763 if (memcmp (raw, p, 16) != 0)
1764 {
1765 xstate_bv |= X86_XSTATE_ZMM;
1766 memcpy (p, raw, 16);
1767 }
1768 }
1769 }
1770
1771 /* Check if any upper MPX registers are changed. */
1772 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1773 for (i = I387_BND0R_REGNUM (tdep);
1774 i < I387_BNDCFGU_REGNUM (tdep); i++)
1775 {
1776 regcache->raw_collect (i, raw);
1777 p = XSAVE_BNDREGS_ADDR (tdep, regs, i);
1778 if (memcmp (raw, p, 16))
1779 {
1780 xstate_bv |= X86_XSTATE_BNDREGS;
1781 memcpy (p, raw, 16);
1782 }
1783 }
1784
1785 /* Check if any upper MPX registers are changed. */
1786 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1787 for (i = I387_BNDCFGU_REGNUM (tdep);
1788 i < I387_MPXEND_REGNUM (tdep); i++)
1789 {
1790 regcache->raw_collect (i, raw);
1791 p = XSAVE_BNDCFG_ADDR (tdep, regs, i);
1792 if (memcmp (raw, p, 8))
1793 {
1794 xstate_bv |= X86_XSTATE_BNDCFG;
1795 memcpy (p, raw, 8);
1796 }
1797 }
1798
1799 /* Check if any upper YMM registers are changed. */
1800 if ((tdep->xcr0 & X86_XSTATE_AVX))
1801 for (i = I387_YMM0H_REGNUM (tdep);
1802 i < I387_YMMENDH_REGNUM (tdep); i++)
1803 {
1804 regcache->raw_collect (i, raw);
1805 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1806 if (memcmp (raw, p, 16))
1807 {
1808 xstate_bv |= X86_XSTATE_AVX;
1809 memcpy (p, raw, 16);
1810 }
1811 }
1812
1813 /* Check if any SSE registers are changed. */
1814 if ((tdep->xcr0 & X86_XSTATE_SSE))
1815 for (i = I387_XMM0_REGNUM (tdep);
1816 i < I387_MXCSR_REGNUM (tdep); i++)
1817 {
1818 regcache->raw_collect (i, raw);
1819 p = FXSAVE_ADDR (tdep, regs, i);
1820 if (memcmp (raw, p, 16))
1821 {
1822 xstate_bv |= X86_XSTATE_SSE;
1823 memcpy (p, raw, 16);
1824 }
1825 }
1826
1827 if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE))
1828 {
1829 i = I387_MXCSR_REGNUM (tdep);
1830 regcache->raw_collect (i, raw);
1831 p = FXSAVE_MXCSR_ADDR (regs);
1832 if (memcmp (raw, p, 4))
1833 {
1834 /* Now, we need to mark one of either SSE of AVX as enabled.
1835 We could pick either. What we do is check to see if one
1836 of the features is already enabled, if it is then we leave
1837 it at that, otherwise we pick SSE. */
1838 if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0)
1839 xstate_bv |= X86_XSTATE_SSE;
1840 memcpy (p, raw, 4);
1841 }
1842 }
1843
1844 /* Check if any X87 registers are changed. Only the non-control
1845 registers are handled here, the control registers are all handled
1846 later on in this function. */
1847 if ((tdep->xcr0 & X86_XSTATE_X87))
1848 for (i = I387_ST0_REGNUM (tdep);
1849 i < I387_FCTRL_REGNUM (tdep); i++)
1850 {
1851 regcache->raw_collect (i, raw);
1852 p = FXSAVE_ADDR (tdep, regs, i);
1853 if (memcmp (raw, p, 10))
1854 {
1855 xstate_bv |= X86_XSTATE_X87;
1856 memcpy (p, raw, 10);
1857 }
1858 }
1859 }
1860 else
1861 {
1862 /* Check if REGNUM is changed. */
1863 regcache->raw_collect (regnum, raw);
1864
1865 switch (regclass)
1866 {
1867 default:
1868 internal_error (_("invalid i387 regclass"));
1869
1870 case pkeys:
1871 /* This is a PKEYS register. */
1872 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1873 if (memcmp (raw, p, 4) != 0)
1874 {
1875 xstate_bv |= X86_XSTATE_PKRU;
1876 memcpy (p, raw, 4);
1877 }
1878 break;
1879
1880 case avx512_zmm16_h:
1881 /* This is a ZMM16-31 register. */
1882 p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum);
1883 if (memcmp (raw, p, 32) != 0)
1884 {
1885 xstate_bv |= X86_XSTATE_ZMM;
1886 memcpy (p, raw, 32);
1887 }
1888 break;
1889
1890 case avx512_zmm0_h:
1891 /* This is a ZMM0-15 register. */
1892 p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum);
1893 if (memcmp (raw, p, 32) != 0)
1894 {
1895 xstate_bv |= X86_XSTATE_ZMM_H;
1896 memcpy (p, raw, 32);
1897 }
1898 break;
1899
1900 case avx512_k:
1901 /* This is a AVX512 mask register. */
1902 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1903 if (memcmp (raw, p, 8) != 0)
1904 {
1905 xstate_bv |= X86_XSTATE_K;
1906 memcpy (p, raw, 8);
1907 }
1908 break;
1909
1910 case avx512_ymmh_avx512:
1911 /* This is an upper YMM16-31 register. */
1912 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1913 if (memcmp (raw, p, 16) != 0)
1914 {
1915 xstate_bv |= X86_XSTATE_ZMM;
1916 memcpy (p, raw, 16);
1917 }
1918 break;
1919
1920 case avx512_xmm_avx512:
1921 /* This is an upper XMM16-31 register. */
1922 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1923 if (memcmp (raw, p, 16) != 0)
1924 {
1925 xstate_bv |= X86_XSTATE_ZMM;
1926 memcpy (p, raw, 16);
1927 }
1928 break;
1929
1930 case avxh:
1931 /* This is an upper YMM register. */
1932 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1933 if (memcmp (raw, p, 16))
1934 {
1935 xstate_bv |= X86_XSTATE_AVX;
1936 memcpy (p, raw, 16);
1937 }
1938 break;
1939
1940 case bndregs:
1941 regcache->raw_collect (regnum, raw);
1942 p = XSAVE_BNDREGS_ADDR (tdep, regs, regnum);
1943 if (memcmp (raw, p, 16))
1944 {
1945 xstate_bv |= X86_XSTATE_BNDREGS;
1946 memcpy (p, raw, 16);
1947 }
1948 break;
1949
1950 case bndcfg:
1951 p = XSAVE_BNDCFG_ADDR (tdep, regs, regnum);
1952 xstate_bv |= X86_XSTATE_BNDCFG;
1953 memcpy (p, raw, 8);
1954 break;
1955
1956 case sse:
1957 /* This is an SSE register. */
1958 p = FXSAVE_ADDR (tdep, regs, regnum);
1959 if (memcmp (raw, p, 16))
1960 {
1961 xstate_bv |= X86_XSTATE_SSE;
1962 memcpy (p, raw, 16);
1963 }
1964 break;
1965
1966 case x87:
1967 /* This is an x87 register. */
1968 p = FXSAVE_ADDR (tdep, regs, regnum);
1969 if (memcmp (raw, p, 10))
1970 {
1971 xstate_bv |= X86_XSTATE_X87;
1972 memcpy (p, raw, 10);
1973 }
1974 break;
1975
1976 case x87_ctrl_or_mxcsr:
1977 /* We only handle MXCSR here. All other x87 control registers
1978 are handled separately below. */
1979 if (regnum == I387_MXCSR_REGNUM (tdep))
1980 {
1981 p = FXSAVE_MXCSR_ADDR (regs);
1982 if (memcmp (raw, p, 2))
1983 {
1984 /* We're only setting MXCSR, so check the initial state
1985 to see if either of AVX or SSE are already enabled.
1986 If they are then we'll attribute this changed MXCSR to
1987 that feature. If neither feature is enabled, then
1988 we'll attribute this change to the SSE feature. */
1989 xstate_bv |= (initial_xstate_bv
1990 & (X86_XSTATE_AVX | X86_XSTATE_SSE));
1991 if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0)
1992 xstate_bv |= X86_XSTATE_SSE;
1993 memcpy (p, raw, 2);
1994 }
1995 }
1996 }
1997 }
1998
1999 /* Only handle x87 control registers. */
2000 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
2001 if (regnum == -1 || regnum == i)
2002 {
2003 /* Most of the FPU control registers occupy only 16 bits in
2004 the xsave extended state. Give those a special treatment. */
2005 if (i != I387_FIOFF_REGNUM (tdep)
2006 && i != I387_FOOFF_REGNUM (tdep))
2007 {
2008 gdb_byte buf[4];
2009
2010 regcache->raw_collect (i, buf);
2011
2012 if (i == I387_FOP_REGNUM (tdep))
2013 {
2014 /* The opcode occupies only 11 bits. Make sure we
2015 don't touch the other bits. */
2016 buf[1] &= ((1 << 3) - 1);
2017 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
2018 }
2019 else if (i == I387_FTAG_REGNUM (tdep))
2020 {
2021 /* Converting back is much easier. */
2022
2023 unsigned short ftag;
2024 int fpreg;
2025
2026 ftag = (buf[1] << 8) | buf[0];
2027 buf[0] = 0;
2028 buf[1] = 0;
2029
2030 for (fpreg = 7; fpreg >= 0; fpreg--)
2031 {
2032 int tag = (ftag >> (fpreg * 2)) & 3;
2033
2034 if (tag != 3)
2035 buf[0] |= (1 << fpreg);
2036 }
2037 }
2038 p = FXSAVE_ADDR (tdep, regs, i);
2039 if (memcmp (p, buf, 2))
2040 {
2041 xstate_bv |= X86_XSTATE_X87;
2042 memcpy (p, buf, 2);
2043 }
2044 }
2045 else
2046 {
2047 int regsize;
2048
2049 regcache->raw_collect (i, raw);
2050 regsize = regcache_register_size (regcache, i);
2051 p = FXSAVE_ADDR (tdep, regs, i);
2052 if (memcmp (raw, p, regsize))
2053 {
2054 xstate_bv |= X86_XSTATE_X87;
2055 memcpy (p, raw, regsize);
2056 }
2057 }
2058 }
2059
2060 /* Update the corresponding bits in `xstate_bv' if any
2061 registers are changed. */
2062 if (xstate_bv)
2063 {
2064 /* The supported bits in `xstat_bv' are 8 bytes. */
2065 initial_xstate_bv |= xstate_bv;
2067 8, byte_order,
2068 initial_xstate_bv);
2069 }
2070}
2071
2072/* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
2073 *RAW. */
2074
2075static int
2076i387_tag (const gdb_byte *raw)
2077{
2078 int integer;
2079 unsigned int exponent;
2080 unsigned long fraction[2];
2081
2082 integer = raw[7] & 0x80;
2083 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
2084 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
2085 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
2086 | (raw[5] << 8) | raw[4]);
2087
2088 if (exponent == 0x7fff)
2089 {
2090 /* Special. */
2091 return (2);
2092 }
2093 else if (exponent == 0x0000)
2094 {
2095 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
2096 {
2097 /* Zero. */
2098 return (1);
2099 }
2100 else
2101 {
2102 /* Special. */
2103 return (2);
2104 }
2105 }
2106 else
2107 {
2108 if (integer)
2109 {
2110 /* Valid. */
2111 return (0);
2112 }
2113 else
2114 {
2115 /* Special. */
2116 return (2);
2117 }
2118 }
2119}
2120
2121/* Prepare the FPU stack in REGCACHE for a function return. */
2122
2123void
2125{
2126 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2127 ULONGEST fstat;
2128
2129 /* Set the top of the floating-point register stack to 7. The
2130 actual value doesn't really matter, but 7 is what a normal
2131 function return would end up with if the program started out with
2132 a freshly initialized FPU. */
2134 fstat |= (7 << 11);
2136
2137 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
2138 floating-point register stack to 7, the appropriate value for the
2139 tag word is 0x3fff. */
2141
2142}
2143
2144/* See i387-tdep.h. */
2145
2146void
2148{
2149 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
2150
2151 if (I387_BND0R_REGNUM (tdep) > 0)
2152 {
2153 gdb_byte bnd_buf[16];
2154
2155 memset (bnd_buf, 0, 16);
2156 for (int i = 0; i < I387_NUM_BND_REGS; i++)
2157 regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf);
2158 }
2159}
int regnum
gdbarch * arch() const
Definition regcache.c:231
void raw_collect(int regnum, void *buf) const override
Definition regcache.c:1127
void raw_supply(int regnum, const void *buf) override
Definition regcache.c:1062
void raw_write(int regnum, const gdb_byte *buf)
Definition regcache.c:833
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition defs.h:515
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition defs.h:480
struct value * get_frame_register_value(frame_info_ptr frame, int regnum)
Definition frame.c:1333
bool read_frame_register_unsigned(frame_info_ptr frame, int regnum, ULONGEST *val)
Definition frame.c:1405
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition frame.c:3027
bool get_frame_register_bytes(frame_info_ptr frame, int regnum, CORE_ADDR offset, gdb::array_view< gdb_byte > buffer, int *optimizedp, int *unavailablep)
Definition frame.c:1480
void put_frame_register(frame_info_ptr frame, int regnum, const gdb_byte *buf)
Definition frame.c:1426
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition gdbarch.c:1396
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition gnu-nat.c:1790
int i386_fp_regnum_p(struct gdbarch *gdbarch, int regnum)
Definition i386-tdep.c:373
struct type * i387_ext_type(struct gdbarch *gdbarch)
Definition i386-tdep.c:3152
#define I386_MAX_REGISTER_SIZE
Definition i386-tdep.h:355
@ I386_ST0_REGNUM
Definition i386-tdep.h:297
#define XSAVE_XSTATE_BV_ADDR(xsave)
Definition i387-tdep.c:733
void i387_value_to_register(frame_info_ptr frame, int regnum, struct type *type, const gdb_byte *from)
Definition i387-tdep.c:383
#define XSAVE_AVX512_ZMM16_H_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:916
ULONGEST i387_xsave_get_clear_bv(struct gdbarch *gdbarch, const void *xsave)
Definition i387-tdep.c:1042
static void print_i387_ext(struct gdbarch *gdbarch, const gdb_byte *raw, struct ui_file *file)
Definition i387-tdep.c:51
void i387_supply_xsave(struct regcache *regcache, int regnum, const void *xsave)
Definition i387-tdep.c:1061
static int xsave_xmm_avx512_offset[]
Definition i387-tdep.c:795
#define XSAVE_AVXH_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:759
static int xsave_avx512_k_offset[]
Definition i387-tdep.c:847
#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:815
static int xsave_bndcfg_offset[]
Definition i387-tdep.c:834
bool i387_guess_xsave_layout(uint64_t xcr0, size_t xsave_size, x86_xsave_layout &layout)
Definition i387-tdep.c:938
#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:930
#define XSAVE_BNDCFG_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:839
void i387_supply_fxsave(struct regcache *regcache, int regnum, const void *fxsave)
Definition i387-tdep.c:589
static int xsave_ymm_avx512_offset[]
Definition i387-tdep.c:767
#define FXSAVE_ADDR(tdep, fxsave, regnum)
Definition i387-tdep.c:571
#define FXSAVE_MXCSR_ADDR(fxsave)
Definition i387-tdep.c:579
x86_xsave_layout i387_fallback_xsave_layout(uint64_t xcr0)
Definition i387-tdep.c:993
static int fxsave_offset[]
Definition i387-tdep.c:535
void i387_collect_fxsave(const struct regcache *regcache, int regnum, void *fxsave)
Definition i387-tdep.c:673
void i387_collect_xsave(const struct regcache *regcache, int regnum, void *xsave, int gcore)
Definition i387-tdep.c:1508
#define FSAVE_ADDR(tdep, fsave, regnum)
Definition i387-tdep.c:431
#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:787
void i387_reset_bnd_regs(struct gdbarch *gdbarch, struct regcache *regcache)
Definition i387-tdep.c:2147
static int xsave_avx512_zmm16_h_offset[]
Definition i387-tdep.c:896
int i387_convert_register_p(struct gdbarch *gdbarch, int regnum, struct type *type)
Definition i387-tdep.c:327
void i387_supply_fsave(struct regcache *regcache, int regnum, const void *fsave)
Definition i387-tdep.c:440
void i387_collect_fsave(const struct regcache *regcache, int regnum, void *fsave)
Definition i387-tdep.c:495
static int xsave_avx512_zmm0_h_offset[]
Definition i387-tdep.c:868
void i387_return_value(struct gdbarch *gdbarch, struct regcache *regcache)
Definition i387-tdep.c:2124
#define XSAVE_BNDREGS_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:830
static int i387_tag(const gdb_byte *raw)
Definition i387-tdep.c:2076
static void print_i387_control_word(int control_p, unsigned int control, struct ui_file *file)
Definition i387-tdep.c:143
static int xsave_avxh_offset[]
Definition i387-tdep.c:739
#define XSAVE_AVX512_ZMM0_H_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:888
static void print_i387_status_word(int status_p, unsigned int status, struct ui_file *file)
Definition i387-tdep.c:105
int i387_register_to_value(frame_info_ptr frame, int regnum, struct type *type, gdb_byte *to, int *optimizedp, int *unavailablep)
Definition i387-tdep.c:348
static int xsave_pkeys_offset[]
Definition i387-tdep.c:924
static int fsave_offset[]
Definition i387-tdep.c:411
static void print_i387_value(struct gdbarch *gdbarch, const gdb_byte *raw, struct ui_file *file)
Definition i387-tdep.c:36
static int xsave_bndregs_offset[]
Definition i387-tdep.c:823
#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum)
Definition i387-tdep.c:859
void i387_print_float_info(struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, const char *args)
Definition i387-tdep.c:204
#define I387_K0_REGNUM(tdep)
Definition i387-tdep.h:51
#define I387_XMM0_REGNUM(tdep)
Definition i387-tdep.h:66
#define I387_ST0_REGNUM(tdep)
Definition i387-tdep.h:33
#define I387_KEND_REGNUM(tdep)
Definition i387-tdep.h:77
#define I387_FOOFF_REGNUM(tdep)
Definition i387-tdep.h:64
#define I387_XMM16_REGNUM(tdep)
Definition i387-tdep.h:67
#define I387_PKEYSEND_REGNUM(tdep)
Definition i387-tdep.h:86
#define I387_BND0R_REGNUM(tdep)
Definition i387-tdep.h:40
#define I387_NUM_BND_REGS
Definition i387-tdep.h:45
#define I387_YMM16H_REGNUM(tdep)
Definition i387-tdep.h:56
#define I387_XMM_AVX512_END_REGNUM(tdep)
Definition i387-tdep.h:83
#define I387_FSTAT_REGNUM(tdep)
Definition i387-tdep.h:59
#define I387_FOP_REGNUM(tdep)
Definition i387-tdep.h:65
#define I387_ZMM16H_REGNUM(tdep)
Definition i387-tdep.h:54
#define I387_FCTRL_REGNUM(tdep)
Definition i387-tdep.h:58
#define I387_FOSEG_REGNUM(tdep)
Definition i387-tdep.h:63
#define I387_MXCSR_REGNUM(tdep)
Definition i387-tdep.h:68
#define I387_YMM0H_REGNUM(tdep)
Definition i387-tdep.h:38
#define I387_FISEG_REGNUM(tdep)
Definition i387-tdep.h:61
#define I387_BNDCFGU_REGNUM(tdep)
Definition i387-tdep.h:41
#define I387_ZMMENDH_REGNUM(tdep)
Definition i387-tdep.h:79
#define I387_PKRU_REGNUM(tdep)
Definition i387-tdep.h:50
#define I387_YMMH_AVX512_END_REGNUM(tdep)
Definition i387-tdep.h:81
#define I387_ZMM0H_REGNUM(tdep)
Definition i387-tdep.h:53
#define I387_FTAG_REGNUM(tdep)
Definition i387-tdep.h:60
#define I387_YMMENDH_REGNUM(tdep)
Definition i387-tdep.h:71
#define I387_MPXEND_REGNUM(tdep)
Definition i387-tdep.h:74
#define I387_FIOFF_REGNUM(tdep)
Definition i387-tdep.h:62
@ all
int regcache_register_size(const struct regcache *regcache, int n)
Definition regcache.c:183
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:649
int register_size(struct gdbarch *gdbarch, int regnum)
Definition regcache.c:170
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:677
x86_xsave_layout xsave_layout
Definition i386-tdep.h:150
type_code code() const
Definition gdbtypes.h:956
Definition value.h:130
gdb::array_view< const gdb_byte > contents()
Definition value.c:1262
bool entirely_available()
Definition value.c:209
void target_float_convert(const gdb_byte *from, const struct type *from_type, gdb_byte *to, const struct type *to_type)
std::string target_float_to_string(const gdb_byte *addr, const struct type *type, const char *format)
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition utils.c:1886
void gdb_puts(const char *linebuffer, struct ui_file *stream)
Definition utils.c:1809