42#include "xtensa-isa.h"
44#include "xtensa-config.h"
50#define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 gdb_printf (gdb_stdlog, "(warn ) " args)
54#define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 gdb_printf (gdb_stdlog, "(info ) " args)
58#define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 gdb_printf (gdb_stdlog, "(trace) " args)
62#define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 gdb_printf (gdb_stdlog, "(verb ) " args)
68#define SP_ALIGNMENT 16
73#define ARGS_NUM_REGS 6
74#define REGISTER_SIZE 4
78#define PS_CALLINC_SHIFT 16
79#define PS_CALLINC_MASK 0x00030000
80#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
89#define ARG_NOF(tdep) \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92#define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
100#define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
104#define XTENSA_ENTRY_LENGTH 3
110#define PS_WOE (1<<18)
114#define XTENSA_MAX_REGISTER_SIZE 64
136 arreg = a_regnum - tdep->
a0_base;
151 areg = ar_regnum - tdep->
ar_base;
154 areg = (areg - wb * 4) & (tdep->
num_aregs - 1);
155 return (areg > 15) ? -1 : areg;
165 return (
unsigned long)
value;
194 DEBUGTRACE (
"extract_call_winsize (pc = 0x%08x)\n", (
int) pc);
208 if (byte_order == BFD_ENDIAN_LITTLE)
210 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
211 winsize = (insn & 0x30) >> 2;
215 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
216 winsize = (insn >> 16) & 0xc;
257 && regnum < tdep->ar_base + tdep->
num_aregs)
259 && regnum < tdep->a0_base + 16))
309 std::string
name = string_printf (
"int%d",
size * 8);
326 internal_error (_(
"invalid register number %d"),
regnum);
367 unsigned int *ptr =
value;
368 unsigned int regval, m, mem = 0;
371 int bitsize = bytesize * 8;
374 DEBUGTRACE (
"xtensa_register_write_masked ()\n");
378 for (i = 0; i < bytesize; i++)
381 mem |= (buffer[bytesize - i - 1] << 24);
386 for (i = 0; i < bytesize; i++)
389 mem |= (buffer[i] << 24);
398 *ptr = mem >> (((0 - bytesize) & 3) * 8);
403 for (i = 0; i < mask->count; i++)
405 start = mask->mask[i].bit_start;
406 size = mask->mask[i].bit_size;
407 regval = mem >> shift;
409 if ((shift +=
size) > bitsize)
410 error (_(
"size of all masks is larger than the register"));
419 regval |= mem << (
size - shift);
423 r = mask->mask[i].reg_num;
424 if (r >= 0 &&
size > 0)
429 m = 0xffffffff >> (32 -
size) << start;
431 regval = (regval & m) | (old_val & ~m);
441static enum register_status
451 unsigned int *ptr =
value;
452 unsigned int regval, mem = 0;
455 int bitsize = bytesize * 8;
458 DEBUGTRACE (
"xtensa_register_read_masked (reg \"%s\", ...)\n",
462 for (i = 0; i < mask->count; i++)
464 int r = mask->mask[i].reg_num;
467 enum register_status
status;
473 regval = (
unsigned int) val;
478 start = mask->mask[i].bit_start;
479 size = mask->mask[i].bit_size;
484 regval &= (0xffffffff >> (32 -
size));
486 mem |= regval << shift;
488 if ((shift +=
size) > bitsize)
489 error (_(
"size of all masks is larger than the register"));
500 mem = regval >> (
size - shift);
512 for (i = 0; i < bytesize; i++)
516 buffer[bytesize - i - 1] = mem & 0xff;
520 for (i = 0; i < bytesize; i++)
524 buffer[i] = mem & 0xff;
534static enum register_status
540 DEBUGTRACE (
"xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
547 && (regnum <= tdep->a0_base + 15))
550 enum register_status
status;
567 || regnum < tdep->a0_base)
569 buffer[0] = (gdb_byte)0;
570 buffer[1] = (gdb_byte)0;
571 buffer[2] = (gdb_byte)0;
572 buffer[3] = (gdb_byte)0;
587 warning (_(
"cannot read register %s"),
599 warning (_(
"cannot read register"));
606 warning (_(
"cannot read register"));
619 internal_error (_(
"invalid register number %d"),
regnum);
629 const gdb_byte *buffer)
631 DEBUGTRACE (
"xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
638 && (regnum <= tdep->a0_base + 15))
654 else if (regnum < tdep->a0_base)
671 warning (_(
"cannot write register %s"),
683 warning (_(
"cannot write register"));
691 warning (_(
"cannot write register"));
707 internal_error (_(
"invalid register number %d"),
regnum);
753#define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
754 | XTENSA_REGISTER_FLAGS_WRITABLE \
755 | XTENSA_REGISTER_FLAGS_VOLATILE)
757#define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
758 | XTENSA_REGISTER_FLAGS_WRITABLE)
836 (
char *) ®s->
lbeg);
839 (
char *) ®s->
lend);
845 (
char *) ®s->
sar);
847 && regnum < tdep->ar_base
855 (
char *) ®s->
ar[i]);
878 DEBUGTRACE (
"xtensa_iterate_over_regset_sections\n");
888#define XTENSA_NUM_SAVED_AREGS 12
988 cache->
call0 = !windowed;
1022 return address & ~15;
1032 DEBUGTRACE (
"xtensa_unwind_pc (next_frame = %s)\n",
1033 host_address_to_string (next_frame.
get ()));
1038 DEBUGINFO (
"[xtensa_unwind_pc] pc = 0x%08x\n", (
unsigned int)
pc);
1054 (this_frame, tdep->
a0_base + 1);
1070 if (byte_order == BFD_ENDIAN_BIG)
1073 code = insn & 0xf000ff00;
1074 if ((
code == 0x00009000) || (
code == 0x00009400))
1077 code = insn & 0xffffff00;
1078 return ((
code == 0x00430000) || (
code == 0x00530000));
1083 code = insn & 0x00ff000f;
1084 if ((
code == 0x090000) || (
code == 0x490000))
1087 code = insn & 0x00ffffff;
1088 return ((
code == 0x00003400) || (
code == 0x00003500));
1095#define XTENSA_ISA_BSZ 32
1096#define XTENSA_ISA_BADPC ((CORE_ADDR)0)
1101#define RETURN_FP goto done
1105 CORE_ADDR start_addr;
1107 xtensa_insnbuf ins, slot;
1109 CORE_ADDR ia, bt, ba;
1111 int ilen, islots, is;
1113 const char *opcname;
1116 if (start_addr == 0)
1121 ins = xtensa_insnbuf_alloc (isa);
1122 slot = xtensa_insnbuf_alloc (isa);
1125 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1127 if (ia + xtensa_isa_maxlength (isa) > bt)
1136 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1137 ifmt = xtensa_format_decode (isa, ins);
1138 if (ifmt == XTENSA_UNDEFINED)
1140 ilen = xtensa_format_length (isa, ifmt);
1141 if (ilen == XTENSA_UNDEFINED)
1143 islots = xtensa_format_num_slots (isa, ifmt);
1144 if (islots == XTENSA_UNDEFINED)
1147 for (is = 0; is < islots; ++is)
1149 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1152 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1153 if (opc == XTENSA_UNDEFINED)
1156 opcname = xtensa_opcode_name (isa, opc);
1158 if (strcasecmp (opcname,
"mov.n") == 0
1159 || strcasecmp (opcname,
"or") == 0)
1161 unsigned int register_operand;
1166 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1167 is, slot, ®ister_operand) != 0)
1169 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1171 if (register_operand == 1)
1173 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1174 ®ister_operand) != 0)
1176 if (xtensa_operand_decode (isa, opc, 0,
1177 ®ister_operand) != 0)
1181 = tdep->
a0_base + register_operand;
1189 || strcasecmp (opcname,
"ill") == 0
1190 || strcasecmp (opcname,
"ill.n") == 0
1192 || strcasecmp (opcname,
"break") == 0
1193 || strcasecmp (opcname,
"break.n") == 0
1195 || xtensa_opcode_is_branch (isa, opc) > 0
1196 || xtensa_opcode_is_jump (isa, opc) > 0
1197 || xtensa_opcode_is_loop (isa, opc) > 0
1198 || xtensa_opcode_is_call (isa, opc) > 0
1199 || strcasecmp (opcname,
"simcall") == 0
1200 || strcasecmp (opcname,
"syscall") == 0)
1206 xtensa_insnbuf_free(isa, slot);
1207 xtensa_insnbuf_free(isa, ins);
1230 CORE_ADDR
ra, wb, ws,
pc, sp,
ps;
1234 int windowed, ps_regnum;
1241 ps = (ps_regnum >= 0
1248 *this_cache = cache;
1266 (this_frame, tdep->
a0_base + callinc * 4);
1273 (this_frame, tdep->
a0_base + 1);
1282 cache->
ra = (cache->
pc & 0xc0000000) | (ra & 0x3fffffff);
1283 cache->
ps = (ps & ~PS_CALLINC_MASK)
1296 cache->
wd.
ws = ws & ~(1 << wb);
1299 cache->
ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1300 cache->
ps = (ps & ~PS_CALLINC_MASK)
1304 if (cache->
wd.
ws == 0)
1310 (this_frame, tdep->
a0_base + 1) - 16;
1312 for (i = 0; i < 4; i++, sp += 4)
1326 for ( i = 4; i < cache->
wd.
callsize; i++, sp += 4)
1333 if ((cache->
prev_sp == 0) && ( ra != 0 ))
1337 if ((cache->
wd.
ws & (1 << cache->
wd.
wb)) == 0)
1342 (this_frame, tdep->
a0_base + 1);
1385\nUnrecognised function prologue. Stack trace cannot be resolved. \
1386This message will not be repeated in this session.\n"));
1417 if (*this_cache == NULL)
1425 else if (!cache->
call0)
1447 && regnum <= tdep->a0_base + 15)
1459 && cache->
wd.
aregs[areg] != -1)
1534 bfd_byte *valbuf = (bfd_byte *) dst;
1540 DEBUGTRACE (
"xtensa_extract_return_value (...)\n");
1542 gdb_assert(len > 0);
1552 if (len > (callsize > 8 ? 8 : 16))
1553 internal_error (_(
"cannot extract return value of %d bytes long"),
1561 tdep->
a0_base + 2 + callsize, wb);
1569 DEBUGINFO (
"[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1574 for (; len > 0; len -= 4, areg++, valbuf += 4)
1590 const bfd_byte *valbuf = (
const bfd_byte *) dst;
1597 DEBUGTRACE (
"xtensa_store_return_value (...)\n");
1607 if (len > (callsize > 8 ? 8 : 16))
1608 internal_error (_(
"unimplemented for this length: %s"),
1611 tdep->
a0_base + 2 + callsize, wb);
1613 DEBUGTRACE (
"[xtensa_store_return_value] callsize %d wb %d\n",
1614 callsize, (
int) wb);
1624 for (; len > 0; len -= 4, areg++, valbuf += 4)
1636 struct value *function,
1637 struct type *valtype,
1640 const gdb_byte *writebuf)
1645 || valtype->
code () == TYPE_CODE_UNION
1646 || valtype->
code () == TYPE_CODE_ARRAY)
1647 && valtype->
length () > 16);
1654 if (writebuf != NULL)
1659 if (readbuf != NULL)
1672 struct value *function,
1676 struct value **args,
1679 CORE_ADDR struct_addr)
1683 int size, onstack_size;
1684 gdb_byte *buf = (gdb_byte *) alloca (16);
1686 struct argument_info
1688 const bfd_byte *contents;
1699 struct argument_info *arg_info =
1700 (
struct argument_info *) alloca (nargs *
sizeof (
struct argument_info));
1704 DEBUGTRACE (
"xtensa_push_dummy_call (...)\n");
1708 DEBUGINFO (
"[xtensa_push_dummy_call] nargs = %d\n", nargs);
1709 DEBUGINFO (
"[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1710 "struct_addr=0x%x\n",
1711 (
int) sp, (
int) return_method, (
int) struct_addr);
1713 for (
int i = 0; i < nargs; i++)
1715 struct value *arg = args[i];
1718 host_address_to_string (arg),
1719 pulongest (arg_type->
length ()));
1720 switch (arg_type->
code ())
1725 case TYPE_CODE_STRUCT:
1733 host_address_to_string (arg->
contents ().data ()));
1748 for (
int i = 0; i < nargs; i++)
1750 struct argument_info *info = &arg_info[i];
1751 struct value *arg = args[i];
1754 switch (arg_type->
code ())
1757 case TYPE_CODE_BOOL:
1758 case TYPE_CODE_CHAR:
1759 case TYPE_CODE_RANGE:
1760 case TYPE_CODE_ENUM:
1770 info->align = arg_type->
length ();
1783 case TYPE_CODE_STRUCT:
1788 info->length = arg_type->
length ();
1789 info->contents = arg->
contents ().data ();
1792 size = (
size + info->align - 1) & ~(info->align - 1);
1793 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1798 info->u.offset = onstack_size;
1799 onstack_size += info->length;
1806 size += info->length;
1828 for (
int i = 0; i < nargs; i++)
1830 struct argument_info *info = &arg_info[i];
1834 int n = info->length;
1835 CORE_ADDR offset = sp + info->u.offset;
1850 int n = info->length;
1851 const bfd_byte *cp = info->contents;
1852 int r = info->u.regno;
1893 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1895 ps = (
unsigned long) val & ~0x00030000;
1943#define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1944#define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1945#define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1946#define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1950static const gdb_byte *
1968 static unsigned char density_little_breakpoint[]
1972 return density_big_breakpoint;
1974 return density_little_breakpoint;
1983call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
1985#define RETURN_RET goto done
1987 xtensa_insnbuf ins, slot;
1989 CORE_ADDR ia, bt, ba;
1991 int ilen, islots, is;
1993 const char *opcname;
1998 ins = xtensa_insnbuf_alloc (isa);
1999 slot = xtensa_insnbuf_alloc (isa);
2002 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2004 if (ia + xtensa_isa_maxlength (isa) > bt)
2013 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2014 ifmt = xtensa_format_decode (isa, ins);
2015 if (ifmt == XTENSA_UNDEFINED)
2017 ilen = xtensa_format_length (isa, ifmt);
2018 if (ilen == XTENSA_UNDEFINED)
2020 islots = xtensa_format_num_slots (isa, ifmt);
2021 if (islots == XTENSA_UNDEFINED)
2024 for (is = 0; is < islots; ++is)
2026 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2029 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2030 if (opc == XTENSA_UNDEFINED)
2033 opcname = xtensa_opcode_name (isa, opc);
2035 if ((strcasecmp (opcname,
"ret.n") == 0)
2036 || (strcasecmp (opcname,
"ret") == 0))
2044 xtensa_insnbuf_free(isa, slot);
2045 xtensa_insnbuf_free(isa, ins);
2082 char ch = *opcname++;
2084 if ((ch !=
'r') && (ch !=
'w') && (ch !=
'x'))
2086 if (*opcname++ !=
's')
2088 if (*opcname++ !=
'r')
2090 if (*opcname++ !=
'.')
2101 const char *opcname;
2104 DEBUGTRACE (
"call0_classify_opcode (..., opc = %d)\n", opc);
2108 opcname = xtensa_opcode_name (isa, opc);
2111 || strcasecmp (opcname,
"ill") == 0
2112 || strcasecmp (opcname,
"ill.n") == 0)
2114 else if (strcasecmp (opcname,
"break") == 0
2115 || strcasecmp (opcname,
"break.n") == 0)
2117 else if (strcasecmp (opcname,
"entry") == 0)
2119 else if (strcasecmp (opcname,
"rfwo") == 0)
2121 else if (strcasecmp (opcname,
"rfwu") == 0)
2123 else if (xtensa_opcode_is_branch (isa, opc) > 0
2124 || xtensa_opcode_is_jump (isa, opc) > 0
2125 || xtensa_opcode_is_loop (isa, opc) > 0
2126 || xtensa_opcode_is_call (isa, opc) > 0
2127 || strcasecmp (opcname,
"simcall") == 0
2128 || strcasecmp (opcname,
"syscall") == 0)
2132 else if (strcasecmp (opcname,
"add") == 0
2133 || strcasecmp (opcname,
"add.n") == 0)
2135 else if (strcasecmp (opcname,
"and") == 0)
2137 else if (strcasecmp (opcname,
"addi") == 0
2138 || strcasecmp (opcname,
"addi.n") == 0
2139 || strcasecmp (opcname,
"addmi") == 0)
2141 else if (strcasecmp (opcname,
"sub") == 0)
2143 else if (strcasecmp (opcname,
"mov.n") == 0
2144 || strcasecmp (opcname,
"or") == 0)
2146 else if (strcasecmp (opcname,
"movi") == 0
2147 || strcasecmp (opcname,
"movi.n") == 0)
2149 else if (strcasecmp (opcname,
"l32r") == 0)
2151 else if (strcasecmp (opcname,
"s32i") == 0
2152 || strcasecmp (opcname,
"s32i.n") == 0)
2154 else if (strcasecmp (opcname,
"l32e") == 0)
2156 else if (strcasecmp (opcname,
"s32e") == 0)
2177 unsigned litbase, litaddr, litval;
2184 gdb_assert (nods == 3);
2190 gdb_assert (nods == 3);
2191 if (src[odv[1]].fr_reg ==
C0_CONST)
2196 else if (src[odv[2]].fr_reg ==
C0_CONST)
2205 gdb_assert (nods == 3);
2209 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2211 if (src[odv[2]].fr_reg ==
C0_CONST)
2215 else if ((src[odv[0]].fr_reg == spreg)
2216 && (src[odv[2]].fr_reg == spreg))
2218 if (src[odv[1]].fr_reg ==
C0_CONST)
2224 if (src[odv[1]].fr_reg ==
C0_CONST)
2229 else if (src[odv[2]].fr_reg ==
C0_CONST)
2238 gdb_assert (nods == 3);
2239 if (src[odv[2]].fr_reg ==
C0_CONST)
2248 gdb_assert (nods == 2);
2261 gdb_assert (nods == 2);
2263 dst[odv[0]].
fr_ofs = odv[1];
2267 gdb_assert (nods == 2);
2272 litaddr = litbase & 1
2273 ? (litbase & ~1) + (
signed)odv[1]
2274 : (pc + 3 + (signed)odv[1]) & ~3;
2277 dst[odv[0]].
fr_ofs = litval;
2281 gdb_assert (nods == 3 && spreg >= 0 && spreg <
C0_NREGS);
2285 && (odv[1] == spreg)
2289 if (src[odv[1]].fr_reg == spreg
2290 && (src[odv[1]].fr_ofs & 3) == 0
2291 && src[odv[0]].fr_reg >= 0
2292 && src[odv[0]].fr_ofs == 0
2293 && src[src[odv[0]].fr_reg].to_stk ==
C0_NOSTK)
2296 gdb_assert ((odv[2] & 3) == 0);
2341 CORE_ADDR start, CORE_ADDR pc,
2349 xtensa_insnbuf ins, slot;
2351 int ilen, islots, is;
2364 DEBUGTRACE (
"call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2365 (
int)start, (
int)
pc);
2381 if (prologue_sal.
line != 0)
2382 body_pc = prologue_sal.
end;
2389 body_pc = std::min (end_pc, body_pc);
2392 body_pc = std::min (
pc, body_pc);
2399 ins = xtensa_insnbuf_alloc (isa);
2400 slot = xtensa_insnbuf_alloc (isa);
2402 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2408 if (ia + xtensa_isa_maxlength (isa) > bt)
2413 error (_(
"Unable to read target memory ..."));
2418 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2419 ifmt = xtensa_format_decode (isa, ins);
2420 if (ifmt == XTENSA_UNDEFINED)
2425 ilen = xtensa_format_length (isa, ifmt);
2426 if (ilen == XTENSA_UNDEFINED)
2431 islots = xtensa_format_num_slots (isa, ifmt);
2432 if (islots == XTENSA_UNDEFINED)
2442 for (j = 0; j < nregs; ++j)
2445 for (is = 0; is < islots; ++is)
2449 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2453 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2454 DEBUGVERB (
"[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2456 if (opc == XTENSA_UNDEFINED)
2489 nods = xtensa_opcode_num_operands (isa, opc);
2490 if (nods == XTENSA_UNDEFINED)
2498 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2503 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2511 if (odv[2] == odv[1])
2514 if ((odv[0] == 1) && (odv[1] != 1))
2528 opclass, nods, odv, ia, 1, cache);
2534 DEBUGVERB (
"[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2535 (
unsigned)ia, fail ?
"failed" :
"succeeded");
2536 xtensa_insnbuf_free(isa, slot);
2537 xtensa_insnbuf_free(isa, ins);
2550 CORE_ADDR body_pc=UINT_MAX;
2551 CORE_ADDR sp, fp, ra;
2552 int fp_regnum =
C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2556 (this_frame, tdep->
a0_base + 1);
2570 goto finish_frame_analysis;
2605 CORE_ADDR unaligned_sp;
2613 goto finish_frame_analysis;
2622 unaligned_sp = (CORE_ADDR)
2625 prev_sp = unaligned_sp + c0_frmsz;
2628 prev_sp = fp + c0_frmsz;
2637 c0_frmsz += fp - sp;
2684 finish_frame_analysis:
2685 cache->
pc = start_pc;
2688 cache->
prev_sp = (ra != 0) ? prev_sp : 0;
2710 unsigned int spilled_value
2747#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2762 xtensa_insnbuf ins, slot;
2764 CORE_ADDR ia, bt, ba;
2766 int ilen, islots, is;
2769 void (*
func) (
struct gdbarch *, int, int, int, CORE_ADDR);
2772 uint32_t at, as, offset;
2775 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2779 ins = xtensa_insnbuf_alloc (isa);
2780 slot = xtensa_insnbuf_alloc (isa);
2791 if (ia + xtensa_isa_maxlength (isa) > bt)
2798 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2799 ifmt = xtensa_format_decode (isa, ins);
2800 if (ifmt == XTENSA_UNDEFINED)
2802 ilen = xtensa_format_length (isa, ifmt);
2803 if (ilen == XTENSA_UNDEFINED)
2805 islots = xtensa_format_num_slots (isa, ifmt);
2806 if (islots == XTENSA_UNDEFINED)
2808 for (is = 0; is < islots; ++is)
2810 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2812 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2813 if (opc == XTENSA_UNDEFINED)
2844 if (WindowUnderflow12)
2867 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2869 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2871 if (xtensa_operand_decode (isa, opc, 0, &at))
2873 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2875 if (xtensa_operand_decode (isa, opc, 1, &as))
2877 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2879 if (xtensa_operand_decode (isa, opc, 2, &offset))
2882 (*func) (
gdbarch, at, as, offset, wb);
2898 CORE_ADDR ps, wb, ws, ra;
2899 int epc1_regnum, i,
regnum;
2915Unable to decode Xtensa Window Interrupt Handler's code."));
2925 cache->
wd.
ws = ws ^ (1 << wb);
2927 cache->
wd.
ws = ws | (1 << wb);
2929 cache->
wd.
wb = (ps & 0xf00) >> 8;
2944 if (epc1_regnum < 0)
2945 error(_(
"Unable to read Xtensa register EPC1"));
2994 DEBUGTRACE (
"xtensa_skip_prologue (start_pc = 0x%08x)\n", (
int) start_pc);
2996#if DONT_SKIP_PROLOGUE
3003 if (prologue_sal.
line != 0)
3021 if (end_func != start_pc)
3024 return prologue_sal.
end;
3030 return body_pc != 0 ? body_pc : start_pc;
3043\n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3049 log.printf (_(
"\n\tpc_regnum: No PC register"));
3051 log.printf (_(
"\n\tps_regnum: No PS register"));
3056 log.printf (_(
"\n\twb_regnum: No WB register"));
3058 log.printf (_(
"\n\tws_regnum: No WS register"));
3060 log.printf (_(
"\n\tar_base: No AR registers"));
3064 log.printf (_(
"\n\ta0_base: No Ax registers"));
3067 internal_error (_(
"the following are invalid: %s"), log.c_str ());
3077 int n, max_size = 4;
3083#define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3085#define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3160 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3251 error (_(
"xtensa_dump_tdep(): not implemented"));
3264 _(
"Set Xtensa debugging."),
3265 _(
"Show Xtensa debugging."), _(
"\
3266When non-zero, Xtensa-specific debugging is enabled. \
3267Can be 1, 2, 3, or 4 indicating the level of debugging."),
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep, gdbarch_supports_arch_info_ftype *supports_arch_info)
static std::vector< const char * > arches
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
enum register_status raw_read(int regnum, gdb_byte *buf)
enum register_status raw_read_part(int regnum, int offset, int len, gdb_byte *buf)
enum register_status cooked_read(int regnum, gdb_byte *buf)
void raw_supply(int regnum, const void *buf) override
void cooked_write(int regnum, const gdb_byte *buf)
void raw_write_part(int regnum, int offset, int len, const gdb_byte *buf)
void raw_write(int regnum, const gdb_byte *buf)
void printf(const char *,...) ATTRIBUTE_PRINTF(2
struct cmd_list_element * showdebuglist
struct cmd_list_element * setdebuglist
set_show_commands add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
int safe_read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, LONGEST *return_value)
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
@ RETURN_VALUE_REGISTER_CONVENTION
@ RETURN_VALUE_STRUCT_CONVENTION
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
struct value * frame_unwind_got_memory(frame_info_ptr frame, int regnum, CORE_ADDR addr)
struct value * frame_unwind_got_register(frame_info_ptr frame, int regnum, int new_regnum)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
CORE_ADDR get_frame_pc(frame_info_ptr frame)
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
void frame_unwind_register(frame_info_ptr next_frame, int regnum, gdb_byte *buf)
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
#define FRAME_OBSTACK_ZALLOC(TYPE)
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype *stab_reg_to_regnum)
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype *unwind_pc)
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_wchar_bit(struct gdbarch *gdbarch, int wchar_bit)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
void set_gdbarch_wchar_signed(struct gdbarch *gdbarch, int wchar_signed)
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
int gdbarch_num_regs(struct gdbarch *gdbarch)
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *register_type)
int gdbarch_ps_regnum(struct gdbarch *gdbarch)
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype *dummy_id)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype *iterate_over_regset_sections)
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, gdbarch_tdep_up tdep)
std::unique_ptr< gdbarch_tdep_base > gdbarch_tdep_up
void iterate_over_regset_sections_cb(const char *sect_name, int supply_size, int collect_size, const struct regset *regset, const char *human_name, void *cb_data)
static int gdbarch_num_cooked_regs(gdbarch *arch)
function_call_return_method
struct type * init_integer_type(type_allocator &alloc, int bit, int unsigned_p, const char *name)
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
struct type * check_typedef(struct type *type)
mach_port_t kern_return_t mach_port_t mach_msg_type_name_t msgportsPoly mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
struct regcache * get_current_regcache(void)
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
const reggroup *const general_reggroup
const reggroup * reggroup_new(const char *name, enum reggroup_type type)
const reggroup *const system_reggroup
const reggroup *const float_reggroup
const reggroup *const save_reggroup
const reggroup *const all_reggroup
void reggroup_add(struct gdbarch *gdbarch, const reggroup *group)
const reggroup *const restore_reggroup
const reggroup *const vector_reggroup
void(* func)(remote_target *remote, char *)
constexpr gdb_byte little_breakpoint[]
constexpr gdb_byte big_breakpoint[]
void set_solib_svr4_fetch_link_map_offsets(struct gdbarch *gdbarch, struct link_map_offsets *(*flmo)(void))
struct link_map_offsets * svr4_ilp32_fetch_link_map_offsets(void)
struct type * builtin_uint16
struct type * builtin_double
struct type * builtin_uint128
struct type * builtin_long
struct type * builtin_data_ptr
struct type * builtin_uint32
struct type * builtin_uint64
struct type * builtin_int
struct type * builtin_uint8
struct type * virtual_type
struct ctype_cache * next
gdb::array_view< const gdb_byte > contents()
struct type * type() const
xtensa_c0reg_t c0_rt[C0_NREGS]
xtensa_elf_greg_t windowstart
xtensa_elf_greg_t windowbase
xtensa_call0_frame_cache_t c0
xtensa_windowed_frame_cache_t wd
unsigned int isa_use_density_instructions
unsigned int num_pseudo_regs
unsigned int target_flags
int max_register_raw_size
unsigned int num_nopriv_regs
xtensa_register_t * regmap
int max_register_virtual_size
unsigned int isa_use_exceptions
unsigned int isa_use_windowed_registers
struct ctype_cache * type_entries
xtensa_register_group_t group
unsigned int target_number
xtensa_register_type_t type
const xtensa_mask_t * mask
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
void gdb_printf(struct ui_file *stream, const char *format,...)
struct value * value_cast(struct type *type, struct value *arg2)
static xtensa_insn_kind call0_classify_opcode(xtensa_isa isa, xtensa_opcode opc)
static int rwx_special_register(const char *opcname)
xtensa_exception_handler_t
static void xtensa_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buffer)
static const char * xtensa_register_name(struct gdbarch *gdbarch, int regnum)
static struct xtensa_frame_cache * xtensa_alloc_frame_cache(int windowed)
struct xtensa_windowed_frame_cache xtensa_windowed_frame_cache_t
static enum return_value_convention xtensa_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static int xtensa_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
struct xtensa_call0_frame_cache xtensa_call0_frame_cache_t
static void xtensa_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
#define DEBUGVERB(args...)
static unsigned int xtensa_debug_level
static struct gdbarch * xtensa_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
static int call0_ret(CORE_ADDR start_pc, CORE_ADDR finish_pc)
static unsigned int xtensa_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR current_pc)
static CORE_ADDR xtensa_frame_align(struct gdbarch *gdbarch, CORE_ADDR address)
#define XTENSA_NUM_SAVED_AREGS
static int extract_call_winsize(struct gdbarch *gdbarch, CORE_ADDR pc)
xtensa_register_t xtensa_rmap[]
#define DEBUGTRACE(args...)
static void xtensa_init_reggroups(void)
static const reggroup * xtensa_ar_reggroup
static const reggroup * xtensa_user_reggroup
static CORE_ADDR a11_saved
static void call0_frame_cache(frame_info_ptr this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static CORE_ADDR a7_saved
#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
static CORE_ADDR call0_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR pc, int nregs, xtensa_frame_cache_t *cache)
#define XTENSA_MAX_REGISTER_SIZE
#define LITTLE_BREAKPOINT
#define DENSITY_BIG_BREAKPOINT
static unsigned long xtensa_read_register(int regnum)
static void xtensa_add_reggroups(struct gdbarch *gdbarch)
static int xtensa_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
static void xtensa_window_interrupt_frame_cache(frame_info_ptr this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static CORE_ADDR a0_saved
#define XTENSA_DBREGN_UREG(n)
void _initialize_xtensa_tdep()
static void xtensa_write_register(int regnum, ULONGEST value)
static void xtensa_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
static const reggroup * xtensa_cp[XTENSA_MAX_COPROCESSOR]
static struct value * xtensa_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static void xtensa_store_return_value(struct type *type, struct regcache *regcache, const void *dst)
static int call0_track_op(struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], xtensa_insn_kind opclass, int nods, unsigned odv[], CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
static int areg_number(struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
static xtensa_exception_handler_t execute_code(struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
static void execute_l32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
static const struct frame_unwind xtensa_unwind
static int arreg_number(struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
#define XTENSA_DBREGN_SREG(n)
static void execute_s32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
static CORE_ADDR xtensa_frame_base_address(frame_info_ptr this_frame, void **this_cache)
static CORE_ADDR xtensa_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
#define DEBUGINFO(args...)
struct xtensa_c0reg xtensa_c0reg_t
static const struct frame_base xtensa_frame_base
static struct regset xtensa_gregset
static int xtensa_find_register_by_name(struct gdbarch *gdbarch, const char *name)
static int xtensa_coprocessor_register_group(const struct reggroup *group)
static const gdb_byte * xtensa_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
struct xtensa_frame_cache xtensa_frame_cache_t
static int windowing_enabled(struct gdbarch *gdbarch, unsigned int ps)
static struct xtensa_frame_cache * xtensa_frame_cache(frame_info_ptr this_frame, void **this_cache)
static int xtensa_session_once_reported
static const reggroup * xtensa_vectra_reggroup
static void xtensa_derive_tdep(xtensa_gdbarch_tdep *tdep)
static void xtensa_verify_config(struct gdbarch *gdbarch)
static void xtensa_supply_gregset(const struct regset *regset, struct regcache *rc, int regnum, const void *gregs, size_t len)
static struct frame_id xtensa_dummy_id(struct gdbarch *gdbarch, frame_info_ptr this_frame)
#define XTENSA_IS_ENTRY(gdbarch, op1)
static enum register_status xtensa_register_read_masked(readable_regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer)
static enum register_status xtensa_pseudo_register_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buffer)
static void xtensa_extract_return_value(struct type *type, struct regcache *regcache, void *dst)
xtensa_isa xtensa_default_isa
static struct type * xtensa_register_type(struct gdbarch *gdbarch, int regnum)
static CORE_ADDR xtensa_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
static int xtensa_reg_to_regnum(struct gdbarch *gdbarch, int regnum)
#define DENSITY_LITTLE_BREAKPOINT
static void xtensa_register_write_masked(struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer)
static CORE_ADDR xtensa_unwind_pc(struct gdbarch *gdbarch, frame_info_ptr next_frame)
static void xtensa_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
static void warning_once(void)
static int xtensa_window_interrupt_insn(struct gdbarch *gdbarch, CORE_ADDR pc)
#define XTENSA_MAX_COPROCESSOR
@ xtRegisterTypeTieRegfile
@ xtTargetFlagsNonVisibleRegs
@ xtTargetFlagsUseFetchStore
#define XTENSA_REGISTER_FLAGS_PRIVILEGED