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arc-tdep.c
Go to the documentation of this file.
1/* Target dependent code for ARC architecture, for GDB.
2
3 Copyright 2005-2023 Free Software Foundation, Inc.
4 Contributed by Synopsys Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21/* GDB header files. */
22#include "defs.h"
23#include "arch-utils.h"
24#include "elf-bfd.h"
25#include "disasm.h"
26#include "dwarf2/frame.h"
27#include "frame-base.h"
28#include "frame-unwind.h"
29#include "gdbcore.h"
30#include "reggroups.h"
31#include "gdbcmd.h"
32#include "objfiles.h"
33#include "osabi.h"
34#include "prologue-value.h"
35#include "target-descriptions.h"
36#include "trad-frame.h"
37
38/* ARC header files. */
39#include "opcode/arc.h"
40#include "opcodes/arc-dis.h"
41#include "arc-tdep.h"
42#include "arch/arc.h"
43
44/* Standard headers. */
45#include <algorithm>
46#include <sstream>
47
48/* The frame unwind cache for ARC. */
49
51{
52 /* The stack pointer at the time this frame was created; i.e. the caller's
53 stack pointer when this function was called. It is used to identify this
54 frame. */
55 CORE_ADDR prev_sp;
56
57 /* Register that is a base for this frame - FP for normal frame, SP for
58 non-FP frames. */
60
61 /* Offset from the previous SP to the current frame base. If GCC uses
62 `SUB SP,SP,offset` to allocate space for local variables, then it will be
63 done after setting up a frame pointer, but it still will be considered
64 part of prologue, therefore SP will be lesser than FP at the end of the
65 prologue analysis. In this case that would be an offset from old SP to a
66 new FP. But in case of non-FP frames, frame base is an SP and thus that
67 would be an offset from old SP to new SP. What is important is that this
68 is an offset from old SP to a known register, so it can be used to find
69 old SP.
70
71 Using FP is preferable, when possible, because SP can change in function
72 body after prologue due to alloca, variadic arguments or other shenanigans.
73 If that is the case in the caller frame, then PREV_SP will point to SP at
74 the moment of function call, but it will be different from SP value at the
75 end of the caller prologue. As a result it will not be possible to
76 reconstruct caller's frame and go past it in the backtrace. Those things
77 are unlikely to happen to FP - FP value at the moment of function call (as
78 stored on stack in callee prologue) is also an FP value at the end of the
79 caller's prologue. */
80
82
83 /* Store addresses for registers saved in prologue. During prologue analysis
84 GDB stores offsets relatively to "old SP", then after old SP is evaluated,
85 offsets are replaced with absolute addresses. */
87};
88
89/* Global debug flag. */
90
92
93/* List of "maintenance print arc" commands. */
94
96
97/* A set of registers that we expect to find in a tdesc_feature. These
98 are used in ARC_TDESC_INIT when processing the target description. */
99
101{
102 /* Information for a single register. */
104 {
105 /* The GDB register number for this register. */
107
108 /* List of names for this register. The first name in this list is the
109 preferred name, the name GDB will use when describing this register. */
110 std::vector<const char *> names;
111
112 /* When true, this register must be present in this feature set. */
114 };
115
116 /* The name for this feature. This is the name used to find this feature
117 within the target description. */
118 const char *name;
119
120 /* List of all the registers that we expect to encounter in this register
121 set. */
122 std::vector<struct register_info> registers;
123};
124
125/* Obsolete feature names for backward compatibility. */
127 = "org.gnu.gdb.arc.core.arcompact";
129 = "org.gnu.gdb.arc.core.v2";
131 = "org.gnu.gdb.arc.core-reduced.v2";
133 = "org.gnu.gdb.arc.aux-minimal";
134/* Modern feature names. */
135static const char *ARC_CORE_FEATURE_NAME = "org.gnu.gdb.arc.core";
136static const char *ARC_AUX_FEATURE_NAME = "org.gnu.gdb.arc.aux";
137
138/* ARCv1 (ARC600, ARC601, ARC700) general core registers feature set.
139 See also arc_update_acc_reg_names() for "accl/acch" names. */
140
142{
144 {
145 { ARC_R0_REGNUM + 0, { "r0" }, true },
146 { ARC_R0_REGNUM + 1, { "r1" }, true },
147 { ARC_R0_REGNUM + 2, { "r2" }, true },
148 { ARC_R0_REGNUM + 3, { "r3" }, true },
149 { ARC_R0_REGNUM + 4, { "r4" }, false },
150 { ARC_R0_REGNUM + 5, { "r5" }, false },
151 { ARC_R0_REGNUM + 6, { "r6" }, false },
152 { ARC_R0_REGNUM + 7, { "r7" }, false },
153 { ARC_R0_REGNUM + 8, { "r8" }, false },
154 { ARC_R0_REGNUM + 9, { "r9" }, false },
155 { ARC_R0_REGNUM + 10, { "r10" }, true },
156 { ARC_R0_REGNUM + 11, { "r11" }, true },
157 { ARC_R0_REGNUM + 12, { "r12" }, true },
158 { ARC_R0_REGNUM + 13, { "r13" }, true },
159 { ARC_R0_REGNUM + 14, { "r14" }, true },
160 { ARC_R0_REGNUM + 15, { "r15" }, true },
161 { ARC_R0_REGNUM + 16, { "r16" }, false },
162 { ARC_R0_REGNUM + 17, { "r17" }, false },
163 { ARC_R0_REGNUM + 18, { "r18" }, false },
164 { ARC_R0_REGNUM + 19, { "r19" }, false },
165 { ARC_R0_REGNUM + 20, { "r20" }, false },
166 { ARC_R0_REGNUM + 21, { "r21" }, false },
167 { ARC_R0_REGNUM + 22, { "r22" }, false },
168 { ARC_R0_REGNUM + 23, { "r23" }, false },
169 { ARC_R0_REGNUM + 24, { "r24" }, false },
170 { ARC_R0_REGNUM + 25, { "r25" }, false },
171 { ARC_R0_REGNUM + 26, { "gp" }, true },
172 { ARC_R0_REGNUM + 27, { "fp" }, true },
173 { ARC_R0_REGNUM + 28, { "sp" }, true },
174 { ARC_R0_REGNUM + 29, { "ilink1" }, false },
175 { ARC_R0_REGNUM + 30, { "ilink2" }, false },
176 { ARC_R0_REGNUM + 31, { "blink" }, true },
177 { ARC_R0_REGNUM + 32, { "r32" }, false },
178 { ARC_R0_REGNUM + 33, { "r33" }, false },
179 { ARC_R0_REGNUM + 34, { "r34" }, false },
180 { ARC_R0_REGNUM + 35, { "r35" }, false },
181 { ARC_R0_REGNUM + 36, { "r36" }, false },
182 { ARC_R0_REGNUM + 37, { "r37" }, false },
183 { ARC_R0_REGNUM + 38, { "r38" }, false },
184 { ARC_R0_REGNUM + 39, { "r39" }, false },
185 { ARC_R0_REGNUM + 40, { "r40" }, false },
186 { ARC_R0_REGNUM + 41, { "r41" }, false },
187 { ARC_R0_REGNUM + 42, { "r42" }, false },
188 { ARC_R0_REGNUM + 43, { "r43" }, false },
189 { ARC_R0_REGNUM + 44, { "r44" }, false },
190 { ARC_R0_REGNUM + 45, { "r45" }, false },
191 { ARC_R0_REGNUM + 46, { "r46" }, false },
192 { ARC_R0_REGNUM + 47, { "r47" }, false },
193 { ARC_R0_REGNUM + 48, { "r48" }, false },
194 { ARC_R0_REGNUM + 49, { "r49" }, false },
195 { ARC_R0_REGNUM + 50, { "r50" }, false },
196 { ARC_R0_REGNUM + 51, { "r51" }, false },
197 { ARC_R0_REGNUM + 52, { "r52" }, false },
198 { ARC_R0_REGNUM + 53, { "r53" }, false },
199 { ARC_R0_REGNUM + 54, { "r54" }, false },
200 { ARC_R0_REGNUM + 55, { "r55" }, false },
201 { ARC_R0_REGNUM + 56, { "r56" }, false },
202 { ARC_R0_REGNUM + 57, { "r57" }, false },
203 { ARC_R0_REGNUM + 58, { "r58", "accl" }, false },
204 { ARC_R0_REGNUM + 59, { "r59", "acch" }, false },
205 { ARC_R0_REGNUM + 60, { "lp_count" }, false },
206 { ARC_R0_REGNUM + 61, { "reserved" }, false },
207 { ARC_R0_REGNUM + 62, { "limm" }, false },
208 { ARC_R0_REGNUM + 63, { "pcl" }, true }
209 }
210};
211
212/* ARCv2 (ARCHS) general core registers feature set. See also
213 arc_update_acc_reg_names() for "accl/acch" names. */
214
216{
218 {
219 { ARC_R0_REGNUM + 0, { "r0" }, true },
220 { ARC_R0_REGNUM + 1, { "r1" }, true },
221 { ARC_R0_REGNUM + 2, { "r2" }, true },
222 { ARC_R0_REGNUM + 3, { "r3" }, true },
223 { ARC_R0_REGNUM + 4, { "r4" }, false },
224 { ARC_R0_REGNUM + 5, { "r5" }, false },
225 { ARC_R0_REGNUM + 6, { "r6" }, false },
226 { ARC_R0_REGNUM + 7, { "r7" }, false },
227 { ARC_R0_REGNUM + 8, { "r8" }, false },
228 { ARC_R0_REGNUM + 9, { "r9" }, false },
229 { ARC_R0_REGNUM + 10, { "r10" }, true },
230 { ARC_R0_REGNUM + 11, { "r11" }, true },
231 { ARC_R0_REGNUM + 12, { "r12" }, true },
232 { ARC_R0_REGNUM + 13, { "r13" }, true },
233 { ARC_R0_REGNUM + 14, { "r14" }, true },
234 { ARC_R0_REGNUM + 15, { "r15" }, true },
235 { ARC_R0_REGNUM + 16, { "r16" }, false },
236 { ARC_R0_REGNUM + 17, { "r17" }, false },
237 { ARC_R0_REGNUM + 18, { "r18" }, false },
238 { ARC_R0_REGNUM + 19, { "r19" }, false },
239 { ARC_R0_REGNUM + 20, { "r20" }, false },
240 { ARC_R0_REGNUM + 21, { "r21" }, false },
241 { ARC_R0_REGNUM + 22, { "r22" }, false },
242 { ARC_R0_REGNUM + 23, { "r23" }, false },
243 { ARC_R0_REGNUM + 24, { "r24" }, false },
244 { ARC_R0_REGNUM + 25, { "r25" }, false },
245 { ARC_R0_REGNUM + 26, { "gp" }, true },
246 { ARC_R0_REGNUM + 27, { "fp" }, true },
247 { ARC_R0_REGNUM + 28, { "sp" }, true },
248 { ARC_R0_REGNUM + 29, { "ilink" }, false },
249 { ARC_R0_REGNUM + 30, { "r30" }, true },
250 { ARC_R0_REGNUM + 31, { "blink" }, true },
251 { ARC_R0_REGNUM + 32, { "r32" }, false },
252 { ARC_R0_REGNUM + 33, { "r33" }, false },
253 { ARC_R0_REGNUM + 34, { "r34" }, false },
254 { ARC_R0_REGNUM + 35, { "r35" }, false },
255 { ARC_R0_REGNUM + 36, { "r36" }, false },
256 { ARC_R0_REGNUM + 37, { "r37" }, false },
257 { ARC_R0_REGNUM + 38, { "r38" }, false },
258 { ARC_R0_REGNUM + 39, { "r39" }, false },
259 { ARC_R0_REGNUM + 40, { "r40" }, false },
260 { ARC_R0_REGNUM + 41, { "r41" }, false },
261 { ARC_R0_REGNUM + 42, { "r42" }, false },
262 { ARC_R0_REGNUM + 43, { "r43" }, false },
263 { ARC_R0_REGNUM + 44, { "r44" }, false },
264 { ARC_R0_REGNUM + 45, { "r45" }, false },
265 { ARC_R0_REGNUM + 46, { "r46" }, false },
266 { ARC_R0_REGNUM + 47, { "r47" }, false },
267 { ARC_R0_REGNUM + 48, { "r48" }, false },
268 { ARC_R0_REGNUM + 49, { "r49" }, false },
269 { ARC_R0_REGNUM + 50, { "r50" }, false },
270 { ARC_R0_REGNUM + 51, { "r51" }, false },
271 { ARC_R0_REGNUM + 52, { "r52" }, false },
272 { ARC_R0_REGNUM + 53, { "r53" }, false },
273 { ARC_R0_REGNUM + 54, { "r54" }, false },
274 { ARC_R0_REGNUM + 55, { "r55" }, false },
275 { ARC_R0_REGNUM + 56, { "r56" }, false },
276 { ARC_R0_REGNUM + 57, { "r57" }, false },
277 { ARC_R0_REGNUM + 58, { "r58", "accl" }, false },
278 { ARC_R0_REGNUM + 59, { "r59", "acch" }, false },
279 { ARC_R0_REGNUM + 60, { "lp_count" }, false },
280 { ARC_R0_REGNUM + 61, { "reserved" }, false },
281 { ARC_R0_REGNUM + 62, { "limm" }, false },
282 { ARC_R0_REGNUM + 63, { "pcl" }, true }
283 }
284};
285
286/* The common auxiliary registers feature set. The REGNUM field
287 must match the ARC_REGNUM enum in arc-tdep.h. */
288
290{
292 {
293 { ARC_FIRST_AUX_REGNUM + 0, { "pc" }, true },
294 { ARC_FIRST_AUX_REGNUM + 1, { "status32" }, true },
295 { ARC_FIRST_AUX_REGNUM + 2, { "lp_start" }, false },
296 { ARC_FIRST_AUX_REGNUM + 3, { "lp_end" }, false },
297 { ARC_FIRST_AUX_REGNUM + 4, { "bta" }, false }
298 }
299};
300
301static char *arc_disassembler_options = NULL;
302
303/* Functions are sorted in the order as they are used in the
304 _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static
305 functions are defined before the first invocation. */
306
307/* Returns an unsigned value of OPERAND_NUM in instruction INSN.
308 For relative branch instructions returned value is an offset, not an actual
309 branch target. */
310
311static ULONGEST
312arc_insn_get_operand_value (const struct arc_instruction &insn,
313 unsigned int operand_num)
314{
315 switch (insn.operands[operand_num].kind)
316 {
317 case ARC_OPERAND_KIND_LIMM:
318 gdb_assert (insn.limm_p);
319 return insn.limm_value;
320 case ARC_OPERAND_KIND_SHIMM:
321 return insn.operands[operand_num].value;
322 default:
323 /* Value in instruction is a register number. */
325 ULONGEST value;
327 insn.operands[operand_num].value,
328 &value);
329 return value;
330 }
331}
332
333/* Like arc_insn_get_operand_value, but returns a signed value. */
334
335static LONGEST
336arc_insn_get_operand_value_signed (const struct arc_instruction &insn,
337 unsigned int operand_num)
338{
339 switch (insn.operands[operand_num].kind)
340 {
341 case ARC_OPERAND_KIND_LIMM:
342 gdb_assert (insn.limm_p);
343 /* Convert unsigned raw value to signed one. This assumes 2's
344 complement arithmetic, but so is the LONG_MIN value from generic
345 defs.h and that assumption is true for ARC. */
346 gdb_static_assert (sizeof (insn.limm_value) == sizeof (int));
347 return (((LONGEST) insn.limm_value) ^ INT_MIN) - INT_MIN;
348 case ARC_OPERAND_KIND_SHIMM:
349 /* Sign conversion has been done by binutils. */
350 return insn.operands[operand_num].value;
351 default:
352 /* Value in instruction is a register number. */
354 LONGEST value;
356 insn.operands[operand_num].value,
357 &value);
358 return value;
359 }
360}
361
362/* Get register with base address of memory operation. */
363
364static int
365arc_insn_get_memory_base_reg (const struct arc_instruction &insn)
366{
367 /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */
368 if (insn.insn_class == PUSH || insn.insn_class == POP)
369 return ARC_SP_REGNUM;
370
371 gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE);
372
373 /* Other instructions all have at least two operands: operand 0 is data,
374 operand 1 is address. Operand 2 is offset from address. However, see
375 comment to arc_instruction.operands - in some cases, third operand may be
376 missing, namely if it is 0. */
377 gdb_assert (insn.operands_count >= 2);
378 return insn.operands[1].value;
379}
380
381/* Get offset of a memory operation INSN. */
382
383static CORE_ADDR
384arc_insn_get_memory_offset (const struct arc_instruction &insn)
385{
386 /* POP_S and PUSH_S have offset as an implicit argument in a
387 disassembler. */
388 if (insn.insn_class == POP)
389 return 4;
390 else if (insn.insn_class == PUSH)
391 return -4;
392
393 gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE);
394
395 /* Other instructions all have at least two operands: operand 0 is data,
396 operand 1 is address. Operand 2 is offset from address. However, see
397 comment to arc_instruction.operands - in some cases, third operand may be
398 missing, namely if it is 0. */
399 if (insn.operands_count < 3)
400 return 0;
401
402 CORE_ADDR value = arc_insn_get_operand_value (insn, 2);
403 /* Handle scaling. */
404 if (insn.writeback_mode == ARC_WRITEBACK_AS)
405 {
406 /* Byte data size is not valid for AS. Halfword means shift by 1 bit.
407 Word and double word means shift by 2 bits. */
408 gdb_assert (insn.data_size_mode != ARC_SCALING_B);
409 if (insn.data_size_mode == ARC_SCALING_H)
410 value <<= 1;
411 else
412 value <<= 2;
413 }
414 return value;
415}
416
417CORE_ADDR
418arc_insn_get_branch_target (const struct arc_instruction &insn)
419{
420 gdb_assert (insn.is_control_flow);
421
422 /* BI [c]: PC = nextPC + (c << 2). */
423 if (insn.insn_class == BI)
424 {
425 ULONGEST reg_value = arc_insn_get_operand_value (insn, 0);
426 return arc_insn_get_linear_next_pc (insn) + (reg_value << 2);
427 }
428 /* BIH [c]: PC = nextPC + (c << 1). */
429 else if (insn.insn_class == BIH)
430 {
431 ULONGEST reg_value = arc_insn_get_operand_value (insn, 0);
432 return arc_insn_get_linear_next_pc (insn) + (reg_value << 1);
433 }
434 /* JLI and EI. */
435 /* JLI and EI depend on optional AUX registers. Not supported right now. */
436 else if (insn.insn_class == JLI)
437 {
439 "JLI_S instruction is not supported by the GDB.");
440 return 0;
441 }
442 else if (insn.insn_class == EI)
443 {
445 "EI_S instruction is not supported by the GDB.");
446 return 0;
447 }
448 /* LEAVE_S: PC = BLINK. */
449 else if (insn.insn_class == LEAVE)
450 {
452 ULONGEST value;
454 return value;
455 }
456 /* BBIT0/1, BRcc: PC = currentPC + operand. */
457 else if (insn.insn_class == BBIT0 || insn.insn_class == BBIT1
458 || insn.insn_class == BRCC)
459 {
460 /* Most instructions has branch target as their sole argument. However
461 conditional brcc/bbit has it as a third operand. */
462 CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 2);
463
464 /* Offset is relative to the 4-byte aligned address of the current
465 instruction, hence last two bits should be truncated. */
466 return pcrel_addr + align_down (insn.address, 4);
467 }
468 /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */
469 else if (insn.insn_class == BRANCH || insn.insn_class == LOOP)
470 {
471 CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 0);
472
473 /* Offset is relative to the 4-byte aligned address of the current
474 instruction, hence last two bits should be truncated. */
475 return pcrel_addr + align_down (insn.address, 4);
476 }
477 /* J, Jcc, JL, JLcc: PC = operand. */
478 else if (insn.insn_class == JUMP)
479 {
480 /* All jumps are single-operand. */
481 return arc_insn_get_operand_value (insn, 0);
482 }
483
484 /* This is some new and unknown instruction. */
485 gdb_assert_not_reached ("Unknown branch instruction.");
486}
487
488/* Dump INSN into gdb_stdlog. */
489
490static void
491arc_insn_dump (const struct arc_instruction &insn)
492{
493 struct gdbarch *gdbarch = target_gdbarch ();
494
495 arc_print ("Dumping arc_instruction at %s\n",
496 paddress (gdbarch, insn.address));
497 arc_print ("\tlength = %u\n", insn.length);
498
499 if (!insn.valid)
500 {
501 arc_print ("\tThis is not a valid ARC instruction.\n");
502 return;
503 }
504
505 arc_print ("\tlength_with_limm = %u\n", insn.length + (insn.limm_p ? 4 : 0));
506 arc_print ("\tcc = 0x%x\n", insn.condition_code);
507 arc_print ("\tinsn_class = %u\n", insn.insn_class);
508 arc_print ("\tis_control_flow = %i\n", insn.is_control_flow);
509 arc_print ("\thas_delay_slot = %i\n", insn.has_delay_slot);
510
511 CORE_ADDR next_pc = arc_insn_get_linear_next_pc (insn);
512 arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch, next_pc));
513
514 if (insn.is_control_flow)
515 {
516 CORE_ADDR t = arc_insn_get_branch_target (insn);
517 arc_print ("\tbranch_target = %s\n", paddress (gdbarch, t));
518 }
519
520 arc_print ("\tlimm_p = %i\n", insn.limm_p);
521 if (insn.limm_p)
522 arc_print ("\tlimm_value = 0x%08x\n", insn.limm_value);
523
524 if (insn.insn_class == STORE || insn.insn_class == LOAD
525 || insn.insn_class == PUSH || insn.insn_class == POP)
526 {
527 arc_print ("\twriteback_mode = %u\n", insn.writeback_mode);
528 arc_print ("\tdata_size_mode = %u\n", insn.data_size_mode);
529 arc_print ("\tmemory_base_register = %s\n",
532 /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a
533 LONGEST for a nicer representation. */
534 arc_print ("\taddr_offset = %s\n",
535 plongest (arc_insn_get_memory_offset (insn)));
536 }
537
538 arc_print ("\toperands_count = %u\n", insn.operands_count);
539 for (unsigned int i = 0; i < insn.operands_count; ++i)
540 {
541 int is_reg = (insn.operands[i].kind == ARC_OPERAND_KIND_REG);
542
543 arc_print ("\toperand[%u] = {\n", i);
544 arc_print ("\t\tis_reg = %i\n", is_reg);
545 if (is_reg)
546 arc_print ("\t\tregister = %s\n",
547 gdbarch_register_name (gdbarch, insn.operands[i].value));
548 /* Don't know if this value is signed or not, so print both
549 representations. This tends to look quite ugly, especially for big
550 numbers. */
551 arc_print ("\t\tunsigned value = %s\n",
552 pulongest (arc_insn_get_operand_value (insn, i)));
553 arc_print ("\t\tsigned value = %s\n",
554 plongest (arc_insn_get_operand_value_signed (insn, i)));
555 arc_print ("\t}\n");
556 }
557}
558
559CORE_ADDR
560arc_insn_get_linear_next_pc (const struct arc_instruction &insn)
561{
562 /* In ARC long immediate is always 4 bytes. */
563 return (insn.address + insn.length + (insn.limm_p ? 4 : 0));
564}
565
566/* Implement the "write_pc" gdbarch method.
567
568 In ARC PC register is a normal register so in most cases setting PC value
569 is a straightforward process: debugger just writes PC value. However it
570 gets trickier in case when current instruction is an instruction in delay
571 slot. In this case CPU will execute instruction at current PC value, then
572 will set PC to the current value of BTA register; also current instruction
573 cannot be branch/jump and some of the other instruction types. Thus if
574 debugger would try to just change PC value in this case, this instruction
575 will get executed, but then core will "jump" to the original branch target.
576
577 Whether current instruction is a delay-slot instruction or not is indicated
578 by DE bit in STATUS32 register indicates if current instruction is a delay
579 slot instruction. This bit is writable by debug host, which allows debug
580 host to prevent core from jumping after the delay slot instruction. It
581 also works in another direction: setting this bit will make core to treat
582 any current instructions as a delay slot instruction and to set PC to the
583 current value of BTA register.
584
585 To workaround issues with changing PC register while in delay slot
586 instruction, debugger should check for the STATUS32.DE bit and reset it if
587 it is set. No other change is required in this function. Most common
588 case, where this function might be required is calling inferior functions
589 from debugger. Generic GDB logic handles this pretty well: current values
590 of registers are stored, value of PC is changed (that is the job of this
591 function), and after inferior function is executed, GDB restores all
592 registers, include BTA and STATUS32, which also means that core is returned
593 to its original state of being halted on delay slot instructions.
594
595 This method is useless for ARC 600, because it doesn't have externally
596 exposed BTA register. In the case of ARC 600 it is impossible to restore
597 core to its state in all occasions thus core should never be halted (from
598 the perspective of debugger host) in the delay slot. */
599
600static void
601arc_write_pc (struct regcache *regcache, CORE_ADDR new_pc)
602{
603 struct gdbarch *gdbarch = regcache->arch ();
604
605 arc_debug_printf ("Writing PC, new value=%s",
606 paddress (gdbarch, new_pc));
607
609 new_pc);
610
611 ULONGEST status32;
613 &status32);
614
615 if ((status32 & ARC_STATUS32_DE_MASK) != 0)
616 {
617 arc_debug_printf ("Changing PC while in delay slot. Will "
618 "reset STATUS32.DE bit to zero. Value of STATUS32 "
619 "register is 0x%s",
620 phex (status32, ARC_REGISTER_SIZE));
621
622 /* Reset bit and write to the cache. */
623 status32 &= ~0x40;
625 status32);
626 }
627}
628
629/* Implement the "virtual_frame_pointer" gdbarch method.
630
631 According to ABI the FP (r27) is used to point to the middle of the current
632 stack frame, just below the saved FP and before local variables, register
633 spill area and outgoing args. However for optimization levels above O2 and
634 in any case in leaf functions, the frame pointer is usually not set at all.
635 The exception being when handling nested functions.
636
637 We use this function to return a "virtual" frame pointer, marking the start
638 of the current stack frame as a register-offset pair. If the FP is not
639 being used, then it should return SP, with an offset of the frame size.
640
641 The current implementation doesn't actually know the frame size, nor
642 whether the FP is actually being used, so for now we just return SP and an
643 offset of zero. This is no worse than other architectures, but is needed
644 to avoid assertion failures.
645
646 TODO: Can we determine the frame size to get a correct offset?
647
648 PC is a program counter where we need the virtual FP. REG_PTR is the base
649 register used for the virtual FP. OFFSET_PTR is the offset used for the
650 virtual FP. */
651
652static void
654 int *reg_ptr, LONGEST *offset_ptr)
655{
656 *reg_ptr = gdbarch_sp_regnum (gdbarch);
657 *offset_ptr = 0;
658}
659
660/* Implement the "push_dummy_call" gdbarch method.
661
662 Stack Frame Layout
663
664 This shows the layout of the stack frame for the general case of a
665 function call; a given function might not have a variable number of
666 arguments or local variables, or might not save any registers, so it would
667 not have the corresponding frame areas. Additionally, a leaf function
668 (i.e. one which calls no other functions) does not need to save the
669 contents of the BLINK register (which holds its return address), and a
670 function might not have a frame pointer.
671
672 The stack grows downward, so SP points below FP in memory; SP always
673 points to the last used word on the stack, not the first one.
674
675 | | |
676 | arg word N | | caller's
677 | : | | frame
678 | arg word 10 | |
679 | arg word 9 | |
680 old SP ---> +-----------------------+ --+
681 | | |
682 | callee-saved | |
683 | registers | |
684 | including fp, blink | |
685 | | | callee's
686 new FP ---> +-----------------------+ | frame
687 | | |
688 | local | |
689 | variables | |
690 | | |
691 | register | |
692 | spill area | |
693 | | |
694 | outgoing args | |
695 | | |
696 new SP ---> +-----------------------+ --+
697 | |
698 | unused |
699 | |
700 |
701 |
702 V
703 downwards
704
705 The list of arguments to be passed to a function is considered to be a
706 sequence of _N_ words (as though all the parameters were stored in order in
707 memory with each parameter occupying an integral number of words). Words
708 1..8 are passed in registers 0..7; if the function has more than 8 words of
709 arguments then words 9..@em N are passed on the stack in the caller's frame.
710
711 If the function has a variable number of arguments, e.g. it has a form such
712 as `function (p1, p2, ...);' and _P_ words are required to hold the values
713 of the named parameters (which are passed in registers 0..@em P -1), then
714 the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the
715 top of the frame so that the anonymous parameter words occupy a continuous
716 region.
717
718 Any arguments are already in target byte order. We just need to store
719 them!
720
721 BP_ADDR is the return address where breakpoint must be placed. NARGS is
722 the number of arguments to the function. ARGS is the arguments values (in
723 target byte order). SP is the Current value of SP register. STRUCT_RETURN
724 is TRUE if structures are returned by the function. STRUCT_ADDR is the
725 hidden address for returning a struct. Returns SP of a new frame. */
726
727static CORE_ADDR
728arc_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
729 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
730 struct value **args, CORE_ADDR sp,
731 function_call_return_method return_method,
732 CORE_ADDR struct_addr)
733{
734 arc_debug_printf ("nargs = %d", nargs);
735
736 int arg_reg = ARC_FIRST_ARG_REGNUM;
737
738 /* Push the return address. */
740
741 /* Are we returning a value using a structure return instead of a normal
742 value return? If so, struct_addr is the address of the reserved space for
743 the return structure to be written on the stack, and that address is
744 passed to that function as a hidden first argument. */
745 if (return_method == return_method_struct)
746 {
747 /* Pass the return address in the first argument register. */
748 regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr);
749
750 arc_debug_printf ("struct return address %s passed in R%d",
751 print_core_address (gdbarch, struct_addr), arg_reg);
752
753 arg_reg++;
754 }
755
756 if (nargs > 0)
757 {
758 unsigned int total_space = 0;
759
760 /* How much space do the arguments occupy in total? Must round each
761 argument's size up to an integral number of words. */
762 for (int i = 0; i < nargs; i++)
763 {
764 unsigned int len = args[i]->type ()->length ();
765 unsigned int space = align_up (len, 4);
766
767 total_space += space;
768
769 arc_debug_printf ("arg %d: %u bytes -> %u", i, len, space);
770 }
771
772 /* Allocate a buffer to hold a memory image of the arguments. */
773 gdb_byte *memory_image = XCNEWVEC (gdb_byte, total_space);
774
775 /* Now copy all of the arguments into the buffer, correctly aligned. */
776 gdb_byte *data = memory_image;
777 for (int i = 0; i < nargs; i++)
778 {
779 unsigned int len = args[i]->type ()->length ();
780 unsigned int space = align_up (len, 4);
781
782 memcpy (data, args[i]->contents ().data (), (size_t) len);
783 arc_debug_printf ("copying arg %d, val 0x%08x, len %d to mem",
784 i, *((int *) args[i]->contents ().data ()),
785 len);
786
787 data += space;
788 }
789
790 /* Now load as much as possible of the memory image into registers. */
791 data = memory_image;
792 while (arg_reg <= ARC_LAST_ARG_REGNUM)
793 {
794 arc_debug_printf ("passing 0x%02x%02x%02x%02x in register R%d",
795 data[0], data[1], data[2], data[3], arg_reg);
796
797 /* Note we don't use write_unsigned here, since that would convert
798 the byte order, but we are already in the correct byte order. */
799 regcache->cooked_write (arg_reg, data);
800
801 data += ARC_REGISTER_SIZE;
802 total_space -= ARC_REGISTER_SIZE;
803
804 /* All the data is now in registers. */
805 if (total_space == 0)
806 break;
807
808 arg_reg++;
809 }
810
811 /* If there is any data left, push it onto the stack (in a single write
812 operation). */
813 if (total_space > 0)
814 {
815 arc_debug_printf ("passing %d bytes on stack\n", total_space);
816
817 sp -= total_space;
818 write_memory (sp, data, (int) total_space);
819 }
820
821 xfree (memory_image);
822 }
823
824 /* Finally, update the SP register. */
826
827 return sp;
828}
829
830/* Implement the "push_dummy_code" gdbarch method.
831
832 We don't actually push any code. We just identify where a breakpoint can
833 be inserted to which we are can return and the resume address where we
834 should be called.
835
836 ARC does not necessarily have an executable stack, so we can't put the
837 return breakpoint there. Instead we put it at the entry point of the
838 function. This means the SP is unchanged.
839
840 SP is a current stack pointer FUNADDR is an address of the function to be
841 called. ARGS is arguments to pass. NARGS is a number of args to pass.
842 VALUE_TYPE is a type of value returned. REAL_PC is a resume address when
843 the function is called. BP_ADDR is an address where breakpoint should be
844 set. Returns the updated stack pointer. */
845
846static CORE_ADDR
847arc_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
848 struct value **args, int nargs, struct type *value_type,
849 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
850 struct regcache *regcache)
851{
852 *real_pc = funaddr;
853 *bp_addr = entry_point_address ();
854 return sp;
855}
856
857/* Implement the "cannot_fetch_register" gdbarch method. */
858
859static int
861{
862 /* Assume that register is readable if it is unknown. LIMM and RESERVED are
863 not real registers, but specific register numbers. They are available as
864 regnums to align architectural register numbers with GDB internal regnums,
865 but they shouldn't appear in target descriptions generated by
866 GDB-servers. */
867 switch (regnum)
868 {
870 case ARC_LIMM_REGNUM:
871 return true;
872 default:
873 return false;
874 }
875}
876
877/* Implement the "cannot_store_register" gdbarch method. */
878
879static int
881{
882 /* Assume that register is writable if it is unknown. See comment in
883 arc_cannot_fetch_register about LIMM and RESERVED. */
884 switch (regnum)
885 {
887 case ARC_LIMM_REGNUM:
888 case ARC_PCL_REGNUM:
889 return true;
890 default:
891 return false;
892 }
893}
894
895/* Get the return value of a function from the registers/memory used to
896 return it, according to the convention used by the ABI - 4-bytes values are
897 in the R0, while 8-byte values are in the R0-R1.
898
899 TODO: This implementation ignores the case of "complex double", where
900 according to ABI, value is returned in the R0-R3 registers.
901
902 TYPE is a returned value's type. VALBUF is a buffer for the returned
903 value. */
904
905static void
907 struct regcache *regcache, gdb_byte *valbuf)
908{
909 unsigned int len = type->length ();
910
911 arc_debug_printf ("called");
912
913 if (len <= ARC_REGISTER_SIZE)
914 {
915 ULONGEST val;
916
917 /* Get the return value from one register. */
919 store_unsigned_integer (valbuf, (int) len,
921
922 arc_debug_printf ("returning 0x%s", phex (val, ARC_REGISTER_SIZE));
923 }
924 else if (len <= ARC_REGISTER_SIZE * 2)
925 {
926 ULONGEST low, high;
927
928 /* Get the return value from two registers. */
931
935 (int) len - ARC_REGISTER_SIZE,
937
938 arc_debug_printf ("returning 0x%s%s",
939 phex (high, ARC_REGISTER_SIZE),
940 phex (low, ARC_REGISTER_SIZE));
941 }
942 else
943 error (_("arc: extract_return_value: type length %u too large"), len);
944}
945
946
947/* Store the return value of a function into the registers/memory used to
948 return it, according to the convention used by the ABI.
949
950 TODO: This implementation ignores the case of "complex double", where
951 according to ABI, value is returned in the R0-R3 registers.
952
953 TYPE is a returned value's type. VALBUF is a buffer with the value to
954 return. */
955
956static void
958 struct regcache *regcache, const gdb_byte *valbuf)
959{
960 unsigned int len = type->length ();
961
962 arc_debug_printf ("called");
963
964 if (len <= ARC_REGISTER_SIZE)
965 {
966 ULONGEST val;
967
968 /* Put the return value into one register. */
969 val = extract_unsigned_integer (valbuf, (int) len,
972
973 arc_debug_printf ("storing 0x%s", phex (val, ARC_REGISTER_SIZE));
974 }
975 else if (len <= ARC_REGISTER_SIZE * 2)
976 {
977 ULONGEST low, high;
978
979 /* Put the return value into two registers. */
983 (int) len - ARC_REGISTER_SIZE,
985
988
989 arc_debug_printf ("storing 0x%s%s",
990 phex (high, ARC_REGISTER_SIZE),
991 phex (low, ARC_REGISTER_SIZE));
992 }
993 else
994 error (_("arc_store_return_value: type length too large."));
995}
996
997/* Implement the "get_longjmp_target" gdbarch method. */
998
999static int
1001{
1002 arc_debug_printf ("called");
1003
1004 struct gdbarch *gdbarch = get_frame_arch (frame);
1005 arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (gdbarch);
1006 int pc_offset = tdep->jb_pc * ARC_REGISTER_SIZE;
1007 gdb_byte buf[ARC_REGISTER_SIZE];
1008 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, ARC_FIRST_ARG_REGNUM);
1009
1010 if (target_read_memory (jb_addr + pc_offset, buf, ARC_REGISTER_SIZE))
1011 return 0; /* Failed to read from memory. */
1012
1015 return 1;
1016}
1017
1018/* Implement the "return_value" gdbarch method. */
1019
1020static enum return_value_convention
1021arc_return_value (struct gdbarch *gdbarch, struct value *function,
1022 struct type *valtype, struct regcache *regcache,
1023 gdb_byte *readbuf, const gdb_byte *writebuf)
1024{
1025 /* If the return type is a struct, or a union, or would occupy more than two
1026 registers, the ABI uses the "struct return convention": the calling
1027 function passes a hidden first parameter to the callee (in R0). That
1028 parameter is the address at which the value being returned should be
1029 stored. Otherwise, the result is returned in registers. */
1030 int is_struct_return = (valtype->code () == TYPE_CODE_STRUCT
1031 || valtype->code () == TYPE_CODE_UNION
1032 || valtype->length () > 2 * ARC_REGISTER_SIZE);
1033
1034 arc_debug_printf ("readbuf = %s, writebuf = %s",
1035 host_address_to_string (readbuf),
1036 host_address_to_string (writebuf));
1037
1038 if (writebuf != NULL)
1039 {
1040 /* Case 1. GDB should not ask us to set a struct return value: it
1041 should know the struct return location and write the value there
1042 itself. */
1043 gdb_assert (!is_struct_return);
1044 arc_store_return_value (gdbarch, valtype, regcache, writebuf);
1045 }
1046 else if (readbuf != NULL)
1047 {
1048 /* Case 2. GDB should not ask us to get a struct return value: it
1049 should know the struct return location and read the value from there
1050 itself. */
1051 gdb_assert (!is_struct_return);
1052 arc_extract_return_value (gdbarch, valtype, regcache, readbuf);
1053 }
1054
1055 return (is_struct_return
1058}
1059
1060/* Return the base address of the frame. For ARC, the base address is the
1061 frame pointer. */
1062
1063static CORE_ADDR
1064arc_frame_base_address (frame_info_ptr this_frame, void **prologue_cache)
1065{
1066 return (CORE_ADDR) get_frame_register_unsigned (this_frame, ARC_FP_REGNUM);
1067}
1068
1069/* Helper function that returns valid pv_t for an instruction operand:
1070 either a register or a constant. */
1071
1072static pv_t
1073arc_pv_get_operand (pv_t *regs, const struct arc_instruction &insn, int operand)
1074{
1075 if (insn.operands[operand].kind == ARC_OPERAND_KIND_REG)
1076 return regs[insn.operands[operand].value];
1077 else
1078 return pv_constant (arc_insn_get_operand_value (insn, operand));
1079}
1080
1081/* Determine whether the given disassembled instruction may be part of a
1082 function prologue. If it is, the information in the frame unwind cache will
1083 be updated. */
1084
1085static bool
1086arc_is_in_prologue (struct gdbarch *gdbarch, const struct arc_instruction &insn,
1087 pv_t *regs, struct pv_area *stack)
1088{
1089 /* It might be that currently analyzed address doesn't contain an
1090 instruction, hence INSN is not valid. It likely means that address points
1091 to a data, non-initialized memory, or middle of a 32-bit instruction. In
1092 practice this may happen if GDB connects to a remote target that has
1093 non-zeroed memory. GDB would read PC value and would try to analyze
1094 prologue, but there is no guarantee that memory contents at the address
1095 specified in PC is address is a valid instruction. There is not much that
1096 that can be done about that. */
1097 if (!insn.valid)
1098 return false;
1099
1100 /* Branch/jump or a predicated instruction. */
1101 if (insn.is_control_flow || insn.condition_code != ARC_CC_AL)
1102 return false;
1103
1104 /* Store of some register. May or may not update base address register. */
1105 if (insn.insn_class == STORE || insn.insn_class == PUSH)
1106 {
1107 /* There is definitely at least one operand - register/value being
1108 stored. */
1109 gdb_assert (insn.operands_count > 0);
1110
1111 /* Store at some constant address. */
1112 if (insn.operands_count > 1
1113 && insn.operands[1].kind != ARC_OPERAND_KIND_REG)
1114 return false;
1115
1116 /* Writeback modes:
1117 Mode Address used Writeback value
1118 --------------------------------------------------
1119 No reg + offset no
1120 A/AW reg + offset reg + offset
1121 AB reg reg + offset
1122 AS reg + (offset << scaling) no
1123
1124 "PUSH reg" is an alias to "ST.AW reg, [SP, -4]" encoding. However
1125 16-bit PUSH_S is a distinct instruction encoding, where offset and
1126 base register are implied through opcode. */
1127
1128 /* Register with base memory address. */
1129 int base_reg = arc_insn_get_memory_base_reg (insn);
1130
1131 /* Address where to write. arc_insn_get_memory_offset returns scaled
1132 value for ARC_WRITEBACK_AS. */
1133 pv_t addr;
1134 if (insn.writeback_mode == ARC_WRITEBACK_AB)
1135 addr = regs[base_reg];
1136 else
1137 addr = pv_add_constant (regs[base_reg],
1139
1140 if (stack->store_would_trash (addr))
1141 return false;
1142
1143 if (insn.data_size_mode != ARC_SCALING_D)
1144 {
1145 /* Find the value being stored. */
1146 pv_t store_value = arc_pv_get_operand (regs, insn, 0);
1147
1148 /* What is the size of a the stored value? */
1149 CORE_ADDR size;
1150 if (insn.data_size_mode == ARC_SCALING_B)
1151 size = 1;
1152 else if (insn.data_size_mode == ARC_SCALING_H)
1153 size = 2;
1154 else
1156
1157 stack->store (addr, size, store_value);
1158 }
1159 else
1160 {
1161 if (insn.operands[0].kind == ARC_OPERAND_KIND_REG)
1162 {
1163 /* If this is a double store, than write N+1 register as well. */
1164 pv_t store_value1 = regs[insn.operands[0].value];
1165 pv_t store_value2 = regs[insn.operands[0].value + 1];
1166 stack->store (addr, ARC_REGISTER_SIZE, store_value1);
1167 stack->store (pv_add_constant (addr, ARC_REGISTER_SIZE),
1168 ARC_REGISTER_SIZE, store_value2);
1169 }
1170 else
1171 {
1172 pv_t store_value
1174 stack->store (addr, ARC_REGISTER_SIZE * 2, store_value);
1175 }
1176 }
1177
1178 /* Is base register updated? */
1179 if (insn.writeback_mode == ARC_WRITEBACK_A
1180 || insn.writeback_mode == ARC_WRITEBACK_AB)
1181 regs[base_reg] = pv_add_constant (regs[base_reg],
1183
1184 return true;
1185 }
1186 else if (insn.insn_class == MOVE)
1187 {
1188 gdb_assert (insn.operands_count == 2);
1189
1190 /* Destination argument can be "0", so nothing will happen. */
1191 if (insn.operands[0].kind == ARC_OPERAND_KIND_REG)
1192 {
1193 int dst_regnum = insn.operands[0].value;
1194 regs[dst_regnum] = arc_pv_get_operand (regs, insn, 1);
1195 }
1196 return true;
1197 }
1198 else if (insn.insn_class == SUB)
1199 {
1200 gdb_assert (insn.operands_count == 3);
1201
1202 /* SUB 0,b,c. */
1203 if (insn.operands[0].kind != ARC_OPERAND_KIND_REG)
1204 return true;
1205
1206 int dst_regnum = insn.operands[0].value;
1207 regs[dst_regnum] = pv_subtract (arc_pv_get_operand (regs, insn, 1),
1208 arc_pv_get_operand (regs, insn, 2));
1209 return true;
1210 }
1211 else if (insn.insn_class == ENTER)
1212 {
1213 /* ENTER_S is a prologue-in-instruction - it saves all callee-saved
1214 registers according to given arguments thus greatly reducing code
1215 size. Which registers will be actually saved depends on arguments.
1216
1217 ENTER_S {R13-...,FP,BLINK} stores registers in following order:
1218
1219 new SP ->
1220 BLINK
1221 R13
1222 R14
1223 R15
1224 ...
1225 FP
1226 old SP ->
1227
1228 There are up to three arguments for this opcode, as presented by ARC
1229 disassembler:
1230 1) amount of general-purpose registers to be saved - this argument is
1231 always present even when it is 0;
1232 2) FP register number (27) if FP has to be stored, otherwise argument
1233 is not present;
1234 3) BLINK register number (31) if BLINK has to be stored, otherwise
1235 argument is not present. If both FP and BLINK are stored, then FP
1236 is present before BLINK in argument list. */
1237 gdb_assert (insn.operands_count > 0);
1238
1239 int regs_saved = arc_insn_get_operand_value (insn, 0);
1240
1241 bool is_fp_saved;
1242 if (insn.operands_count > 1)
1243 is_fp_saved = (insn.operands[1].value == ARC_FP_REGNUM);
1244 else
1245 is_fp_saved = false;
1246
1247 bool is_blink_saved;
1248 if (insn.operands_count > 1)
1249 is_blink_saved = (insn.operands[insn.operands_count - 1].value
1250 == ARC_BLINK_REGNUM);
1251 else
1252 is_blink_saved = false;
1253
1254 /* Amount of bytes to be allocated to store specified registers. */
1255 CORE_ADDR st_size = ((regs_saved + is_fp_saved + is_blink_saved)
1257 pv_t new_sp = pv_add_constant (regs[ARC_SP_REGNUM], -st_size);
1258
1259 /* Assume that if the last register (closest to new SP) can be written,
1260 then it is possible to write all of them. */
1261 if (stack->store_would_trash (new_sp))
1262 return false;
1263
1264 /* Current store address. */
1265 pv_t addr = regs[ARC_SP_REGNUM];
1266
1267 if (is_fp_saved)
1268 {
1269 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE);
1270 stack->store (addr, ARC_REGISTER_SIZE, regs[ARC_FP_REGNUM]);
1271 }
1272
1273 /* Registers are stored in backward order: from GP (R26) to R13. */
1274 for (int i = ARC_R13_REGNUM + regs_saved - 1; i >= ARC_R13_REGNUM; i--)
1275 {
1276 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE);
1277 stack->store (addr, ARC_REGISTER_SIZE, regs[i]);
1278 }
1279
1280 if (is_blink_saved)
1281 {
1282 addr = pv_add_constant (addr, -ARC_REGISTER_SIZE);
1283 stack->store (addr, ARC_REGISTER_SIZE,
1284 regs[ARC_BLINK_REGNUM]);
1285 }
1286
1287 gdb_assert (pv_is_identical (addr, new_sp));
1288
1289 regs[ARC_SP_REGNUM] = new_sp;
1290
1291 if (is_fp_saved)
1292 regs[ARC_FP_REGNUM] = regs[ARC_SP_REGNUM];
1293
1294 return true;
1295 }
1296
1297 /* Some other architectures, like nds32 or arm, try to continue as far as
1298 possible when building a prologue cache (as opposed to when skipping
1299 prologue), so that cache will be as full as possible. However current
1300 code for ARC doesn't recognize some instructions that may modify SP, like
1301 ADD, AND, OR, etc, hence there is no way to guarantee that SP wasn't
1302 clobbered by the skipped instruction. Potential existence of extension
1303 instruction, which may do anything they want makes this even more complex,
1304 so it is just better to halt on a first unrecognized instruction. */
1305
1306 return false;
1307}
1308
1309/* Analyze the prologue and update the corresponding frame cache for the frame
1310 unwinder for unwinding frames that doesn't have debug info. In such
1311 situation GDB attempts to parse instructions in the prologue to understand
1312 where each register is saved.
1313
1314 If CACHE is not NULL, then it will be filled with information about saved
1315 registers.
1316
1317 There are several variations of prologue which GDB may encounter. "Full"
1318 prologue looks like this:
1319
1320 sub sp,sp,<imm> ; Space for variadic arguments.
1321 push blink ; Store return address.
1322 push r13 ; Store callee saved registers (up to R26/GP).
1323 push r14
1324 push fp ; Store frame pointer.
1325 mov fp,sp ; Update frame pointer.
1326 sub sp,sp,<imm> ; Create space for local vars on the stack.
1327
1328 Depending on compiler options lots of things may change:
1329
1330 1) BLINK is not saved in leaf functions.
1331 2) Frame pointer is not saved and updated if -fomit-frame-pointer is used.
1332 3) 16-bit versions of those instructions may be used.
1333 4) Instead of a sequence of several push'es, compiler may instead prefer to
1334 do one subtract on stack pointer and then store registers using normal
1335 store, that doesn't update SP. Like this:
1336
1337
1338 sub sp,sp,8 ; Create space for callee-saved registers.
1339 st r13,[sp,4] ; Store callee saved registers (up to R26/GP).
1340 st r14,[sp,0]
1341
1342 5) ENTER_S instruction can encode most of prologue sequence in one
1343 instruction (except for those subtracts for variadic arguments and local
1344 variables).
1345 6) GCC may use "millicode" functions from libgcc to store callee-saved
1346 registers with minimal code-size requirements. This function currently
1347 doesn't support this.
1348
1349 ENTRYPOINT is a function entry point where prologue starts.
1350
1351 LIMIT_PC is a maximum possible end address of prologue (meaning address
1352 of first instruction after the prologue). It might also point to the middle
1353 of prologue if execution has been stopped by the breakpoint at this address
1354 - in this case debugger should analyze prologue only up to this address,
1355 because further instructions haven't been executed yet.
1356
1357 Returns address of the first instruction after the prologue. */
1358
1359static CORE_ADDR
1360arc_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR entrypoint,
1361 const CORE_ADDR limit_pc, struct arc_frame_cache *cache)
1362{
1363 arc_debug_printf ("entrypoint=%s, limit_pc=%s",
1364 paddress (gdbarch, entrypoint),
1365 paddress (gdbarch, limit_pc));
1366
1367 /* Prologue values. Only core registers can be stored. */
1368 pv_t regs[ARC_LAST_CORE_REGNUM + 1];
1369 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1370 regs[i] = pv_register (i, 0);
1372
1373 CORE_ADDR current_prologue_end = entrypoint;
1374
1375 /* Look at each instruction in the prologue. */
1376 while (current_prologue_end < limit_pc)
1377 {
1378 struct arc_instruction insn;
1379
1381 arc_insn_decode (current_prologue_end, dis.disasm_info (),
1382 arc_delayed_print_insn, &insn);
1383
1384 if (arc_debug)
1385 arc_insn_dump (insn);
1386
1387 /* If this instruction is in the prologue, fields in the cache will be
1388 updated, and the saved registers mask may be updated. */
1389 if (!arc_is_in_prologue (gdbarch, insn, regs, &stack))
1390 {
1391 /* Found an instruction that is not in the prologue. */
1392 arc_debug_printf ("End of prologue reached at address %s",
1393 paddress (gdbarch, insn.address));
1394 break;
1395 }
1396
1397 current_prologue_end = arc_insn_get_linear_next_pc (insn);
1398 }
1399
1400 if (cache != NULL)
1401 {
1402 /* Figure out if it is a frame pointer or just a stack pointer. */
1404 {
1406 cache->frame_base_offset = -regs[ARC_FP_REGNUM].k;
1407 }
1408 else
1409 {
1411 cache->frame_base_offset = -regs[ARC_SP_REGNUM].k;
1412 }
1413
1414 /* Assign offset from old SP to all saved registers. */
1415 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1416 {
1417 CORE_ADDR offset;
1418 if (stack.find_reg (gdbarch, i, &offset))
1419 cache->saved_regs[i].set_addr (offset);
1420 }
1421 }
1422
1423 return current_prologue_end;
1424}
1425
1426/* Estimated maximum prologue length in bytes. This should include:
1427 1) Store instruction for each callee-saved register (R25 - R13 + 1)
1428 2) Two instructions for FP
1429 3) One for BLINK
1430 4) Three substract instructions for SP (for variadic args, for
1431 callee saved regs and for local vars) and assuming that those SUB use
1432 long-immediate (hence double length).
1433 5) Stores of arguments registers are considered part of prologue too
1434 (R7 - R1 + 1).
1435 This is quite an extreme case, because even with -O0 GCC will collapse first
1436 two SUBs into one and long immediate values are quite unlikely to appear in
1437 this case, but still better to overshoot a bit - prologue analysis will
1438 anyway stop at the first instruction that doesn't fit prologue, so this
1439 limit will be rarely reached. */
1440
1441const static int MAX_PROLOGUE_LENGTH
1442 = 4 * (ARC_R25_REGNUM - ARC_R13_REGNUM + 1 + 2 + 1 + 6
1444
1445/* Implement the "skip_prologue" gdbarch method.
1446
1447 Skip the prologue for the function at PC. This is done by checking from
1448 the line information read from the DWARF, if possible; otherwise, we scan
1449 the function prologue to find its end. */
1450
1451static CORE_ADDR
1452arc_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1453{
1454 arc_debug_printf ("pc = %s", paddress (gdbarch, pc));
1455
1456 CORE_ADDR func_addr;
1457 const char *func_name;
1458
1459 /* See what the symbol table says. */
1460 if (find_pc_partial_function (pc, &func_name, &func_addr, NULL))
1461 {
1462 /* Found a function. */
1463 CORE_ADDR postprologue_pc
1464 = skip_prologue_using_sal (gdbarch, func_addr);
1465
1466 if (postprologue_pc != 0)
1467 return std::max (pc, postprologue_pc);
1468 }
1469
1470 /* No prologue info in symbol table, have to analyze prologue. */
1471
1472 /* Find an upper limit on the function prologue using the debug
1473 information. If there is no debug information about prologue end, then
1474 skip_prologue_using_sal will return 0. */
1475 CORE_ADDR limit_pc = skip_prologue_using_sal (gdbarch, pc);
1476
1477 /* If there is no debug information at all, it is required to give some
1478 semi-arbitrary hard limit on amount of bytes to scan during prologue
1479 analysis. */
1480 if (limit_pc == 0)
1481 limit_pc = pc + MAX_PROLOGUE_LENGTH;
1482
1483 /* Find the address of the first instruction after the prologue by scanning
1484 through it - no other information is needed, so pass NULL as a cache. */
1485 return arc_analyze_prologue (gdbarch, pc, limit_pc, NULL);
1486}
1487
1488/* Implement the "print_insn" gdbarch method.
1489
1490 arc_get_disassembler () may return different functions depending on bfd
1491 type, so it is not possible to pass print_insn directly to
1492 set_gdbarch_print_insn (). Instead this wrapper function is used. It also
1493 may be used by other functions to get disassemble_info for address. It is
1494 important to note, that those print_insn from opcodes always print
1495 instruction to the stream specified in the INFO. If this is not desired,
1496 then either `print_insn` function in INFO should be set to some function
1497 that will not print, or `stream` should be different from standard
1498 gdb_stdlog. */
1499
1500int
1501arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info)
1502{
1503 /* Standard BFD "machine number" field allows libopcodes disassembler to
1504 distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM
1505 and HS, which have some difference between. There are two ways to specify
1506 what is the target core:
1507 1) via the disassemble_info->disassembler_options;
1508 2) otherwise libopcodes will use private (architecture-specific) ELF
1509 header.
1510
1511 Using disassembler_options is preferable, because it comes directly from
1512 GDBserver which scanned an actual ARC core identification info. However,
1513 not all GDBservers report core architecture, so as a fallback GDB still
1514 should support analysis of ELF header. The libopcodes disassembly code
1515 uses the section to find the BFD and the BFD to find the ELF header,
1516 therefore this function should set disassemble_info->section properly.
1517
1518 disassembler_options was already set by non-target specific code with
1519 proper options obtained via gdbarch_disassembler_options ().
1520
1521 This function might be called multiple times in a sequence, reusing same
1522 disassemble_info. */
1523 if ((info->disassembler_options == NULL) && (info->section == NULL))
1524 {
1525 struct obj_section *s = find_pc_section (addr);
1526 if (s != NULL)
1527 info->section = s->the_bfd_section;
1528 }
1529
1530 return default_print_insn (addr, info);
1531}
1532
1533/* Baremetal breakpoint instructions.
1534
1535 ARC supports both big- and little-endian. However, instructions for
1536 little-endian processors are encoded in the middle-endian: half-words are
1537 in big-endian, while bytes inside the half-words are in little-endian; data
1538 is represented in the "normal" little-endian. Big-endian processors treat
1539 data and code identically.
1540
1541 Assuming the number 0x01020304, it will be presented this way:
1542
1543 Address : N N+1 N+2 N+3
1544 little-endian : 0x04 0x03 0x02 0x01
1545 big-endian : 0x01 0x02 0x03 0x04
1546 ARC middle-endian : 0x02 0x01 0x04 0x03
1547 */
1548
1549static const gdb_byte arc_brk_s_be[] = { 0x7f, 0xff };
1550static const gdb_byte arc_brk_s_le[] = { 0xff, 0x7f };
1551static const gdb_byte arc_brk_be[] = { 0x25, 0x6f, 0x00, 0x3f };
1552static const gdb_byte arc_brk_le[] = { 0x6f, 0x25, 0x3f, 0x00 };
1553
1554/* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff
1555 (little endian) or 0xff7f (big endian). We used to insert BRK_S even
1556 instead of 32-bit instructions, which works mostly ok, unless breakpoint is
1557 inserted into delay slot instruction. In this case if branch is taken
1558 BLINK value will be set to address of instruction after delay slot, however
1559 if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S,
1560 then BLINK value will have an invalid value - it will point to the address
1561 after the BRK_S (which was there at the moment of branch execution) while
1562 it should point to the address after the 32-bit long instruction. To avoid
1563 such issues this function disassembles instruction at target location and
1564 evaluates it value.
1565
1566 ARC 600 supports only 16-bit BRK_S.
1567
1568 NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S]
1569 is much better because it doesn't commit unlike TRAP_S, so it can be set in
1570 delay slots; however it cannot be used in user-mode, hence usage of TRAP_S
1571 in GDB for user-space. */
1572
1573/* Implement the "breakpoint_kind_from_pc" gdbarch method. */
1574
1575static int
1577{
1578 size_t length_with_limm = gdb_insn_length (gdbarch, *pcptr);
1579
1580 /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with
1581 BRK. LIMM is part of instruction length, so it can be either 4 or 8
1582 bytes for 32-bit instructions. */
1583 if ((length_with_limm == 4 || length_with_limm == 8)
1585 return sizeof (arc_brk_le);
1586 else
1587 return sizeof (arc_brk_s_le);
1588}
1589
1590/* Implement the "sw_breakpoint_from_kind" gdbarch method. */
1591
1592static const gdb_byte *
1594{
1595 gdb_assert (kind == 2 || kind == 4);
1596 *size = kind;
1597
1598 if (kind == sizeof (arc_brk_le))
1599 {
1600 return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1601 ? arc_brk_be
1602 : arc_brk_le);
1603 }
1604 else
1605 {
1606 return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1607 ? arc_brk_s_be
1608 : arc_brk_s_le);
1609 }
1610}
1611
1612/* Implement the "frame_align" gdbarch method. */
1613
1614static CORE_ADDR
1615arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1616{
1617 return align_down (sp, 4);
1618}
1619
1620/* Dump the frame info. Used for internal debugging only. */
1621
1622static void
1623arc_print_frame_cache (struct gdbarch *gdbarch, const char *message,
1624 struct arc_frame_cache *cache, int addresses_known)
1625{
1626 arc_debug_printf ("frame_info %s", message);
1627 arc_debug_printf ("prev_sp = %s", paddress (gdbarch, cache->prev_sp));
1628 arc_debug_printf ("frame_base_reg = %i", cache->frame_base_reg);
1629 arc_debug_printf ("frame_base_offset = %s",
1630 plongest (cache->frame_base_offset));
1631
1632 for (int i = 0; i <= ARC_BLINK_REGNUM; i++)
1633 {
1634 if (cache->saved_regs[i].is_addr ())
1635 arc_debug_printf ("saved register %s at %s %s",
1637 (addresses_known) ? "address" : "offset",
1638 paddress (gdbarch, cache->saved_regs[i].addr ()));
1639 }
1640}
1641
1642/* Frame unwinder for normal frames. */
1643
1644static struct arc_frame_cache *
1646{
1647 arc_debug_printf ("called");
1648
1649 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1650
1651 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
1652 CORE_ADDR entrypoint, prologue_end;
1653 if (find_pc_partial_function (block_addr, NULL, &entrypoint, &prologue_end))
1654 {
1655 struct symtab_and_line sal = find_pc_line (entrypoint, 0);
1656 CORE_ADDR prev_pc = get_frame_pc (this_frame);
1657 if (sal.line == 0)
1658 /* No line info so use current PC. */
1659 prologue_end = prev_pc;
1660 else if (sal.end < prologue_end)
1661 /* The next line begins after the function end. */
1662 prologue_end = sal.end;
1663
1664 prologue_end = std::min (prologue_end, prev_pc);
1665 }
1666 else
1667 {
1668 /* If find_pc_partial_function returned nothing then there is no symbol
1669 information at all for this PC. Currently it is assumed in this case
1670 that current PC is entrypoint to function and try to construct the
1671 frame from that. This is, probably, suboptimal, for example ARM
1672 assumes in this case that program is inside the normal frame (with
1673 frame pointer). ARC, perhaps, should try to do the same. */
1674 entrypoint = get_frame_register_unsigned (this_frame,
1676 prologue_end = entrypoint + MAX_PROLOGUE_LENGTH;
1677 }
1678
1679 /* Allocate new frame cache instance and space for saved register info.
1680 FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */
1681 struct arc_frame_cache *cache
1683 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1684
1685 arc_analyze_prologue (gdbarch, entrypoint, prologue_end, cache);
1686
1687 if (arc_debug)
1688 arc_print_frame_cache (gdbarch, "after prologue", cache, false);
1689
1690 CORE_ADDR unwound_fb = get_frame_register_unsigned (this_frame,
1691 cache->frame_base_reg);
1692 if (unwound_fb == 0)
1693 return cache;
1694 cache->prev_sp = unwound_fb + cache->frame_base_offset;
1695
1696 for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++)
1697 {
1698 if (cache->saved_regs[i].is_addr ())
1699 cache->saved_regs[i].set_addr (cache->saved_regs[i].addr ()
1700 + cache->prev_sp);
1701 }
1702
1703 if (arc_debug)
1704 arc_print_frame_cache (gdbarch, "after previous SP found", cache, true);
1705
1706 return cache;
1707}
1708
1709/* Implement the "this_id" frame_unwind method. */
1710
1711static void
1712arc_frame_this_id (frame_info_ptr this_frame, void **this_cache,
1713 struct frame_id *this_id)
1714{
1715 arc_debug_printf ("called");
1716
1717 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1718
1719 if (*this_cache == NULL)
1720 *this_cache = arc_make_frame_cache (this_frame);
1721 struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache);
1722
1723 CORE_ADDR stack_addr = cache->prev_sp;
1724
1725 /* There are 4 possible situation which decide how frame_id->code_addr is
1726 evaluated:
1727
1728 1) Function is compiled with option -g. Then frame_id will be created
1729 in dwarf_* function and not in this function. NB: even if target
1730 binary is compiled with -g, some std functions like __start and _init
1731 are not, so they still will follow one of the following choices.
1732
1733 2) Function is compiled without -g and binary hasn't been stripped in
1734 any way. In this case GDB still has enough information to evaluate
1735 frame code_addr properly. This case is covered by call to
1736 get_frame_func ().
1737
1738 3) Binary has been striped with option -g (strip debug symbols). In
1739 this case there is still enough symbols for get_frame_func () to work
1740 properly, so this case is also covered by it.
1741
1742 4) Binary has been striped with option -s (strip all symbols). In this
1743 case GDB cannot get function start address properly, so we return current
1744 PC value instead.
1745 */
1746 CORE_ADDR code_addr = get_frame_func (this_frame);
1747 if (code_addr == 0)
1748 code_addr = get_frame_register_unsigned (this_frame,
1750
1751 *this_id = frame_id_build (stack_addr, code_addr);
1752}
1753
1754/* Implement the "prev_register" frame_unwind method. */
1755
1756static struct value *
1758 void **this_cache, int regnum)
1759{
1760 if (*this_cache == NULL)
1761 *this_cache = arc_make_frame_cache (this_frame);
1762 struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache);
1763
1764 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1765
1766 /* If we are asked to unwind the PC, then we need to return BLINK instead:
1767 the saved value of PC points into this frame's function's prologue, not
1768 the next frame's function's resume location. */
1771
1772 /* SP is a special case - we should return prev_sp, because
1773 trad_frame_get_prev_register will return _current_ SP value.
1774 Alternatively we could have stored cache->prev_sp in the cache->saved
1775 regs, but here we follow the lead of AArch64, ARM and Xtensa and will
1776 leave that logic in this function, instead of prologue analyzers. That I
1777 think is a bit more clear as `saved_regs` should contain saved regs, not
1778 computable.
1779
1780 Because value has been computed, "got_constant" should be used, so that
1781 returned value will be a "not_lval" - immutable. */
1782
1784 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1785
1786 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
1787}
1788
1789/* Implement the "init_reg" dwarf2_frame method. */
1790
1791static void
1793 struct dwarf2_frame_state_reg *reg,
1795{
1797 /* The return address column. */
1798 reg->how = DWARF2_FRAME_REG_RA;
1799 else if (regnum == gdbarch_sp_regnum (gdbarch))
1800 /* The call frame address. */
1802}
1803
1804/* Signal trampoline frame unwinder. Allows frame unwinding to happen
1805 from within signal handlers. */
1806
1807static struct arc_frame_cache *
1809{
1810 arc_debug_printf ("called");
1811
1812 gdbarch *arch = get_frame_arch (this_frame);
1813 arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (arch);
1814
1815 /* Allocate new frame cache instance and space for saved register info. */
1816 struct arc_frame_cache *cache = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache);
1817 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1818
1819 /* Get the stack pointer and use it as the frame base. */
1820 cache->prev_sp = arc_frame_base_address (this_frame, NULL);
1821
1822 /* If the ARC-private target-dependent info doesn't have a table of
1823 offsets of saved register contents within an OS signal context
1824 structure, then there is nothing to analyze. */
1825 if (tdep->sc_reg_offset == NULL)
1826 return cache;
1827
1828 /* Find the address of the sigcontext structure. */
1829 CORE_ADDR addr = tdep->sigcontext_addr (this_frame);
1830
1831 /* For each register, if its contents have been saved within the
1832 sigcontext structure, determine the address of those contents. */
1833 gdb_assert (tdep->sc_num_regs <= (ARC_LAST_REGNUM + 1));
1834 for (int i = 0; i < tdep->sc_num_regs; i++)
1835 {
1836 if (tdep->sc_reg_offset[i] != ARC_OFFSET_NO_REGISTER)
1837 cache->saved_regs[i].set_addr (addr + tdep->sc_reg_offset[i]);
1838 }
1839
1840 return cache;
1841}
1842
1843/* Implement the "this_id" frame_unwind method for signal trampoline
1844 frames. */
1845
1846static void
1848 void **this_cache, struct frame_id *this_id)
1849{
1850 arc_debug_printf ("called");
1851
1852 if (*this_cache == NULL)
1853 *this_cache = arc_make_sigtramp_frame_cache (this_frame);
1854
1855 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1856 struct arc_frame_cache *cache = (struct arc_frame_cache *) *this_cache;
1857 CORE_ADDR stack_addr = cache->prev_sp;
1858 CORE_ADDR code_addr
1860 *this_id = frame_id_build (stack_addr, code_addr);
1861}
1862
1863/* Get a register from a signal handler frame. */
1864
1865static struct value *
1867 void **this_cache, int regnum)
1868{
1869 arc_debug_printf ("regnum = %d", regnum);
1870
1871 /* Make sure we've initialized the cache. */
1872 if (*this_cache == NULL)
1873 *this_cache = arc_make_sigtramp_frame_cache (this_frame);
1874
1875 struct arc_frame_cache *cache = (struct arc_frame_cache *) *this_cache;
1876 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
1877}
1878
1879/* Frame sniffer for signal handler frame. Only recognize a frame if we
1880 have a sigcontext_addr handler in the target dependency. */
1881
1882static int
1884 frame_info_ptr this_frame,
1885 void **this_cache)
1886{
1887 arc_debug_printf ("called");
1888
1889 gdbarch *arch = get_frame_arch (this_frame);
1890 arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (arch);
1891
1892 /* If we have a sigcontext_addr handler, then just return 1 (same as the
1893 "default_frame_sniffer ()"). */
1894 return (tdep->sigcontext_addr != NULL && tdep->is_sigtramp != NULL
1895 && tdep->is_sigtramp (this_frame));
1896}
1897
1898/* Structure defining the ARC ordinary frame unwind functions. Since we are
1899 the fallback unwinder, we use the default frame sniffer, which always
1900 accepts the frame. */
1901
1902static const struct frame_unwind arc_frame_unwind = {
1903 "arc prologue",
1908 NULL,
1910 NULL,
1911 NULL
1912};
1913
1914/* Structure defining the ARC signal frame unwind functions. Custom
1915 sniffer is used, because this frame must be accepted only in the right
1916 context. */
1917
1919 "arc sigtramp",
1924 NULL,
1926 NULL,
1927 NULL
1928};
1929
1930
1937
1938static enum arc_isa
1939mach_type_to_arc_isa (const unsigned long mach)
1940{
1941 switch (mach)
1942 {
1943 case bfd_mach_arc_arc600:
1944 case bfd_mach_arc_arc601:
1945 case bfd_mach_arc_arc700:
1946 return ARC_ISA_ARCV1;
1947 case bfd_mach_arc_arcv2:
1948 return ARC_ISA_ARCV2;
1949 default:
1950 internal_error (_("unknown machine id %lu"), mach);
1951 }
1952}
1953
1954/* See arc-tdep.h. */
1955
1957arc_arch_features_create (const bfd *abfd, const unsigned long mach)
1958{
1959 /* Use 4 as a fallback value. */
1960 int reg_size = 4;
1961
1962 /* Try to guess the features parameters by looking at the binary to be
1963 executed. If the user is providing a binary that does not match the
1964 target, then tough luck. This is the last effort to makes sense of
1965 what's going on. */
1966 if (abfd != nullptr && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
1967 {
1968 unsigned char eclass = elf_elfheader (abfd)->e_ident[EI_CLASS];
1969
1970 if (eclass == ELFCLASS32)
1971 reg_size = 4;
1972 else if (eclass == ELFCLASS64)
1973 reg_size = 8;
1974 else
1975 internal_error (_("unknown ELF header class %d"), eclass);
1976 }
1977
1978 /* MACH from a bfd_arch_info struct is used here. It should be a safe
1979 bet, as it looks like the struct is always initialized even when we
1980 don't pass any elf file to GDB at all (it uses default arch in that
1981 case). */
1982 arc_isa isa = mach_type_to_arc_isa (mach);
1983
1984 return arc_arch_features (reg_size, isa);
1985}
1986
1987/* Look for obsolete core feature names in TDESC. */
1988
1989static const struct tdesc_feature *
1991{
1992 const struct tdesc_feature *feat = nullptr;
1993
1995
1996 if (feat == nullptr)
1998
1999 if (feat == nullptr)
2000 feat = tdesc_find_feature
2002
2003 return feat;
2004}
2005
2006/* Look for obsolete aux feature names in TDESC. */
2007
2008static const struct tdesc_feature *
2010{
2012}
2013
2014/* Based on the MACH value, determines which core register features set
2015 must be used. */
2016
2017static arc_register_feature *
2018determine_core_reg_feature_set (const unsigned long mach)
2019{
2020 switch (mach_type_to_arc_isa (mach))
2021 {
2022 case ARC_ISA_ARCV1:
2024 case ARC_ISA_ARCV2:
2026 default:
2027 gdb_assert_not_reached
2028 ("Unknown machine type to determine the core feature set.");
2029 }
2030}
2031
2032/* At the moment, there is only 1 auxiliary register features set.
2033 This is a place holder for future extendability. */
2034
2035static const arc_register_feature *
2040
2041/* Update accumulator register names (ACCH/ACCL) for r58 and r59 in the
2042 register sets. The endianness determines the assignment:
2043
2044 ,------.------.
2045 | acch | accl |
2046 ,----|------+------|
2047 | LE | r59 | r58 |
2048 | BE | r58 | r59 |
2049 `----^------^------' */
2050
2051static void
2052arc_update_acc_reg_names (const int byte_order)
2053{
2054 const char *r58_alias
2055 = byte_order == BFD_ENDIAN_LITTLE ? "accl" : "acch";
2056 const char *r59_alias
2057 = byte_order == BFD_ENDIAN_LITTLE ? "acch" : "accl";
2058
2059 /* Subscript 1 must be OK because those registers have 2 names. */
2060 arc_v1_core_reg_feature.registers[ARC_R58_REGNUM].names[1] = r58_alias;
2061 arc_v1_core_reg_feature.registers[ARC_R59_REGNUM].names[1] = r59_alias;
2062 arc_v2_core_reg_feature.registers[ARC_R58_REGNUM].names[1] = r58_alias;
2063 arc_v2_core_reg_feature.registers[ARC_R59_REGNUM].names[1] = r59_alias;
2064}
2065
2066/* Go through all the registers in REG_SET and check if they exist
2067 in FEATURE. The TDESC_DATA is updated with the register number
2068 in REG_SET if it is found in the feature. If a required register
2069 is not found, this function returns false. */
2070
2071static bool
2073 const struct tdesc_feature *feature,
2074 const struct arc_register_feature *reg_set)
2075{
2076 for (const auto &reg : reg_set->registers)
2077 {
2078 bool found = false;
2079
2080 for (const char *name : reg.names)
2081 {
2082 found
2083 = tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
2084
2085 if (found)
2086 break;
2087 }
2088
2089 if (!found && reg.required_p)
2090 {
2091 std::ostringstream reg_names;
2092 for (std::size_t i = 0; i < reg.names.size(); ++i)
2093 {
2094 if (i == 0)
2095 reg_names << "'" << reg.names[0] << "'";
2096 else
2097 reg_names << " or '" << reg.names[0] << "'";
2098 }
2099 arc_print (_("Error: Cannot find required register(s) %s "
2100 "in feature '%s'.\n"), reg_names.str ().c_str (),
2101 feature->name.c_str ());
2102 return false;
2103 }
2104 }
2105
2106 return true;
2107}
2108
2109/* Check for the existance of "lp_start" and "lp_end" in target description.
2110 If both are present, assume there is hardware loop support in the target.
2111 This can be improved by looking into "lpc_size" field of "isa_config"
2112 auxiliary register. */
2113
2114static bool
2116 struct tdesc_arch_data *data)
2117{
2118 const auto feature_aux = tdesc_find_feature (tdesc, ARC_AUX_FEATURE_NAME);
2119 const auto aux_regset = determine_aux_reg_feature_set ();
2120
2121 if (feature_aux == nullptr)
2122 return false;
2123
2124 bool hw_loop_p = false;
2125 const auto lp_start_name =
2126 aux_regset->registers[ARC_LP_START_REGNUM - ARC_FIRST_AUX_REGNUM].names[0];
2127 const auto lp_end_name =
2128 aux_regset->registers[ARC_LP_END_REGNUM - ARC_FIRST_AUX_REGNUM].names[0];
2129
2130 hw_loop_p = tdesc_numbered_register (feature_aux, data,
2131 ARC_LP_START_REGNUM, lp_start_name);
2132 hw_loop_p &= tdesc_numbered_register (feature_aux, data,
2133 ARC_LP_END_REGNUM, lp_end_name);
2134
2135 return hw_loop_p;
2136}
2137
2138/* Initialize target description for the ARC.
2139
2140 Returns true if input TDESC was valid and in this case it will assign TDESC
2141 and TDESC_DATA output parameters. */
2142
2143static bool
2144arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc,
2146{
2147 const struct target_desc *tdesc_loc = info.target_desc;
2148 arc_debug_printf ("Target description initialization.");
2149
2150 /* If target doesn't provide a description, use the default ones. */
2151 if (!tdesc_has_registers (tdesc_loc))
2152 {
2154 = arc_arch_features_create (info.abfd,
2155 info.bfd_arch_info->mach);
2157 }
2158 gdb_assert (tdesc_loc != nullptr);
2159
2160 arc_debug_printf ("Have got a target description");
2161
2162 const struct tdesc_feature *feature_core
2164 const struct tdesc_feature *feature_aux
2166
2167 /* Maybe there still is a chance to salvage the input. */
2168 if (feature_core == nullptr)
2169 feature_core = find_obsolete_core_names (tdesc_loc);
2170 if (feature_aux == nullptr)
2171 feature_aux = find_obsolete_aux_names (tdesc_loc);
2172
2173 if (feature_core == nullptr)
2174 {
2175 arc_print (_("Error: Cannot find required feature '%s' in supplied "
2176 "target description.\n"), ARC_CORE_FEATURE_NAME);
2177 return false;
2178 }
2179
2180 if (feature_aux == nullptr)
2181 {
2182 arc_print (_("Error: Cannot find required feature '%s' in supplied "
2183 "target description.\n"), ARC_AUX_FEATURE_NAME);
2184 return false;
2185 }
2186
2187 const arc_register_feature *arc_core_reg_feature
2188 = determine_core_reg_feature_set (info.bfd_arch_info->mach);
2189 const arc_register_feature *arc_aux_reg_feature
2191
2192 tdesc_arch_data_up tdesc_data_loc = tdesc_data_alloc ();
2193
2194 arc_update_acc_reg_names (info.byte_order);
2195
2196 bool valid_p = arc_check_tdesc_feature (tdesc_data_loc.get (),
2197 feature_core,
2198 arc_core_reg_feature);
2199
2200 valid_p &= arc_check_tdesc_feature (tdesc_data_loc.get (),
2201 feature_aux,
2202 arc_aux_reg_feature);
2203
2204 if (!valid_p)
2205 {
2206 arc_debug_printf ("Target description is not valid");
2207 return false;
2208 }
2209
2210 *tdesc = tdesc_loc;
2211 *tdesc_data = std::move (tdesc_data_loc);
2212
2213 return true;
2214}
2215
2216/* Implement the type_align gdbarch function. */
2217
2218static ULONGEST
2220{
2221 switch (type->code ())
2222 {
2223 case TYPE_CODE_PTR:
2224 case TYPE_CODE_FUNC:
2225 case TYPE_CODE_FLAGS:
2226 case TYPE_CODE_INT:
2227 case TYPE_CODE_RANGE:
2228 case TYPE_CODE_FLT:
2229 case TYPE_CODE_ENUM:
2230 case TYPE_CODE_REF:
2231 case TYPE_CODE_RVALUE_REF:
2232 case TYPE_CODE_CHAR:
2233 case TYPE_CODE_BOOL:
2234 case TYPE_CODE_DECFLOAT:
2235 case TYPE_CODE_METHODPTR:
2236 case TYPE_CODE_MEMBERPTR:
2238 return std::min<ULONGEST> (4, type->length ());
2239 default:
2240 return 0;
2241 }
2242}
2243
2244/* Implement the "init" gdbarch method. */
2245
2246static struct gdbarch *
2248{
2249 const struct target_desc *tdesc;
2251
2252 arc_debug_printf ("Architecture initialization.");
2253
2254 if (!arc_tdesc_init (info, &tdesc, &tdesc_data))
2255 return nullptr;
2256
2257 /* Allocate the ARC-private target-dependent information structure, and the
2258 GDB target-independent information structure. */
2261 arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (gdbarch);
2262 tdep->jb_pc = -1; /* No longjmp support by default. */
2264
2265 /* Data types. */
2278
2280
2282
2283 /* tdesc_use_registers expects gdbarch_num_regs to return number of registers
2284 parsed by gdbarch_init, and then it will add all of the remaining
2285 registers and will increase number of registers. */
2291 set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */
2292
2295
2298
2300
2302
2305
2308
2309 /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */
2312 else
2314
2316
2318
2320
2321 /* "nonsteppable" watchpoint means that watchpoint triggers before
2322 instruction is committed, therefore it is required to remove watchpoint
2323 to step though instruction that triggers it. ARC watchpoints trigger
2324 only after instruction is committed, thus there is no need to remove
2325 them. In fact on ARC watchpoint for memory writes may trigger with more
2326 significant delay, like one or two instructions, depending on type of
2327 memory where write is performed (CCM or external) and next instruction
2328 after the memory write. */
2330
2331 /* This doesn't include possible long-immediate value. */
2333
2334 /* Frame unwinders and sniffers. */
2340
2341 /* Setup stuff specific to a particular environment (baremetal or Linux).
2342 It can override functions set earlier. */
2344
2345 if (tdep->jb_pc >= 0)
2347
2348 /* Disassembler options. Enforce CPU if it was specified in XML target
2349 description, otherwise use default method of determining CPU (ELF private
2350 header). */
2351 if (info.target_desc != NULL)
2352 {
2353 const struct bfd_arch_info *tdesc_arch
2354 = tdesc_architecture (info.target_desc);
2355 if (tdesc_arch != NULL)
2356 {
2358 /* FIXME: It is not really good to change disassembler options
2359 behind the scene, because that might override options
2360 specified by the user. However as of now ARC doesn't support
2361 `set disassembler-options' hence this code is the only place
2362 where options are changed. It also changes options for all
2363 existing gdbarches, which also can be problematic, if
2364 arc_gdbarch_init will start reusing existing gdbarch
2365 instances. */
2366 /* Target description specifies a BFD architecture, which is
2367 different from ARC cpu, as accepted by disassembler (and most
2368 other ARC tools), because cpu values are much more fine grained -
2369 there can be multiple cpu values per single BFD architecture. As
2370 a result this code should translate architecture to some cpu
2371 value. Since there is no info on exact cpu configuration, it is
2372 best to use the most feature-rich CPU, so that disassembler will
2373 recognize all instructions available to the specified
2374 architecture. */
2375 switch (tdesc_arch->mach)
2376 {
2377 case bfd_mach_arc_arc601:
2378 arc_disassembler_options = xstrdup ("cpu=arc601");
2379 break;
2380 case bfd_mach_arc_arc600:
2381 arc_disassembler_options = xstrdup ("cpu=arc600");
2382 break;
2383 case bfd_mach_arc_arc700:
2384 arc_disassembler_options = xstrdup ("cpu=arc700");
2385 break;
2386 case bfd_mach_arc_arcv2:
2387 /* Machine arcv2 has three arches: ARCv2, EM and HS; where ARCv2
2388 is treated as EM. */
2389 if (arc_arch_is_hs (tdesc_arch))
2390 arc_disassembler_options = xstrdup ("cpu=hs38_linux");
2391 else
2392 arc_disassembler_options = xstrdup ("cpu=em4_fpuda");
2393 break;
2394 default:
2396 break;
2397 }
2398 }
2399 }
2400
2403 disassembler_options_arc ());
2404
2405 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
2406
2407 return gdbarch;
2408}
2409
2410/* Implement the "dump_tdep" gdbarch method. */
2411
2412static void
2413arc_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
2414{
2415 arc_gdbarch_tdep *tdep = gdbarch_tdep<arc_gdbarch_tdep> (gdbarch);
2416
2417 gdb_printf (file, "arc_dump_tdep: jb_pc = %i\n", tdep->jb_pc);
2418
2419 gdb_printf (file, "arc_dump_tdep: is_sigtramp = <%s>\n",
2420 host_address_to_string (tdep->is_sigtramp));
2421 gdb_printf (file, "arc_dump_tdep: sigcontext_addr = <%s>\n",
2422 host_address_to_string (tdep->sigcontext_addr));
2423 gdb_printf (file, "arc_dump_tdep: sc_reg_offset = <%s>\n",
2424 host_address_to_string (tdep->sc_reg_offset));
2425 gdb_printf (file, "arc_dump_tdep: sc_num_regs = %d\n",
2426 tdep->sc_num_regs);
2427}
2428
2429/* This command accepts single argument - address of instruction to
2430 disassemble. */
2431
2432static void
2433dump_arc_instruction_command (const char *args, int from_tty)
2434{
2435 struct value *val;
2436 if (args != NULL && strlen (args) > 0)
2437 val = parse_expression (args)->evaluate ();
2438 else
2439 val = access_value_history (0);
2440 val->record_latest ();
2441
2442 CORE_ADDR address = value_as_address (val);
2443 struct arc_instruction insn;
2445 arc_insn_decode (address, dis.disasm_info (), arc_delayed_print_insn, &insn);
2446 arc_insn_dump (insn);
2447}
2448
2449void _initialize_arc_tdep ();
2450void
2452{
2454
2455 /* Register ARC-specific commands with gdb. */
2456
2457 /* Add root prefix command for "maintenance print arc" commands. */
2459 _("ARC-specific maintenance commands for printing GDB "
2460 "internal state."),
2463
2464 add_cmd ("arc-instruction", class_maintenance,
2466 _("Dump arc_instruction structure for specified address."),
2468
2469 /* Debug internals for ARC GDB. */
2471 &arc_debug,
2472 _("Set ARC specific debugging."),
2473 _("Show ARC specific debugging."),
2474 _("When set, ARC specific debugging is enabled."),
2475 NULL, NULL, &setdebuglist, &showdebuglist);
2476}
@ SUB
int regnum
const char *const name
void xfree(void *)
gdb_static_assert(sizeof(splay_tree_key) >=sizeof(CORE_ADDR *))
static enum arc_isa mach_type_to_arc_isa(const unsigned long mach)
Definition arc-tdep.c:1939
static const gdb_byte arc_brk_s_le[]
Definition arc-tdep.c:1550
static const gdb_byte arc_brk_s_be[]
Definition arc-tdep.c:1549
static enum return_value_convention arc_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
Definition arc-tdep.c:1021
static void arc_insn_dump(const struct arc_instruction &insn)
Definition arc-tdep.c:491
static CORE_ADDR arc_frame_base_address(frame_info_ptr this_frame, void **prologue_cache)
Definition arc-tdep.c:1064
void _initialize_arc_tdep()
Definition arc-tdep.c:2451
static void arc_sigtramp_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
Definition arc-tdep.c:1847
static CORE_ADDR arc_analyze_prologue(struct gdbarch *gdbarch, const CORE_ADDR entrypoint, const CORE_ADDR limit_pc, struct arc_frame_cache *cache)
Definition arc-tdep.c:1360
static bool arc_is_in_prologue(struct gdbarch *gdbarch, const struct arc_instruction &insn, pv_t *regs, struct pv_area *stack)
Definition arc-tdep.c:1086
static pv_t arc_pv_get_operand(pv_t *regs, const struct arc_instruction &insn, int operand)
Definition arc-tdep.c:1073
static const int MAX_PROLOGUE_LENGTH
Definition arc-tdep.c:1442
static const gdb_byte arc_brk_le[]
Definition arc-tdep.c:1552
static CORE_ADDR arc_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition arc-tdep.c:1615
static ULONGEST arc_type_align(struct gdbarch *gdbarch, struct type *type)
Definition arc-tdep.c:2219
static const char * ARC_AUX_FEATURE_NAME
Definition arc-tdep.c:136
static struct arc_register_feature arc_v1_core_reg_feature
Definition arc-tdep.c:141
static char * arc_disassembler_options
Definition arc-tdep.c:301
static struct gdbarch * arc_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
Definition arc-tdep.c:2247
static int arc_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
Definition arc-tdep.c:1576
static const struct frame_base arc_normal_base
Definition arc-tdep.c:1931
bool arc_debug
Definition arc-tdep.c:91
static int arc_get_longjmp_target(frame_info_ptr frame, CORE_ADDR *pc)
Definition arc-tdep.c:1000
CORE_ADDR arc_insn_get_linear_next_pc(const struct arc_instruction &insn)
Definition arc-tdep.c:560
static bool arc_tdesc_init(struct gdbarch_info info, const struct target_desc **tdesc, tdesc_arch_data_up *tdesc_data)
Definition arc-tdep.c:2144
static const gdb_byte arc_brk_be[]
Definition arc-tdep.c:1551
static struct arc_register_feature arc_v2_core_reg_feature
Definition arc-tdep.c:215
static const char * ARC_AUX_OBSOLETE_FEATURE_NAME
Definition arc-tdep.c:133
static LONGEST arc_insn_get_operand_value_signed(const struct arc_instruction &insn, unsigned int operand_num)
Definition arc-tdep.c:336
static const struct frame_unwind arc_sigtramp_frame_unwind
Definition arc-tdep.c:1918
static const char * ARC_CORE_V2_REDUCED_OBSOLETE_FEATURE_NAME
Definition arc-tdep.c:131
static void arc_update_acc_reg_names(const int byte_order)
Definition arc-tdep.c:2052
static int arc_insn_get_memory_base_reg(const struct arc_instruction &insn)
Definition arc-tdep.c:365
static CORE_ADDR arc_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
Definition arc-tdep.c:728
arc_arch_features arc_arch_features_create(const bfd *abfd, const unsigned long mach)
Definition arc-tdep.c:1957
static struct value * arc_sigtramp_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
Definition arc-tdep.c:1866
static struct arc_frame_cache * arc_make_frame_cache(frame_info_ptr this_frame)
Definition arc-tdep.c:1645
static int arc_cannot_store_register(struct gdbarch *gdbarch, int regnum)
Definition arc-tdep.c:880
static void arc_write_pc(struct regcache *regcache, CORE_ADDR new_pc)
Definition arc-tdep.c:601
static void arc_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
Definition arc-tdep.c:1712
static int arc_cannot_fetch_register(struct gdbarch *gdbarch, int regnum)
Definition arc-tdep.c:860
static const struct tdesc_feature * find_obsolete_core_names(const struct target_desc *tdesc)
Definition arc-tdep.c:1990
static struct cmd_list_element * maintenance_print_arc_list
Definition arc-tdep.c:95
static const char * ARC_CORE_V1_OBSOLETE_FEATURE_NAME
Definition arc-tdep.c:127
static void arc_virtual_frame_pointer(struct gdbarch *gdbarch, CORE_ADDR pc, int *reg_ptr, LONGEST *offset_ptr)
Definition arc-tdep.c:653
static CORE_ADDR arc_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition arc-tdep.c:1452
static void arc_print_frame_cache(struct gdbarch *gdbarch, const char *message, struct arc_frame_cache *cache, int addresses_known)
Definition arc-tdep.c:1623
static struct value * arc_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
Definition arc-tdep.c:1757
static void arc_extract_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, gdb_byte *valbuf)
Definition arc-tdep.c:906
static const arc_register_feature * determine_aux_reg_feature_set()
Definition arc-tdep.c:2036
static ULONGEST arc_insn_get_operand_value(const struct arc_instruction &insn, unsigned int operand_num)
Definition arc-tdep.c:312
int arc_delayed_print_insn(bfd_vma addr, struct disassemble_info *info)
Definition arc-tdep.c:1501
static const char * ARC_CORE_FEATURE_NAME
Definition arc-tdep.c:135
CORE_ADDR arc_insn_get_branch_target(const struct arc_instruction &insn)
Definition arc-tdep.c:418
static const char * ARC_CORE_V2_OBSOLETE_FEATURE_NAME
Definition arc-tdep.c:129
static void arc_store_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
Definition arc-tdep.c:957
static void arc_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, frame_info_ptr info)
Definition arc-tdep.c:1792
static struct arc_frame_cache * arc_make_sigtramp_frame_cache(frame_info_ptr this_frame)
Definition arc-tdep.c:1808
static bool arc_check_for_hw_loops(const struct target_desc *tdesc, struct tdesc_arch_data *data)
Definition arc-tdep.c:2115
static int arc_sigtramp_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_cache)
Definition arc-tdep.c:1883
static const struct frame_unwind arc_frame_unwind
Definition arc-tdep.c:1902
static CORE_ADDR arc_push_dummy_code(struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache)
Definition arc-tdep.c:847
static const struct tdesc_feature * find_obsolete_aux_names(const struct target_desc *tdesc)
Definition arc-tdep.c:2009
static arc_register_feature * determine_core_reg_feature_set(const unsigned long mach)
Definition arc-tdep.c:2018
static void dump_arc_instruction_command(const char *args, int from_tty)
Definition arc-tdep.c:2433
static const gdb_byte * arc_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
Definition arc-tdep.c:1593
static const struct arc_register_feature arc_common_aux_reg_feature
Definition arc-tdep.c:289
static bool arc_check_tdesc_feature(struct tdesc_arch_data *tdesc_data, const struct tdesc_feature *feature, const struct arc_register_feature *reg_set)
Definition arc-tdep.c:2072
static void arc_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
Definition arc-tdep.c:2413
static CORE_ADDR arc_insn_get_memory_offset(const struct arc_instruction &insn)
Definition arc-tdep.c:384
#define arc_print(fmt, args...)
Definition arc-tdep.h:113
static int arc_mach_is_arc600(struct gdbarch *gdbarch)
Definition arc-tdep.h:150
#define ARC_STATUS32_DE_MASK
Definition arc-tdep.h:108
#define ARC_REGISTER_SIZE
Definition arc-tdep.h:103
static bool arc_arch_is_hs(const struct bfd_arch_info *arch)
Definition arc-tdep.h:172
#define ARC_OFFSET_NO_REGISTER
Definition arc-tdep.h:111
@ ARC_R1_REGNUM
Definition arc-tdep.h:39
@ ARC_LAST_ARG_REGNUM
Definition arc-tdep.h:95
@ ARC_R25_REGNUM
Definition arc-tdep.h:45
@ ARC_PCL_REGNUM
Definition arc-tdep.h:73
@ ARC_R0_REGNUM
Definition arc-tdep.h:38
@ ARC_LAST_REGNUM
Definition arc-tdep.h:91
@ ARC_LIMM_REGNUM
Definition arc-tdep.h:71
@ ARC_LP_END_REGNUM
Definition arc-tdep.h:85
@ ARC_R59_REGNUM
Definition arc-tdep.h:59
@ ARC_FP_REGNUM
Definition arc-tdep.h:49
@ ARC_FIRST_ARG_REGNUM
Definition arc-tdep.h:94
@ ARC_STATUS32_REGNUM
Definition arc-tdep.h:81
@ ARC_BLINK_REGNUM
Definition arc-tdep.h:56
@ ARC_FIRST_AUX_REGNUM
Definition arc-tdep.h:79
@ ARC_RESERVED_REGNUM
Definition arc-tdep.h:65
@ ARC_LAST_CORE_REGNUM
Definition arc-tdep.h:74
@ ARC_SP_REGNUM
Definition arc-tdep.h:51
@ ARC_R13_REGNUM
Definition arc-tdep.h:43
@ ARC_PC_REGNUM
Definition arc-tdep.h:78
@ ARC_R58_REGNUM
Definition arc-tdep.h:58
@ ARC_LP_START_REGNUM
Definition arc-tdep.h:83
#define arc_debug_printf(fmt,...)
Definition arc-tdep.h:119
const target_desc * arc_lookup_target_description(const struct arc_arch_features &features)
Definition arc.c:105
arc_isa
Definition arc.h:25
@ ARC_ISA_ARCV1
Definition arc.h:26
@ ARC_ISA_ARCV2
Definition arc.h:27
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep, gdbarch_supports_arch_info_ftype *supports_arch_info)
int default_print_insn(bfd_vma memaddr, disassemble_info *info)
struct gdbarch * target_gdbarch(void)
static std::vector< const char * > arches
Definition arch-utils.c:685
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition arch-utils.c:177
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
Definition blockframe.c:373
bool find_reg(struct gdbarch *gdbarch, int reg, CORE_ADDR *offset_p)
bool store_would_trash(pv_t addr)
void store(pv_t addr, CORE_ADDR size, pv_t value)
gdbarch * arch() const
Definition regcache.c:231
void cooked_write(int regnum, const gdb_byte *buf)
Definition regcache.c:870
void * get(unsigned key)
Definition registry.h:211
struct cmd_list_element * maintenanceprintlist
Definition cli-cmds.c:151
struct cmd_list_element * showdebuglist
Definition cli-cmds.c:167
struct cmd_list_element * setdebuglist
Definition cli-cmds.c:165
struct cmd_list_element * add_cmd(const char *name, enum command_class theclass, const char *doc, struct cmd_list_element **list)
Definition cli-decode.c:233
set_show_commands add_setshow_boolean_cmd(const char *name, enum command_class theclass, bool *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition cli-decode.c:809
struct cmd_list_element * add_basic_prefix_cmd(const char *name, enum command_class theclass, const char *doc, struct cmd_list_element **subcommands, int allow_unknown, struct cmd_list_element **list)
Definition cli-decode.c:391
@ class_maintenance
Definition command.h:65
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition corefile.c:347
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition defs.h:515
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition defs.h:480
return_value_convention
Definition defs.h:257
@ RETURN_VALUE_REGISTER_CONVENTION
Definition defs.h:260
@ RETURN_VALUE_STRUCT_CONVENTION
Definition defs.h:267
int gdb_insn_length(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition disasm.c:1230
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition frame.c:1369
void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, frame_info_ptr))
Definition frame.c:666
@ DWARF2_FRAME_REG_RA
Definition frame.h:61
@ DWARF2_FRAME_REG_CFA
Definition frame.h:63
expression_up parse_expression(const char *, innermost_block_tracker *=nullptr, parser_flags flags=0)
Definition parse.c:458
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition frame-base.c:93
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
Definition frame.c:1399
CORE_ADDR get_frame_pc(frame_info_ptr frame)
Definition frame.c:2712
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition frame.c:736
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition frame.c:3027
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
Definition frame.c:1098
CORE_ADDR get_frame_address_in_block(frame_info_ptr this_frame)
Definition frame.c:2742
@ SIGTRAMP_FRAME
Definition frame.h:198
@ NORMAL_FRAME
Definition frame.h:187
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition frame.h:825
void set_gdbarch_long_long_bit(struct gdbarch *gdbarch, int long_long_bit)
Definition gdbarch.c:1493
void set_gdbarch_addr_bit(struct gdbarch *gdbarch, int addr_bit)
Definition gdbarch.c:1750
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2054
void set_gdbarch_char_signed(struct gdbarch *gdbarch, int char_signed)
Definition gdbarch.c:1786
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition gdbarch.c:2081
void set_gdbarch_disassembler_options(struct gdbarch *gdbarch, char **disassembler_options)
Definition gdbarch.c:5344
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition gdbarch.c:1396
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
Definition gdbarch.c:2173
void set_gdbarch_valid_disassembler_options(struct gdbarch *gdbarch, const disasm_options_and_args_t *valid_disassembler_options)
Definition gdbarch.c:5361
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
Definition gdbarch.c:4093
void set_gdbarch_write_pc(struct gdbarch *gdbarch, gdbarch_write_pc_ftype *write_pc)
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype *get_longjmp_target)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
int gdbarch_addr_bit(struct gdbarch *gdbarch)
Definition gdbarch.c:1739
void set_gdbarch_push_dummy_code(struct gdbarch *gdbarch, gdbarch_push_dummy_code_ftype *push_dummy_code)
void set_gdbarch_int_bit(struct gdbarch *gdbarch, int int_bit)
Definition gdbarch.c:1459
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition gdbarch.c:2913
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
Definition gdbarch.c:2470
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition gdbarch.c:3574
void set_gdbarch_fp0_regnum(struct gdbarch *gdbarch, int fp0_regnum)
Definition gdbarch.c:2098
void set_gdbarch_double_bit(struct gdbarch *gdbarch, int double_bit)
Definition gdbarch.c:1612
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
void set_gdbarch_cannot_step_breakpoint(struct gdbarch *gdbarch, int cannot_step_breakpoint)
Definition gdbarch.c:3557
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition gdbarch.c:2047
int gdbarch_sp_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2037
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition gdbarch.c:2064
void set_gdbarch_virtual_frame_pointer(struct gdbarch *gdbarch, gdbarch_virtual_frame_pointer_ftype *virtual_frame_pointer)
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype *print_insn)
void set_gdbarch_float_bit(struct gdbarch *gdbarch, int float_bit)
Definition gdbarch.c:1578
int gdbarch_ps_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2071
void set_gdbarch_short_bit(struct gdbarch *gdbarch, int short_bit)
Definition gdbarch.c:1442
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition gdbarch.c:1958
void set_gdbarch_long_bit(struct gdbarch *gdbarch, int long_bit)
Definition gdbarch.c:1476
void set_gdbarch_ptr_bit(struct gdbarch *gdbarch, int ptr_bit)
Definition gdbarch.c:1732
void set_gdbarch_type_align(struct gdbarch *gdbarch, gdbarch_type_align_ftype *type_align)
void set_gdbarch_cannot_store_register(struct gdbarch *gdbarch, gdbarch_cannot_store_register_ftype *cannot_store_register)
void set_gdbarch_cannot_fetch_register(struct gdbarch *gdbarch, gdbarch_cannot_fetch_register_ftype *cannot_fetch_register)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition gdbarch.c:1941
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_double_format(struct gdbarch *gdbarch, const struct floatformat **double_format)
Definition gdbarch.c:1629
void set_gdbarch_float_format(struct gdbarch *gdbarch, const struct floatformat **float_format)
Definition gdbarch.c:1595
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, gdbarch_tdep_up tdep)
Definition gdbarch.c:266
std::unique_ptr< gdbarch_tdep_base > gdbarch_tdep_up
Definition gdbarch.h:73
function_call_return_method
Definition gdbarch.h:114
@ return_method_struct
Definition gdbarch.h:126
const struct floatformat * floatformats_ieee_single[BFD_ENDIAN_UNKNOWN]
Definition gdbtypes.c:85
const struct floatformat * floatformats_ieee_double[BFD_ENDIAN_UNKNOWN]
Definition gdbtypes.c:89
struct type * check_typedef(struct type *type)
Definition gdbtypes.c:2966
size_t size
Definition go32-nat.c:239
info(Component c)
Definition gdbarch.py:41
struct obj_section * find_pc_section(CORE_ADDR pc)
Definition objfiles.c:1128
CORE_ADDR entry_point_address(void)
Definition objfiles.c:371
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition osabi.c:382
pv_t pv_subtract(pv_t a, pv_t b)
pv_t pv_constant(CORE_ADDR k)
pv_t pv_register(int reg, CORE_ADDR k)
int pv_is_identical(pv_t a, pv_t b)
pv_t pv_add_constant(pv_t v, CORE_ADDR k)
int pv_is_register(pv_t a, int r)
int value
Definition py-param.c:79
enum register_status regcache_cooked_read_signed(struct regcache *regcache, int regnum, LONGEST *val)
Definition regcache.c:772
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:796
struct regcache * get_current_regcache(void)
Definition regcache.c:429
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:825
LONGEST frame_base_offset
Definition arc-tdep.c:81
trad_frame_saved_reg * saved_regs
Definition arc-tdep.c:86
CORE_ADDR prev_sp
Definition arc-tdep.c:55
const int * sc_reg_offset
Definition arc-tdep.h:140
bool(* is_sigtramp)(frame_info_ptr)
Definition arc-tdep.h:134
CORE_ADDR(* sigcontext_addr)(frame_info_ptr)
Definition arc-tdep.h:137
std::vector< const char * > names
Definition arc-tdep.c:110
std::vector< struct register_info > registers
Definition arc-tdep.c:122
const char * name
Definition arc-tdep.c:118
enum dwarf2_frame_reg_rule how
Definition frame.h:86
struct disassemble_info * disasm_info()
Definition disasm.h:55
CORE_ADDR addr() const
Definition objfiles.h:385
struct bfd_section * the_bfd_section
Definition objfiles.h:398
CORE_ADDR end
Definition symtab.h:2338
std::vector< tdesc_feature_up > features
bool is_addr() const
Definition trad-frame.h:165
void set_addr(LONGEST addr)
Definition trad-frame.h:102
type_code code() const
Definition gdbtypes.h:956
ULONGEST length() const
Definition gdbtypes.h:983
Definition value.h:130
int record_latest()
Definition value.c:1666
CORE_ADDR address
Definition value.h:658
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition symtab.c:3963
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
Definition symtab.c:3295
tdesc_arch_data_up tdesc_data_alloc(void)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
static const registry< gdbarch >::key< tdesc_arch_data > tdesc_data
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, tdesc_arch_data_up &&early_data, tdesc_unknown_register_ftype unk_reg_cb)
int tdesc_has_registers(const struct target_desc *target_desc)
const struct bfd_arch_info * tdesc_architecture(const struct target_desc *target_desc)
std::unique_ptr< tdesc_arch_data, tdesc_arch_data_deleter > tdesc_arch_data_up
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition target.c:1785
trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct gdbarch *gdbarch)
Definition trad-frame.c:62
struct value * trad_frame_get_prev_register(frame_info_ptr this_frame, trad_frame_saved_reg this_saved_regs[], int regnum)
Definition trad-frame.c:187
const char * print_core_address(struct gdbarch *gdbarch, CORE_ADDR address)
Definition utils.c:3187
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition utils.c:3166
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition utils.c:1886
#define gdb_stderr
Definition utils.h:187
CORE_ADDR value_as_address(struct value *val)
Definition value.c:2636
struct value * access_value_history(int num)
Definition value.c:1709