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xtensa-tdep.c
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1/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
2
3 Copyright (C) 2003-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "solib-svr4.h"
23#include "symtab.h"
24#include "gdbtypes.h"
25#include "gdbcore.h"
26#include "value.h"
27#include "osabi.h"
28#include "regcache.h"
29#include "reggroups.h"
30#include "regset.h"
31
32#include "dwarf2/frame.h"
33#include "frame-base.h"
34#include "frame-unwind.h"
35
36#include "arch-utils.h"
37#include "gdbarch.h"
38
39#include "command.h"
40#include "gdbcmd.h"
41
42#include "xtensa-isa.h"
43#include "xtensa-tdep.h"
44#include "xtensa-config.h"
45#include <algorithm>
46
47
48static unsigned int xtensa_debug_level = 0;
49
50#define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 gdb_printf (gdb_stdlog, "(warn ) " args)
53
54#define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 gdb_printf (gdb_stdlog, "(info ) " args)
57
58#define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 gdb_printf (gdb_stdlog, "(trace) " args)
61
62#define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 gdb_printf (gdb_stdlog, "(verb ) " args)
65
66
67/* According to the ABI, the SP must be aligned to 16-byte boundaries. */
68#define SP_ALIGNMENT 16
69
70
71/* On Windowed ABI, we use a6 through a11 for passing arguments
72 to a function called by GDB because CALL4 is used. */
73#define ARGS_NUM_REGS 6
74#define REGISTER_SIZE 4
75
76
77/* Extract the call size from the return address or PS register. */
78#define PS_CALLINC_SHIFT 16
79#define PS_CALLINC_MASK 0x00030000
80#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
82
83/* On TX, hardware can be configured without Exception Option.
84 There is no PS register in this case. Inside XT-GDB, let us treat
85 it as a virtual read-only register always holding the same value. */
86#define TX_PS 0x20
87
88/* ABI-independent macros. */
89#define ARG_NOF(tdep) \
90 (tdep->call_abi \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92#define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
96
97/* XTENSA_IS_ENTRY tests whether the first byte of an instruction
98 indicates that the instruction is an ENTRY instruction. */
99
100#define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
103
104#define XTENSA_ENTRY_LENGTH 3
105
106/* windowing_enabled() returns true, if windowing is enabled.
107 WOE must be set to 1; EXCM to 0.
108 Note: We assume that EXCM is always 0 for XEA1. */
109
110#define PS_WOE (1<<18)
111#define PS_EXC (1<<4)
112
113/* Big enough to hold the size of the largest register in bytes. */
114#define XTENSA_MAX_REGISTER_SIZE 64
115
116static int
117windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
118{
119 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
120
121 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
122 if (tdep->call_abi == CallAbiCall0Only)
123 return 0;
124
125 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
126}
127
128/* Convert a live A-register number to the corresponding AR-register
129 number. */
130static int
131arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
132{
133 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
134 int arreg;
135
136 arreg = a_regnum - tdep->a0_base;
137 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
138 arreg &= tdep->num_aregs - 1;
139
140 return arreg + tdep->ar_base;
141}
142
143/* Convert a live AR-register number to the corresponding A-register order
144 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
145static int
146areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
147{
148 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
149 int areg;
150
151 areg = ar_regnum - tdep->ar_base;
152 if (areg < 0 || areg >= tdep->num_aregs)
153 return -1;
154 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
155 return (areg > 15) ? -1 : areg;
156}
157
158/* Read Xtensa register directly from the hardware. */
159static unsigned long
161{
162 ULONGEST value;
163
165 return (unsigned long) value;
166}
167
168/* Write Xtensa register directly to the hardware. */
169static void
174
175/* Return the window size of the previous call to the function from which we
176 have just returned.
177
178 This function is used to extract the return value after a called function
179 has returned to the caller. On Xtensa, the register that holds the return
180 value (from the perspective of the caller) depends on what call
181 instruction was used. For now, we are assuming that the call instruction
182 precedes the current address, so we simply analyze the call instruction.
183 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
184 method to call the inferior function. */
185
186static int
187extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
188{
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 int winsize = 4;
191 int insn;
192 gdb_byte buf[4];
193
194 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
195
196 /* Read the previous instruction (should be a call[x]{4|8|12}. */
197 read_memory (pc-3, buf, 3);
198 insn = extract_unsigned_integer (buf, 3, byte_order);
199
200 /* Decode call instruction:
201 Little Endian
202 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
203 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
204 Big Endian
205 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
206 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
207
208 if (byte_order == BFD_ENDIAN_LITTLE)
209 {
210 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
211 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
212 }
213 else
214 {
215 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
216 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
217 }
218 return winsize;
219}
220
221
222/* REGISTER INFORMATION */
223
224/* Find register by name. */
225static int
227{
228 int i;
229 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
230
231 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++)
232 if (strcasecmp (tdep->regmap[i].name, name) == 0)
233 return i;
234
235 return -1;
236}
237
238/* Returns the name of a register. */
239static const char *
241{
242 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
243
244 /* Return the name stored in the register map. */
245 return tdep->regmap[regnum].name;
246}
247
248/* Return the type of a register. Create a new type, if necessary. */
249
250static struct type *
252{
253 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
254
255 /* Return signed integer for ARx and Ax registers. */
256 if ((regnum >= tdep->ar_base
257 && regnum < tdep->ar_base + tdep->num_aregs)
258 || (regnum >= tdep->a0_base
259 && regnum < tdep->a0_base + 16))
261
263 || regnum == tdep->a0_base + 1)
265
266 /* Return the stored type for all other registers. */
267 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
268 {
269 xtensa_register_t* reg = &tdep->regmap[regnum];
270
271 /* Set ctype for this register (only the first time). */
272
273 if (reg->ctype == 0)
274 {
275 struct ctype_cache *tp;
276 int size = reg->byte_size;
277
278 /* We always use the memory representation,
279 even if the register width is smaller. */
280 switch (size)
281 {
282 case 1:
284 break;
285
286 case 2:
288 break;
289
290 case 4:
292 break;
293
294 case 8:
296 break;
297
298 case 16:
300 break;
301
302 default:
303 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
304 if (tp->size == size)
305 break;
306
307 if (tp == NULL)
308 {
309 std::string name = string_printf ("int%d", size * 8);
310
311 tp = XNEW (struct ctype_cache);
312 tp->next = tdep->type_entries;
313 tdep->type_entries = tp;
314 tp->size = size;
315 type_allocator alloc (gdbarch);
316 tp->virtual_type
317 = init_integer_type (alloc, size * 8, 1, name.c_str ());
318 }
319
320 reg->ctype = tp->virtual_type;
321 }
322 }
323 return reg->ctype;
324 }
325
326 internal_error (_("invalid register number %d"), regnum);
327 return 0;
328}
329
330
331/* Return the 'local' register number for stubs, dwarf2, etc.
332 The debugging information enumerates registers starting from 0 for A0
333 to n for An. So, we only have to add the base number for A0. */
334
335static int
337{
338 int i;
339 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
340
341 if (regnum >= 0 && regnum < 16)
342 return tdep->a0_base + regnum;
343
344 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++)
345 if (regnum == tdep->regmap[i].target_number)
346 return i;
347
348 return -1;
349}
350
351
352/* Write the bits of a masked register to the various registers.
353 Only the masked areas of these registers are modified; the other
354 fields are untouched. The size of masked registers is always less
355 than or equal to 32 bits. */
356
357static void
359 xtensa_register_t *reg, const gdb_byte *buffer)
360{
361 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4];
362 const xtensa_mask_t *mask = reg->mask;
363
364 int shift = 0; /* Shift for next mask (mod 32). */
365 int start, size; /* Start bit and size of current mask. */
366
367 unsigned int *ptr = value;
368 unsigned int regval, m, mem = 0;
369
370 int bytesize = reg->byte_size;
371 int bitsize = bytesize * 8;
372 int i, r;
373
374 DEBUGTRACE ("xtensa_register_write_masked ()\n");
375
376 /* Copy the masked register to host byte-order. */
377 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG)
378 for (i = 0; i < bytesize; i++)
379 {
380 mem >>= 8;
381 mem |= (buffer[bytesize - i - 1] << 24);
382 if ((i & 3) == 3)
383 *ptr++ = mem;
384 }
385 else
386 for (i = 0; i < bytesize; i++)
387 {
388 mem >>= 8;
389 mem |= (buffer[i] << 24);
390 if ((i & 3) == 3)
391 *ptr++ = mem;
392 }
393
394 /* We might have to shift the final value:
395 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
396 bytesize & 3 == x -> shift (4-x) * 8. */
397
398 *ptr = mem >> (((0 - bytesize) & 3) * 8);
399 ptr = value;
400 mem = *ptr;
401
402 /* Write the bits to the masked areas of the other registers. */
403 for (i = 0; i < mask->count; i++)
404 {
405 start = mask->mask[i].bit_start;
406 size = mask->mask[i].bit_size;
407 regval = mem >> shift;
408
409 if ((shift += size) > bitsize)
410 error (_("size of all masks is larger than the register"));
411
412 if (shift >= 32)
413 {
414 mem = *(++ptr);
415 shift -= 32;
416 bitsize -= 32;
417
418 if (shift > 0)
419 regval |= mem << (size - shift);
420 }
421
422 /* Make sure we have a valid register. */
423 r = mask->mask[i].reg_num;
424 if (r >= 0 && size > 0)
425 {
426 /* Don't overwrite the unmasked areas. */
427 ULONGEST old_val;
429 m = 0xffffffff >> (32 - size) << start;
430 regval <<= start;
431 regval = (regval & m) | (old_val & ~m);
433 }
434 }
435}
436
437
438/* Read a tie state or mapped registers. Read the masked areas
439 of the registers and assemble them into a single value. */
440
441static enum register_status
443 xtensa_register_t *reg, gdb_byte *buffer)
444{
445 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4];
446 const xtensa_mask_t *mask = reg->mask;
447
448 int shift = 0;
449 int start, size;
450
451 unsigned int *ptr = value;
452 unsigned int regval, mem = 0;
453
454 int bytesize = reg->byte_size;
455 int bitsize = bytesize * 8;
456 int i;
457
458 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
459 reg->name == 0 ? "" : reg->name);
460
461 /* Assemble the register from the masked areas of other registers. */
462 for (i = 0; i < mask->count; i++)
463 {
464 int r = mask->mask[i].reg_num;
465 if (r >= 0)
466 {
467 enum register_status status;
468 ULONGEST val;
469
470 status = regcache->cooked_read (r, &val);
471 if (status != REG_VALID)
472 return status;
473 regval = (unsigned int) val;
474 }
475 else
476 regval = 0;
477
478 start = mask->mask[i].bit_start;
479 size = mask->mask[i].bit_size;
480
481 regval >>= start;
482
483 if (size < 32)
484 regval &= (0xffffffff >> (32 - size));
485
486 mem |= regval << shift;
487
488 if ((shift += size) > bitsize)
489 error (_("size of all masks is larger than the register"));
490
491 if (shift >= 32)
492 {
493 *ptr++ = mem;
494 bitsize -= 32;
495 shift -= 32;
496
497 if (shift == 0)
498 mem = 0;
499 else
500 mem = regval >> (size - shift);
501 }
502 }
503
504 if (shift > 0)
505 *ptr = mem;
506
507 /* Copy value to target byte order. */
508 ptr = value;
509 mem = *ptr;
510
511 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG)
512 for (i = 0; i < bytesize; i++)
513 {
514 if ((i & 3) == 0)
515 mem = *ptr++;
516 buffer[bytesize - i - 1] = mem & 0xff;
517 mem >>= 8;
518 }
519 else
520 for (i = 0; i < bytesize; i++)
521 {
522 if ((i & 3) == 0)
523 mem = *ptr++;
524 buffer[i] = mem & 0xff;
525 mem >>= 8;
526 }
527
528 return REG_VALID;
529}
530
531
532/* Read pseudo registers. */
533
534static enum register_status
537 int regnum,
538 gdb_byte *buffer)
539{
540 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
542 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
543
544 /* Read aliases a0..a15, if this is a Windowed ABI. */
546 && (regnum >= tdep->a0_base)
547 && (regnum <= tdep->a0_base + 15))
548 {
549 ULONGEST value;
550 enum register_status status;
551
553 &value);
554 if (status != REG_VALID)
555 return status;
557 }
558
559 /* We can always read non-pseudo registers. */
560 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
561 return regcache->raw_read (regnum, buffer);
562
563 /* We have to find out how to deal with privileged registers.
564 Let's treat them as pseudo-registers, but we cannot read/write them. */
565
566 else if (tdep->call_abi == CallAbiCall0Only
567 || regnum < tdep->a0_base)
568 {
569 buffer[0] = (gdb_byte)0;
570 buffer[1] = (gdb_byte)0;
571 buffer[2] = (gdb_byte)0;
572 buffer[3] = (gdb_byte)0;
573 return REG_VALID;
574 }
575 /* Pseudo registers. */
576 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
577 {
578 xtensa_register_t *reg = &tdep->regmap[regnum];
580 int flags = tdep->target_flags;
581
582 /* We cannot read Unknown or Unmapped registers. */
584 {
586 {
587 warning (_("cannot read register %s"),
589 return REG_VALID;
590 }
591 }
592
593 /* Some targets cannot read TIE register files. */
594 else if (type == xtRegisterTypeTieRegfile)
595 {
596 /* Use 'fetch' to get register? */
598 {
599 warning (_("cannot read register"));
600 return REG_VALID;
601 }
602
603 /* On some targets (esp. simulators), we can always read the reg. */
604 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
605 {
606 warning (_("cannot read register"));
607 return REG_VALID;
608 }
609 }
610
611 /* We can always read mapped registers. */
613 return xtensa_register_read_masked (regcache, reg, buffer);
614
615 /* Assume that we can read the register. */
616 return regcache->raw_read (regnum, buffer);
617 }
618 else
619 internal_error (_("invalid register number %d"), regnum);
620}
621
622
623/* Write pseudo registers. */
624
625static void
627 struct regcache *regcache,
628 int regnum,
629 const gdb_byte *buffer)
630{
631 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
633 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
634
635 /* Renumber register, if aliases a0..a15 on Windowed ABI. */
637 && (regnum >= tdep->a0_base)
638 && (regnum <= tdep->a0_base + 15))
639 {
640 ULONGEST value;
642 tdep->wb_regnum, &value);
644 }
645
646 /* We can always write 'core' registers.
647 Note: We might have converted Ax->ARy. */
648 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
649 regcache->raw_write (regnum, buffer);
650
651 /* We have to find out how to deal with privileged registers.
652 Let's treat them as pseudo-registers, but we cannot read/write them. */
653
654 else if (regnum < tdep->a0_base)
655 {
656 return;
657 }
658 /* Pseudo registers. */
659 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
660 {
661 xtensa_register_t *reg = &tdep->regmap[regnum];
663 int flags = tdep->target_flags;
664
665 /* On most targets, we cannot write registers
666 of type "Unknown" or "Unmapped". */
668 {
670 {
671 warning (_("cannot write register %s"),
673 return;
674 }
675 }
676
677 /* Some targets cannot read TIE register files. */
678 else if (type == xtRegisterTypeTieRegfile)
679 {
680 /* Use 'store' to get register? */
682 {
683 warning (_("cannot write register"));
684 return;
685 }
686
687 /* On some targets (esp. simulators), we can always write
688 the register. */
689 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
690 {
691 warning (_("cannot write register"));
692 return;
693 }
694 }
695
696 /* We can always write mapped registers. */
698 {
700 return;
701 }
702
703 /* Assume that we can write the register. */
704 regcache->raw_write (regnum, buffer);
705 }
706 else
707 internal_error (_("invalid register number %d"), regnum);
708}
709
714
715static void
717{
718 int i;
719
723
724 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
725 xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i).release (),
727}
728
729static void
731{
732 /* Xtensa-specific groups. */
736
737 for (int i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
739}
740
741static int
743{
744 int i;
745
746 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
747 if (group == xtensa_cp[i])
748 return i;
749
750 return -1;
751}
752
753#define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
754 | XTENSA_REGISTER_FLAGS_WRITABLE \
755 | XTENSA_REGISTER_FLAGS_VOLATILE)
756
757#define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
758 | XTENSA_REGISTER_FLAGS_WRITABLE)
759
760static int
762 int regnum,
763 const struct reggroup *group)
764{
765 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
766 xtensa_register_t* reg = &tdep->regmap[regnum];
769 int cp_number;
770
771 if (group == save_reggroup)
772 /* Every single register should be included into the list of registers
773 to be watched for changes while using -data-list-changed-registers. */
774 return 1;
775
776 /* First, skip registers that are not visible to this target
777 (unknown and unmapped registers when not using ISS). */
778
780 return 0;
781 if (group == all_reggroup)
782 return 1;
783 if (group == xtensa_ar_reggroup)
784 return rg & xtRegisterGroupAddrReg;
785 if (group == xtensa_user_reggroup)
786 return rg & xtRegisterGroupUser;
787 if (group == float_reggroup)
788 return rg & xtRegisterGroupFloat;
789 if (group == general_reggroup)
790 return rg & xtRegisterGroupGeneral;
791 if (group == system_reggroup)
792 return rg & xtRegisterGroupState;
793 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
794 return rg & xtRegisterGroupVectra;
795 if (group == restore_reggroup)
797 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
798 cp_number = xtensa_coprocessor_register_group (group);
799 if (cp_number >= 0)
800 return rg & (xtRegisterGroupCP0 << cp_number);
801 else
802 return 1;
803}
804
805
806/* Supply register REGNUM from the buffer specified by GREGS and LEN
807 in the general-purpose register set REGSET to register cache
808 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
809
810static void
812 struct regcache *rc,
813 int regnum,
814 const void *gregs,
815 size_t len)
816{
817 const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs;
818 struct gdbarch *gdbarch = rc->arch ();
819 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
820 int i;
821
822 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
823
824 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
825 rc->raw_supply (gdbarch_pc_regnum (gdbarch), (char *) &regs->pc);
826 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
827 rc->raw_supply (gdbarch_ps_regnum (gdbarch), (char *) &regs->ps);
828 if (regnum == tdep->wb_regnum || regnum == -1)
829 rc->raw_supply (tdep->wb_regnum,
830 (char *) &regs->windowbase);
831 if (regnum == tdep->ws_regnum || regnum == -1)
832 rc->raw_supply (tdep->ws_regnum,
833 (char *) &regs->windowstart);
834 if (regnum == tdep->lbeg_regnum || regnum == -1)
835 rc->raw_supply (tdep->lbeg_regnum,
836 (char *) &regs->lbeg);
837 if (regnum == tdep->lend_regnum || regnum == -1)
838 rc->raw_supply (tdep->lend_regnum,
839 (char *) &regs->lend);
840 if (regnum == tdep->lcount_regnum || regnum == -1)
841 rc->raw_supply (tdep->lcount_regnum,
842 (char *) &regs->lcount);
843 if (regnum == tdep->sar_regnum || regnum == -1)
844 rc->raw_supply (tdep->sar_regnum,
845 (char *) &regs->sar);
846 if (regnum >=tdep->ar_base
847 && regnum < tdep->ar_base
848 + tdep->num_aregs)
849 rc->raw_supply
850 (regnum, (char *) &regs->ar[regnum - tdep->ar_base]);
851 else if (regnum == -1)
852 {
853 for (i = 0; i < tdep->num_aregs; ++i)
854 rc->raw_supply (tdep->ar_base + i,
855 (char *) &regs->ar[i]);
856 }
857}
858
859
860/* Xtensa register set. */
861
862static struct regset
864{
865 NULL,
867};
868
869
870/* Iterate over supported core file register note sections. */
871
872static void
875 void *cb_data,
876 const struct regcache *regcache)
877{
878 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
879
880 cb (".reg", sizeof (xtensa_elf_gregset_t), sizeof (xtensa_elf_gregset_t),
881 &xtensa_gregset, NULL, cb_data);
882}
883
884
885/* Handling frames. */
886
887/* Number of registers to save in case of Windowed ABI. */
888#define XTENSA_NUM_SAVED_AREGS 12
889
890/* Frame cache part for Windowed ABI. */
892{
893 int wb; /* WINDOWBASE of the previous frame. */
894 int callsize; /* Call size of this frame. */
895 int ws; /* WINDOWSTART of the previous frame. It keeps track of
896 life windows only. If there is no bit set for the
897 window, that means it had been already spilled
898 because of window overflow. */
899
900 /* Addresses of spilled A-registers.
901 AREGS[i] == -1, if corresponding AR is alive. */
904
905/* Call0 ABI Definitions. */
906
907#define C0_MAXOPDS 3 /* Maximum number of operands for prologue
908 analysis. */
909#define C0_CLESV 12 /* Callee-saved registers are here and up. */
910#define C0_SP 1 /* Register used as SP. */
911#define C0_FP 15 /* Register used as FP. */
912#define C0_RA 0 /* Register used as return address. */
913#define C0_ARGS 2 /* Register used as first arg/retval. */
914#define C0_NARGS 6 /* Number of A-regs for args/retvals. */
915
916/* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
917 A-register where the current content of the reg came from (in terms
918 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
919 mean that the original content of the register was saved to the stack.
920 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
921 know where SP will end up until the entire prologue has been analyzed. */
923#define C0_CONST -1 /* fr_reg value if register contains a constant. */
924#define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
925#define C0_NOSTK -1 /* to_stk value if register has not been stored. */
926
927extern xtensa_isa xtensa_default_isa;
929typedef struct xtensa_c0reg
931 int fr_reg; /* original register from which register content
932 is derived, or C0_CONST, or C0_INEXP. */
933 int fr_ofs; /* constant offset from reg, or immediate value. */
934 int to_stk; /* offset from original SP to register (4-byte aligned),
935 or C0_NOSTK if register has not been saved. */
937
938/* Frame cache part for Call0 ABI. */
939typedef struct xtensa_call0_frame_cache
941 int c0_frmsz; /* Stack frame size. */
942 int c0_hasfp; /* Current frame uses frame pointer. */
943 int fp_regnum; /* A-register used as FP. */
944 int c0_fp; /* Actual value of frame pointer. */
945 int c0_fpalign; /* Dynamic adjustment for the stack
946 pointer. It's an AND mask. Zero,
947 if alignment was not adjusted. */
948 int c0_old_sp; /* In case of dynamic adjustment, it is
949 a register holding unaligned sp.
950 C0_INEXP, when undefined. */
951 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
952 stack offset. C0_NOSTK otherwise. */
954 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
957typedef struct xtensa_frame_cache
959 CORE_ADDR base; /* Stack pointer of this frame. */
960 CORE_ADDR pc; /* PC of this frame at the function entry point. */
961 CORE_ADDR ra; /* The raw return address of this frame. */
962 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
963 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
964 int call0; /* It's a call0 framework (else windowed). */
965 union
967 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
968 xtensa_call0_frame_cache_t c0; /* call0 == true. */
969 };
971
972
973static struct xtensa_frame_cache *
974xtensa_alloc_frame_cache (int windowed)
975{
977 int i;
978
979 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
980
982
983 cache->base = 0;
984 cache->pc = 0;
985 cache->ra = 0;
986 cache->ps = 0;
987 cache->prev_sp = 0;
988 cache->call0 = !windowed;
989 if (cache->call0)
990 {
991 cache->c0.c0_frmsz = -1;
992 cache->c0.c0_hasfp = 0;
993 cache->c0.fp_regnum = -1;
994 cache->c0.c0_fp = -1;
995 cache->c0.c0_fpalign = 0;
996 cache->c0.c0_old_sp = C0_INEXP;
997 cache->c0.c0_sp_ofs = C0_NOSTK;
998
999 for (i = 0; i < C0_NREGS; i++)
1000 {
1001 cache->c0.c0_rt[i].fr_reg = i;
1002 cache->c0.c0_rt[i].fr_ofs = 0;
1003 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1004 }
1005 }
1006 else
1007 {
1008 cache->wd.wb = 0;
1009 cache->wd.ws = 0;
1010 cache->wd.callsize = -1;
1011
1012 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1013 cache->wd.aregs[i] = -1;
1014 }
1015 return cache;
1016}
1017
1018
1019static CORE_ADDR
1020xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1021{
1022 return address & ~15;
1023}
1024
1025
1026static CORE_ADDR
1027xtensa_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
1028{
1029 gdb_byte buf[8];
1030 CORE_ADDR pc;
1031
1032 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1033 host_address_to_string (next_frame.get ()));
1034
1035 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1036 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1037
1038 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1039
1040 return pc;
1041}
1042
1043
1044static struct frame_id
1045xtensa_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame)
1046{
1047 CORE_ADDR pc, fp;
1048 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1049
1050 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1051
1052 pc = get_frame_pc (this_frame);
1054 (this_frame, tdep->a0_base + 1);
1055
1056 /* Make dummy frame ID unique by adding a constant. */
1057 return frame_id_build (fp + SP_ALIGNMENT, pc);
1058}
1059
1060/* Returns true, if instruction to execute next is unique to Xtensa Window
1061 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1062
1063static int
1064xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1065{
1066 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1067 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1068 unsigned int code;
1069
1070 if (byte_order == BFD_ENDIAN_BIG)
1071 {
1072 /* Check, if this is L32E or S32E. */
1073 code = insn & 0xf000ff00;
1074 if ((code == 0x00009000) || (code == 0x00009400))
1075 return 1;
1076 /* Check, if this is RFWU or RFWO. */
1077 code = insn & 0xffffff00;
1078 return ((code == 0x00430000) || (code == 0x00530000));
1079 }
1080 else
1081 {
1082 /* Check, if this is L32E or S32E. */
1083 code = insn & 0x00ff000f;
1084 if ((code == 0x090000) || (code == 0x490000))
1085 return 1;
1086 /* Check, if this is RFWU or RFWO. */
1087 code = insn & 0x00ffffff;
1088 return ((code == 0x00003400) || (code == 0x00003500));
1089 }
1090}
1091
1092/* Returns the best guess about which register is a frame pointer
1093 for the function containing CURRENT_PC. */
1095#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1096#define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1097
1098static unsigned int
1099xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1100{
1101#define RETURN_FP goto done
1102
1103 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1104 unsigned int fp_regnum = tdep->a0_base + 1;
1105 CORE_ADDR start_addr;
1106 xtensa_isa isa;
1107 xtensa_insnbuf ins, slot;
1108 gdb_byte ibuf[XTENSA_ISA_BSZ];
1109 CORE_ADDR ia, bt, ba;
1110 xtensa_format ifmt;
1111 int ilen, islots, is;
1112 xtensa_opcode opc;
1113 const char *opcname;
1114
1115 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1116 if (start_addr == 0)
1117 return fp_regnum;
1118
1119 isa = xtensa_default_isa;
1120 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1121 ins = xtensa_insnbuf_alloc (isa);
1122 slot = xtensa_insnbuf_alloc (isa);
1123 ba = 0;
1124
1125 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1126 {
1127 if (ia + xtensa_isa_maxlength (isa) > bt)
1128 {
1129 ba = ia;
1130 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1131 ? ba + XTENSA_ISA_BSZ : current_pc;
1132 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1133 RETURN_FP;
1134 }
1135
1136 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1137 ifmt = xtensa_format_decode (isa, ins);
1138 if (ifmt == XTENSA_UNDEFINED)
1139 RETURN_FP;
1140 ilen = xtensa_format_length (isa, ifmt);
1141 if (ilen == XTENSA_UNDEFINED)
1142 RETURN_FP;
1143 islots = xtensa_format_num_slots (isa, ifmt);
1144 if (islots == XTENSA_UNDEFINED)
1145 RETURN_FP;
1146
1147 for (is = 0; is < islots; ++is)
1148 {
1149 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1150 RETURN_FP;
1151
1152 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1153 if (opc == XTENSA_UNDEFINED)
1154 RETURN_FP;
1155
1156 opcname = xtensa_opcode_name (isa, opc);
1157
1158 if (strcasecmp (opcname, "mov.n") == 0
1159 || strcasecmp (opcname, "or") == 0)
1160 {
1161 unsigned int register_operand;
1162
1163 /* Possible candidate for setting frame pointer
1164 from A1. This is what we are looking for. */
1165
1166 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1167 is, slot, &register_operand) != 0)
1168 RETURN_FP;
1169 if (xtensa_operand_decode (isa, opc, 1, &register_operand) != 0)
1170 RETURN_FP;
1171 if (register_operand == 1) /* Mov{.n} FP A1. */
1172 {
1173 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1174 &register_operand) != 0)
1175 RETURN_FP;
1176 if (xtensa_operand_decode (isa, opc, 0,
1177 &register_operand) != 0)
1178 RETURN_FP;
1179
1180 fp_regnum
1181 = tdep->a0_base + register_operand;
1182 RETURN_FP;
1183 }
1184 }
1185
1186 if (
1187 /* We have problems decoding the memory. */
1188 opcname == NULL
1189 || strcasecmp (opcname, "ill") == 0
1190 || strcasecmp (opcname, "ill.n") == 0
1191 /* Hit planted breakpoint. */
1192 || strcasecmp (opcname, "break") == 0
1193 || strcasecmp (opcname, "break.n") == 0
1194 /* Flow control instructions finish prologue. */
1195 || xtensa_opcode_is_branch (isa, opc) > 0
1196 || xtensa_opcode_is_jump (isa, opc) > 0
1197 || xtensa_opcode_is_loop (isa, opc) > 0
1198 || xtensa_opcode_is_call (isa, opc) > 0
1199 || strcasecmp (opcname, "simcall") == 0
1200 || strcasecmp (opcname, "syscall") == 0)
1201 /* Can not continue analysis. */
1202 RETURN_FP;
1203 }
1204 }
1205done:
1206 xtensa_insnbuf_free(isa, slot);
1207 xtensa_insnbuf_free(isa, ins);
1208 return fp_regnum;
1209}
1210
1211/* The key values to identify the frame using "cache" are
1212
1213 cache->base = SP (or best guess about FP) of this frame;
1214 cache->pc = entry-PC (entry point of the frame function);
1215 cache->prev_sp = SP of the previous frame. */
1216
1217static void
1219 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1220
1221static void
1223 xtensa_frame_cache_t *cache,
1224 CORE_ADDR pc);
1225
1226static struct xtensa_frame_cache *
1227xtensa_frame_cache (frame_info_ptr this_frame, void **this_cache)
1228{
1229 xtensa_frame_cache_t *cache;
1230 CORE_ADDR ra, wb, ws, pc, sp, ps;
1231 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1232 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1233 unsigned int fp_regnum;
1234 int windowed, ps_regnum;
1235
1236 if (*this_cache)
1237 return (struct xtensa_frame_cache *) *this_cache;
1238
1240 ps_regnum = gdbarch_ps_regnum (gdbarch);
1241 ps = (ps_regnum >= 0
1242 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1243
1244 windowed = windowing_enabled (gdbarch, ps);
1245
1246 /* Get pristine xtensa-frame. */
1247 cache = xtensa_alloc_frame_cache (windowed);
1248 *this_cache = cache;
1249
1250 if (windowed)
1251 {
1252 LONGEST op1;
1253 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1254
1255 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1256 wb = get_frame_register_unsigned (this_frame,
1257 tdep->wb_regnum);
1258 ws = get_frame_register_unsigned (this_frame,
1259 tdep->ws_regnum);
1260
1261 if (safe_read_memory_integer (pc, 1, byte_order, &op1)
1262 && XTENSA_IS_ENTRY (gdbarch, op1))
1263 {
1264 int callinc = CALLINC (ps);
1266 (this_frame, tdep->a0_base + callinc * 4);
1267
1268 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1269 cache->wd.callsize = 0;
1270 cache->wd.wb = wb;
1271 cache->wd.ws = ws;
1273 (this_frame, tdep->a0_base + 1);
1274
1275 /* This only can be the outermost frame since we are
1276 just about to execute ENTRY. SP hasn't been set yet.
1277 We can assume any frame size, because it does not
1278 matter, and, let's fake frame base in cache. */
1279 cache->base = cache->prev_sp - 16;
1280
1281 cache->pc = pc;
1282 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1283 cache->ps = (ps & ~PS_CALLINC_MASK)
1284 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1285
1286 return cache;
1287 }
1288 else
1289 {
1291 ra = get_frame_register_unsigned (this_frame,
1292 tdep->a0_base);
1293 cache->wd.callsize = WINSIZE (ra);
1294 cache->wd.wb = (wb - cache->wd.callsize / 4)
1295 & (tdep->num_aregs / 4 - 1);
1296 cache->wd.ws = ws & ~(1 << wb);
1297
1298 cache->pc = get_frame_func (this_frame);
1299 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1300 cache->ps = (ps & ~PS_CALLINC_MASK)
1301 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1302 }
1303
1304 if (cache->wd.ws == 0)
1305 {
1306 int i;
1307
1308 /* Set A0...A3. */
1310 (this_frame, tdep->a0_base + 1) - 16;
1311
1312 for (i = 0; i < 4; i++, sp += 4)
1313 {
1314 cache->wd.aregs[i] = sp;
1315 }
1316
1317 if (cache->wd.callsize > 4)
1318 {
1319 /* Set A4...A7/A11. */
1320 /* Get the SP of the frame previous to the previous one.
1321 To achieve this, we have to dereference SP twice. */
1322 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1323 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1324 sp -= cache->wd.callsize * 4;
1325
1326 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1327 {
1328 cache->wd.aregs[i] = sp;
1329 }
1330 }
1331 }
1332
1333 if ((cache->prev_sp == 0) && ( ra != 0 ))
1334 /* If RA is equal to 0 this frame is an outermost frame. Leave
1335 cache->prev_sp unchanged marking the boundary of the frame stack. */
1336 {
1337 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1338 {
1339 /* Register window overflow already happened.
1340 We can read caller's SP from the proper spill location. */
1342 (this_frame, tdep->a0_base + 1);
1343 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1344 }
1345 else
1346 {
1347 /* Read caller's frame SP directly from the previous window. */
1348 int regnum = arreg_number
1349 (gdbarch, tdep->a0_base + 1,
1350 cache->wd.wb);
1351
1353 }
1354 }
1355 }
1357 {
1358 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1359
1360 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1361 /* Everything was set already, including cache->base. */
1362 return cache;
1363 }
1364 else /* Call0 framework. */
1365 {
1366 call0_frame_cache (this_frame, cache, pc);
1367 fp_regnum = cache->c0.fp_regnum;
1368 }
1369
1370 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1371
1372 return cache;
1373}
1375static int xtensa_session_once_reported = 1;
1376
1377/* Report a problem with prologue analysis while doing backtracing.
1378 But, do it only once to avoid annoying repeated messages. */
1379
1380static void
1381warning_once (void)
1382{
1384 warning (_("\
1385\nUnrecognised function prologue. Stack trace cannot be resolved. \
1386This message will not be repeated in this session.\n"));
1387
1389}
1390
1391
1392static void
1394 void **this_cache,
1395 struct frame_id *this_id)
1396{
1397 struct xtensa_frame_cache *cache =
1398 xtensa_frame_cache (this_frame, this_cache);
1399
1400 if (cache->prev_sp == 0)
1401 return;
1402
1403 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1404}
1405
1406static struct value *
1408 void **this_cache,
1409 int regnum)
1410{
1411 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1412 struct xtensa_frame_cache *cache;
1413 ULONGEST saved_reg = 0;
1414 int done = 1;
1415 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1416
1417 if (*this_cache == NULL)
1418 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1419 cache = (struct xtensa_frame_cache *) *this_cache;
1420
1422 saved_reg = cache->ra;
1423 else if (regnum == tdep->a0_base + 1)
1424 saved_reg = cache->prev_sp;
1425 else if (!cache->call0)
1426 {
1427 if (regnum == tdep->ws_regnum)
1428 saved_reg = cache->wd.ws;
1429 else if (regnum == tdep->wb_regnum)
1430 saved_reg = cache->wd.wb;
1431 else if (regnum == gdbarch_ps_regnum (gdbarch))
1432 saved_reg = cache->ps;
1433 else
1434 done = 0;
1435 }
1436 else
1437 done = 0;
1438
1439 if (done)
1440 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1441
1442 if (!cache->call0) /* Windowed ABI. */
1443 {
1444 /* Convert A-register numbers to AR-register numbers,
1445 if we deal with A-register. */
1446 if (regnum >= tdep->a0_base
1447 && regnum <= tdep->a0_base + 15)
1448 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1449
1450 /* Check, if we deal with AR-register saved on stack. */
1451 if (regnum >= tdep->ar_base
1452 && regnum <= (tdep->ar_base
1453 + tdep->num_aregs))
1454 {
1455 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1456
1457 if (areg >= 0
1458 && areg < XTENSA_NUM_SAVED_AREGS
1459 && cache->wd.aregs[areg] != -1)
1460 return frame_unwind_got_memory (this_frame, regnum,
1461 cache->wd.aregs[areg]);
1462 }
1463 }
1464 else /* Call0 ABI. */
1465 {
1466 int reg = (regnum >= tdep->ar_base
1467 && regnum <= (tdep->ar_base
1468 + C0_NREGS))
1469 ? regnum - tdep->ar_base : regnum;
1470
1471 if (reg < C0_NREGS)
1472 {
1473 CORE_ADDR spe;
1474 int stkofs;
1475
1476 /* If register was saved in the prologue, retrieve it. */
1477 stkofs = cache->c0.c0_rt[reg].to_stk;
1478 if (stkofs != C0_NOSTK)
1479 {
1480 /* Determine SP on entry based on FP. */
1481 spe = cache->c0.c0_fp
1482 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1483
1484 return frame_unwind_got_memory (this_frame, regnum,
1485 spe + stkofs);
1486 }
1487 }
1488 }
1489
1490 /* All other registers have been either saved to
1491 the stack or are still alive in the processor. */
1492
1493 return frame_unwind_got_register (this_frame, regnum, regnum);
1494}
1495
1496
1497static const struct frame_unwind
1499{
1500 "xtensa prologue",
1505 NULL,
1507};
1508
1509static CORE_ADDR
1510xtensa_frame_base_address (frame_info_ptr this_frame, void **this_cache)
1511{
1512 struct xtensa_frame_cache *cache =
1513 xtensa_frame_cache (this_frame, this_cache);
1514
1515 return cache->base;
1516}
1517
1525};
1526
1527
1528static void
1530 struct regcache *regcache,
1531 void *dst)
1532{
1533 struct gdbarch *gdbarch = regcache->arch ();
1534 bfd_byte *valbuf = (bfd_byte *) dst;
1535 int len = type->length ();
1536 ULONGEST pc, wb;
1537 int callsize, areg;
1538 int offset = 0;
1539
1540 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1541
1542 gdb_assert(len > 0);
1543
1544 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1545 if (tdep->call_abi != CallAbiCall0Only)
1546 {
1547 /* First, we have to find the caller window in the register file. */
1549 callsize = extract_call_winsize (gdbarch, pc);
1550
1551 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1552 if (len > (callsize > 8 ? 8 : 16))
1553 internal_error (_("cannot extract return value of %d bytes long"),
1554 len);
1555
1556 /* Get the register offset of the return
1557 register (A2) in the caller window. */
1559 (regcache, tdep->wb_regnum, &wb);
1560 areg = arreg_number (gdbarch,
1561 tdep->a0_base + 2 + callsize, wb);
1562 }
1563 else
1564 {
1565 /* No windowing hardware - Call0 ABI. */
1566 areg = tdep->a0_base + C0_ARGS;
1567 }
1568
1569 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1570
1571 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1572 offset = 4 - len;
1573
1574 for (; len > 0; len -= 4, areg++, valbuf += 4)
1575 {
1576 if (len < 4)
1577 regcache->raw_read_part (areg, offset, len, valbuf);
1578 else
1579 regcache->raw_read (areg, valbuf);
1580 }
1581}
1582
1583
1584static void
1586 struct regcache *regcache,
1587 const void *dst)
1588{
1589 struct gdbarch *gdbarch = regcache->arch ();
1590 const bfd_byte *valbuf = (const bfd_byte *) dst;
1591 unsigned int areg;
1592 ULONGEST pc, wb;
1593 int callsize;
1594 int len = type->length ();
1595 int offset = 0;
1596
1597 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1598
1599 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1600 if (tdep->call_abi != CallAbiCall0Only)
1601 {
1603 (regcache, tdep->wb_regnum, &wb);
1605 callsize = extract_call_winsize (gdbarch, pc);
1606
1607 if (len > (callsize > 8 ? 8 : 16))
1608 internal_error (_("unimplemented for this length: %s"),
1609 pulongest (type->length ()));
1610 areg = arreg_number (gdbarch,
1611 tdep->a0_base + 2 + callsize, wb);
1612
1613 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1614 callsize, (int) wb);
1615 }
1616 else
1617 {
1618 areg = tdep->a0_base + C0_ARGS;
1619 }
1620
1621 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1622 offset = 4 - len;
1623
1624 for (; len > 0; len -= 4, areg++, valbuf += 4)
1625 {
1626 if (len < 4)
1627 regcache->raw_write_part (areg, offset, len, valbuf);
1628 else
1629 regcache->raw_write (areg, valbuf);
1630 }
1631}
1632
1633
1636 struct value *function,
1637 struct type *valtype,
1638 struct regcache *regcache,
1639 gdb_byte *readbuf,
1640 const gdb_byte *writebuf)
1641{
1642 /* Structures up to 16 bytes are returned in registers. */
1643
1644 int struct_return = ((valtype->code () == TYPE_CODE_STRUCT
1645 || valtype->code () == TYPE_CODE_UNION
1646 || valtype->code () == TYPE_CODE_ARRAY)
1647 && valtype->length () > 16);
1648
1649 if (struct_return)
1651
1652 DEBUGTRACE ("xtensa_return_value(...)\n");
1653
1654 if (writebuf != NULL)
1655 {
1656 xtensa_store_return_value (valtype, regcache, writebuf);
1657 }
1658
1659 if (readbuf != NULL)
1660 {
1661 gdb_assert (!struct_return);
1662 xtensa_extract_return_value (valtype, regcache, readbuf);
1663 }
1665}
1666
1667
1668/* DUMMY FRAME */
1669
1670static CORE_ADDR
1672 struct value *function,
1673 struct regcache *regcache,
1674 CORE_ADDR bp_addr,
1675 int nargs,
1676 struct value **args,
1677 CORE_ADDR sp,
1678 function_call_return_method return_method,
1679 CORE_ADDR struct_addr)
1680{
1681 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1682 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1683 int size, onstack_size;
1684 gdb_byte *buf = (gdb_byte *) alloca (16);
1685 CORE_ADDR ra, ps;
1686 struct argument_info
1687 {
1688 const bfd_byte *contents;
1689 int length;
1690 int onstack; /* onstack == 0 => in reg */
1691 int align; /* alignment */
1692 union
1693 {
1694 int offset; /* stack offset if on stack. */
1695 int regno; /* regno if in register. */
1696 } u;
1697 };
1698
1699 struct argument_info *arg_info =
1700 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1701
1702 CORE_ADDR osp = sp;
1703
1704 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1705
1706 if (xtensa_debug_level > 3)
1707 {
1708 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1709 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1710 "struct_addr=0x%x\n",
1711 (int) sp, (int) return_method, (int) struct_addr);
1712
1713 for (int i = 0; i < nargs; i++)
1714 {
1715 struct value *arg = args[i];
1716 struct type *arg_type = check_typedef (arg->type ());
1717 gdb_printf (gdb_stdlog, "%2d: %s %3s ", i,
1718 host_address_to_string (arg),
1719 pulongest (arg_type->length ()));
1720 switch (arg_type->code ())
1721 {
1722 case TYPE_CODE_INT:
1723 gdb_printf (gdb_stdlog, "int");
1724 break;
1725 case TYPE_CODE_STRUCT:
1726 gdb_printf (gdb_stdlog, "struct");
1727 break;
1728 default:
1729 gdb_printf (gdb_stdlog, "%3d", arg_type->code ());
1730 break;
1731 }
1732 gdb_printf (gdb_stdlog, " %s\n",
1733 host_address_to_string (arg->contents ().data ()));
1734 }
1735 }
1736
1737 /* First loop: collect information.
1738 Cast into type_long. (This shouldn't happen often for C because
1739 GDB already does this earlier.) It's possible that GDB could
1740 do it all the time but it's harmless to leave this code here. */
1741
1742 size = 0;
1743 onstack_size = 0;
1744
1745 if (return_method == return_method_struct)
1747
1748 for (int i = 0; i < nargs; i++)
1749 {
1750 struct argument_info *info = &arg_info[i];
1751 struct value *arg = args[i];
1752 struct type *arg_type = check_typedef (arg->type ());
1753
1754 switch (arg_type->code ())
1755 {
1756 case TYPE_CODE_INT:
1757 case TYPE_CODE_BOOL:
1758 case TYPE_CODE_CHAR:
1759 case TYPE_CODE_RANGE:
1760 case TYPE_CODE_ENUM:
1761
1762 /* Cast argument to long if necessary as the mask does it too. */
1763 if (arg_type->length ()
1764 < builtin_type (gdbarch)->builtin_long->length ())
1765 {
1766 arg_type = builtin_type (gdbarch)->builtin_long;
1767 arg = value_cast (arg_type, arg);
1768 }
1769 /* Aligment is equal to the type length for the basic types. */
1770 info->align = arg_type->length ();
1771 break;
1772
1773 case TYPE_CODE_FLT:
1774
1775 /* Align doubles correctly. */
1776 if (arg_type->length ()
1777 == builtin_type (gdbarch)->builtin_double->length ())
1778 info->align = builtin_type (gdbarch)->builtin_double->length ();
1779 else
1780 info->align = builtin_type (gdbarch)->builtin_long->length ();
1781 break;
1782
1783 case TYPE_CODE_STRUCT:
1784 default:
1785 info->align = builtin_type (gdbarch)->builtin_long->length ();
1786 break;
1787 }
1788 info->length = arg_type->length ();
1789 info->contents = arg->contents ().data ();
1790
1791 /* Align size and onstack_size. */
1792 size = (size + info->align - 1) & ~(info->align - 1);
1793 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1794
1795 if (size + info->length > REGISTER_SIZE * ARG_NOF (tdep))
1796 {
1797 info->onstack = 1;
1798 info->u.offset = onstack_size;
1799 onstack_size += info->length;
1800 }
1801 else
1802 {
1803 info->onstack = 0;
1804 info->u.regno = ARG_1ST (tdep) + size / REGISTER_SIZE;
1805 }
1806 size += info->length;
1807 }
1808
1809 /* Adjust the stack pointer and align it. */
1810 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1811
1812 /* Simulate MOVSP, if Windowed ABI. */
1813 if ((tdep->call_abi != CallAbiCall0Only)
1814 && (sp != osp))
1815 {
1816 read_memory (osp - 16, buf, 16);
1817 write_memory (sp - 16, buf, 16);
1818 }
1819
1820 /* Second Loop: Load arguments. */
1821
1822 if (return_method == return_method_struct)
1823 {
1824 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1825 regcache->cooked_write (ARG_1ST (tdep), buf);
1826 }
1827
1828 for (int i = 0; i < nargs; i++)
1829 {
1830 struct argument_info *info = &arg_info[i];
1831
1832 if (info->onstack)
1833 {
1834 int n = info->length;
1835 CORE_ADDR offset = sp + info->u.offset;
1836
1837 /* Odd-sized structs are aligned to the lower side of a memory
1838 word in big-endian mode and require a shift. This only
1839 applies for structures smaller than one word. */
1840
1841 if (n < REGISTER_SIZE
1842 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1843 offset += (REGISTER_SIZE - n);
1844
1845 write_memory (offset, info->contents, info->length);
1846
1847 }
1848 else
1849 {
1850 int n = info->length;
1851 const bfd_byte *cp = info->contents;
1852 int r = info->u.regno;
1853
1854 /* Odd-sized structs are aligned to the lower side of registers in
1855 big-endian mode and require a shift. The odd-sized leftover will
1856 be at the end. Note that this is only true for structures smaller
1857 than REGISTER_SIZE; for larger odd-sized structures the excess
1858 will be left-aligned in the register on both endiannesses. */
1859
1860 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1861 {
1862 ULONGEST v;
1863 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1864 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1865
1866 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1867 regcache->cooked_write (r, buf);
1868
1869 cp += REGISTER_SIZE;
1870 n -= REGISTER_SIZE;
1871 r++;
1872 }
1873 else
1874 while (n > 0)
1875 {
1876 regcache->cooked_write (r, cp);
1877
1878 cp += REGISTER_SIZE;
1879 n -= REGISTER_SIZE;
1880 r++;
1881 }
1882 }
1883 }
1884
1885 /* Set the return address of dummy frame to the dummy address.
1886 The return address for the current function (in A0) is
1887 saved in the dummy frame, so we can safely overwrite A0 here. */
1888
1889 if (tdep->call_abi != CallAbiCall0Only)
1890 {
1891 ULONGEST val;
1892
1893 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1895 ps = (unsigned long) val & ~0x00030000;
1897 (regcache, tdep->a0_base + 4, ra);
1900 ps | 0x00010000);
1901
1902 /* All the registers have been saved. After executing
1903 dummy call, they all will be restored. So it's safe
1904 to modify WINDOWSTART register to make it look like there
1905 is only one register window corresponding to WINDOWEBASE. */
1906
1907 regcache->raw_read (tdep->wb_regnum, buf);
1909 (regcache, tdep->ws_regnum,
1910 1 << extract_unsigned_integer (buf, 4, byte_order));
1911 }
1912 else
1913 {
1914 /* Simulate CALL0: write RA into A0 register. */
1916 (regcache, tdep->a0_base, bp_addr);
1917 }
1918
1919 /* Set new stack pointer and return it. */
1921 tdep->a0_base + 1, sp);
1922 /* Make dummy frame ID unique by adding a constant. */
1923 return sp + SP_ALIGNMENT;
1924}
1925
1926/* Implement the breakpoint_kind_from_pc gdbarch method. */
1927
1928static int
1929xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1930{
1931 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1932
1934 return 2;
1935 else
1936 return 4;
1937}
1938
1939/* Return a breakpoint for the current location of PC. We always use
1940 the density version if we have density instructions (regardless of the
1941 current instruction at PC), and use regular instructions otherwise. */
1943#define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1944#define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1945#define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1946#define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1947
1948/* Implement the sw_breakpoint_from_kind gdbarch method. */
1949
1950static const gdb_byte *
1951xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1952{
1953 *size = kind;
1954
1955 if (kind == 4)
1956 {
1957 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1958 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1959
1960 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1961 return big_breakpoint;
1962 else
1963 return little_breakpoint;
1964 }
1965 else
1966 {
1967 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1968 static unsigned char density_little_breakpoint[]
1970
1971 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1972 return density_big_breakpoint;
1973 else
1974 return density_little_breakpoint;
1975 }
1976}
1977
1978/* Call0 ABI support routines. */
1979
1980/* Return true, if PC points to "ret" or "ret.n". */
1981
1982static int
1983call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
1984{
1985#define RETURN_RET goto done
1986 xtensa_isa isa;
1987 xtensa_insnbuf ins, slot;
1988 gdb_byte ibuf[XTENSA_ISA_BSZ];
1989 CORE_ADDR ia, bt, ba;
1990 xtensa_format ifmt;
1991 int ilen, islots, is;
1992 xtensa_opcode opc;
1993 const char *opcname;
1994 int found_ret = 0;
1995
1996 isa = xtensa_default_isa;
1997 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1998 ins = xtensa_insnbuf_alloc (isa);
1999 slot = xtensa_insnbuf_alloc (isa);
2000 ba = 0;
2001
2002 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2003 {
2004 if (ia + xtensa_isa_maxlength (isa) > bt)
2005 {
2006 ba = ia;
2007 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2008 ? ba + XTENSA_ISA_BSZ : finish_pc;
2009 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2010 RETURN_RET;
2011 }
2012
2013 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2014 ifmt = xtensa_format_decode (isa, ins);
2015 if (ifmt == XTENSA_UNDEFINED)
2016 RETURN_RET;
2017 ilen = xtensa_format_length (isa, ifmt);
2018 if (ilen == XTENSA_UNDEFINED)
2019 RETURN_RET;
2020 islots = xtensa_format_num_slots (isa, ifmt);
2021 if (islots == XTENSA_UNDEFINED)
2022 RETURN_RET;
2023
2024 for (is = 0; is < islots; ++is)
2025 {
2026 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2027 RETURN_RET;
2028
2029 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2030 if (opc == XTENSA_UNDEFINED)
2031 RETURN_RET;
2032
2033 opcname = xtensa_opcode_name (isa, opc);
2034
2035 if ((strcasecmp (opcname, "ret.n") == 0)
2036 || (strcasecmp (opcname, "ret") == 0))
2037 {
2038 found_ret = 1;
2039 RETURN_RET;
2040 }
2041 }
2042 }
2043 done:
2044 xtensa_insnbuf_free(isa, slot);
2045 xtensa_insnbuf_free(isa, ins);
2046 return found_ret;
2047}
2048
2049/* Call0 opcode class. Opcodes are preclassified according to what they
2050 mean for Call0 prologue analysis, and their number of significant operands.
2051 The purpose of this is to simplify prologue analysis by separating
2052 instruction decoding (libisa) from the semantics of prologue analysis. */
2056 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2057 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2058 c0opc_flow, /* Flow control insn. */
2059 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2060 c0opc_break, /* Debugger software breakpoints. */
2061 c0opc_add, /* Adding two registers. */
2062 c0opc_addi, /* Adding a register and an immediate. */
2063 c0opc_and, /* Bitwise "and"-ing two registers. */
2064 c0opc_sub, /* Subtracting a register from a register. */
2065 c0opc_mov, /* Moving a register to a register. */
2066 c0opc_movi, /* Moving an immediate to a register. */
2067 c0opc_l32r, /* Loading a literal. */
2068 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2069 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2070 c0opc_l32e, /* L32E instruction. */
2071 c0opc_s32e, /* S32E instruction. */
2072 c0opc_rfwo, /* RFWO instruction. */
2073 c0opc_rfwu, /* RFWU instruction. */
2074 c0opc_NrOf /* Number of opcode classifications. */
2075};
2076
2077/* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2078
2079static int
2080rwx_special_register (const char *opcname)
2081{
2082 char ch = *opcname++;
2083
2084 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2085 return 0;
2086 if (*opcname++ != 's')
2087 return 0;
2088 if (*opcname++ != 'r')
2089 return 0;
2090 if (*opcname++ != '.')
2091 return 0;
2092
2093 return 1;
2094}
2095
2096/* Classify an opcode based on what it means for Call0 prologue analysis. */
2097
2099call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2100{
2101 const char *opcname;
2103
2104 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2105
2106 /* Get opcode name and handle special classifications. */
2107
2108 opcname = xtensa_opcode_name (isa, opc);
2109
2110 if (opcname == NULL
2111 || strcasecmp (opcname, "ill") == 0
2112 || strcasecmp (opcname, "ill.n") == 0)
2113 opclass = c0opc_illegal;
2114 else if (strcasecmp (opcname, "break") == 0
2115 || strcasecmp (opcname, "break.n") == 0)
2116 opclass = c0opc_break;
2117 else if (strcasecmp (opcname, "entry") == 0)
2118 opclass = c0opc_entry;
2119 else if (strcasecmp (opcname, "rfwo") == 0)
2120 opclass = c0opc_rfwo;
2121 else if (strcasecmp (opcname, "rfwu") == 0)
2122 opclass = c0opc_rfwu;
2123 else if (xtensa_opcode_is_branch (isa, opc) > 0
2124 || xtensa_opcode_is_jump (isa, opc) > 0
2125 || xtensa_opcode_is_loop (isa, opc) > 0
2126 || xtensa_opcode_is_call (isa, opc) > 0
2127 || strcasecmp (opcname, "simcall") == 0
2128 || strcasecmp (opcname, "syscall") == 0)
2129 opclass = c0opc_flow;
2130
2131 /* Also, classify specific opcodes that need to be tracked. */
2132 else if (strcasecmp (opcname, "add") == 0
2133 || strcasecmp (opcname, "add.n") == 0)
2134 opclass = c0opc_add;
2135 else if (strcasecmp (opcname, "and") == 0)
2136 opclass = c0opc_and;
2137 else if (strcasecmp (opcname, "addi") == 0
2138 || strcasecmp (opcname, "addi.n") == 0
2139 || strcasecmp (opcname, "addmi") == 0)
2140 opclass = c0opc_addi;
2141 else if (strcasecmp (opcname, "sub") == 0)
2142 opclass = c0opc_sub;
2143 else if (strcasecmp (opcname, "mov.n") == 0
2144 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2145 opclass = c0opc_mov;
2146 else if (strcasecmp (opcname, "movi") == 0
2147 || strcasecmp (opcname, "movi.n") == 0)
2148 opclass = c0opc_movi;
2149 else if (strcasecmp (opcname, "l32r") == 0)
2150 opclass = c0opc_l32r;
2151 else if (strcasecmp (opcname, "s32i") == 0
2152 || strcasecmp (opcname, "s32i.n") == 0)
2153 opclass = c0opc_s32i;
2154 else if (strcasecmp (opcname, "l32e") == 0)
2155 opclass = c0opc_l32e;
2156 else if (strcasecmp (opcname, "s32e") == 0)
2157 opclass = c0opc_s32e;
2158 else if (rwx_special_register (opcname))
2159 opclass = c0opc_rwxsr;
2160
2161 return opclass;
2162}
2163
2164/* Tracks register movement/mutation for a given operation, which may
2165 be within a bundle. Updates the destination register tracking info
2166 accordingly. The pc is needed only for pc-relative load instructions
2167 (eg. l32r). The SP register number is needed to identify stores to
2168 the stack frame. Returns 0, if analysis was successful, non-zero
2169 otherwise. */
2170
2171static int
2173 xtensa_insn_kind opclass, int nods, unsigned odv[],
2174 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2175{
2176 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2177 unsigned litbase, litaddr, litval;
2178 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2179
2180 switch (opclass)
2181 {
2182 case c0opc_addi:
2183 /* 3 operands: dst, src, imm. */
2184 gdb_assert (nods == 3);
2185 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2186 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2187 break;
2188 case c0opc_add:
2189 /* 3 operands: dst, src1, src2. */
2190 gdb_assert (nods == 3);
2191 if (src[odv[1]].fr_reg == C0_CONST)
2192 {
2193 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2194 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2195 }
2196 else if (src[odv[2]].fr_reg == C0_CONST)
2197 {
2198 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2199 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2200 }
2201 else dst[odv[0]].fr_reg = C0_INEXP;
2202 break;
2203 case c0opc_and:
2204 /* 3 operands: dst, src1, src2. */
2205 gdb_assert (nods == 3);
2206 if (cache->c0.c0_fpalign == 0)
2207 {
2208 /* Handle dynamic stack alignment. */
2209 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2210 {
2211 if (src[odv[2]].fr_reg == C0_CONST)
2212 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2213 break;
2214 }
2215 else if ((src[odv[0]].fr_reg == spreg)
2216 && (src[odv[2]].fr_reg == spreg))
2217 {
2218 if (src[odv[1]].fr_reg == C0_CONST)
2219 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2220 break;
2221 }
2222 /* else fall through. */
2223 }
2224 if (src[odv[1]].fr_reg == C0_CONST)
2225 {
2226 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2227 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2228 }
2229 else if (src[odv[2]].fr_reg == C0_CONST)
2230 {
2231 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2232 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2233 }
2234 else dst[odv[0]].fr_reg = C0_INEXP;
2235 break;
2236 case c0opc_sub:
2237 /* 3 operands: dst, src1, src2. */
2238 gdb_assert (nods == 3);
2239 if (src[odv[2]].fr_reg == C0_CONST)
2240 {
2241 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2242 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2243 }
2244 else dst[odv[0]].fr_reg = C0_INEXP;
2245 break;
2246 case c0opc_mov:
2247 /* 2 operands: dst, src [, src]. */
2248 gdb_assert (nods == 2);
2249 /* First, check if it's a special case of saving unaligned SP
2250 to a spare register in case of dynamic stack adjustment.
2251 But, only do it one time. The second time could be initializing
2252 frame pointer. We don't want to overwrite the first one. */
2253 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2254 cache->c0.c0_old_sp = odv[0];
2255
2256 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2257 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2258 break;
2259 case c0opc_movi:
2260 /* 2 operands: dst, imm. */
2261 gdb_assert (nods == 2);
2262 dst[odv[0]].fr_reg = C0_CONST;
2263 dst[odv[0]].fr_ofs = odv[1];
2264 break;
2265 case c0opc_l32r:
2266 /* 2 operands: dst, literal offset. */
2267 gdb_assert (nods == 2);
2268 /* litbase = xtensa_get_litbase (pc); can be also used. */
2269 litbase = (tdep->litbase_regnum == -1)
2271 (tdep->litbase_regnum);
2272 litaddr = litbase & 1
2273 ? (litbase & ~1) + (signed)odv[1]
2274 : (pc + 3 + (signed)odv[1]) & ~3;
2275 litval = read_memory_integer (litaddr, 4, byte_order);
2276 dst[odv[0]].fr_reg = C0_CONST;
2277 dst[odv[0]].fr_ofs = litval;
2278 break;
2279 case c0opc_s32i:
2280 /* 3 operands: value, base, offset. */
2281 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2282 /* First, check if it's a spill for saved unaligned SP,
2283 when dynamic stack adjustment was applied to this frame. */
2284 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2285 && (odv[1] == spreg) /* SP usage indicates spill. */
2286 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2287 cache->c0.c0_sp_ofs = odv[2];
2288
2289 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2290 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2291 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2292 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2293 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2294 {
2295 /* ISA encoding guarantees alignment. But, check it anyway. */
2296 gdb_assert ((odv[2] & 3) == 0);
2297 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2298 }
2299 break;
2300 /* If we end up inside Window Overflow / Underflow interrupt handler
2301 report an error because these handlers should have been handled
2302 already in a different way. */
2303 case c0opc_l32e:
2304 case c0opc_s32e:
2305 case c0opc_rfwo:
2306 case c0opc_rfwu:
2307 return 1;
2308 default:
2309 return 1;
2310 }
2311 return 0;
2312}
2313
2314/* Analyze prologue of the function at start address to determine if it uses
2315 the Call0 ABI, and if so track register moves and linear modifications
2316 in the prologue up to the PC or just beyond the prologue, whichever is
2317 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2318 prologue. The prologue may overlap non-prologue instructions but is
2319 guaranteed to end by the first flow-control instruction (jump, branch,
2320 call or return). Since an optimized function may move information around
2321 and change the stack frame arbitrarily during the prologue, the information
2322 is guaranteed valid only at the point in the function indicated by the PC.
2323 May be used to skip the prologue or identify the ABI, w/o tracking.
2324
2325 Returns: Address of first instruction after prologue, or PC (whichever
2326 is first), or 0, if decoding failed (in libisa).
2327 Input args:
2328 start Start address of function/prologue.
2329 pc Program counter to stop at. Use 0 to continue to end of prologue.
2330 If 0, avoids infinite run-on in corrupt code memory by bounding
2331 the scan to the end of the function if that can be determined.
2332 nregs Number of general registers to track.
2333 InOut args:
2334 cache Xtensa frame cache.
2335
2336 Note that these may produce useful results even if decoding fails
2337 because they begin with default assumptions that analysis may change. */
2338
2339static CORE_ADDR
2341 CORE_ADDR start, CORE_ADDR pc,
2342 int nregs, xtensa_frame_cache_t *cache)
2343{
2344 CORE_ADDR ia; /* Current insn address in prologue. */
2345 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2346 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2347 gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2348 xtensa_isa isa; /* libisa ISA handle. */
2349 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2350 xtensa_format ifmt; /* libisa instruction format. */
2351 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2352 xtensa_opcode opc; /* Opcode in current slot. */
2353 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2354 int nods; /* Opcode number of operands. */
2355 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2356 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2357 int j; /* General loop counter. */
2358 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2359 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2360 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2361
2362 struct symtab_and_line prologue_sal;
2363
2364 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2365 (int)start, (int)pc);
2366
2367 /* Try to limit the scan to the end of the function if a non-zero pc
2368 arg was not supplied to avoid probing beyond the end of valid memory.
2369 If memory is full of garbage that classifies as c0opc_uninteresting.
2370 If this fails (eg. if no symbols) pc ends up 0 as it was.
2371 Initialize the Call0 frame and register tracking info.
2372 Assume it's Call0 until an 'entry' instruction is encountered.
2373 Assume we may be in the prologue until we hit a flow control instr. */
2374
2375 rtmp = NULL;
2376 body_pc = UINT_MAX;
2377 end_pc = 0;
2378
2379 /* Find out, if we have an information about the prologue from DWARF. */
2380 prologue_sal = find_pc_line (start, 0);
2381 if (prologue_sal.line != 0) /* Found debug info. */
2382 body_pc = prologue_sal.end;
2383
2384 /* If we are going to analyze the prologue in general without knowing about
2385 the current PC, make the best assumption for the end of the prologue. */
2386 if (pc == 0)
2387 {
2388 find_pc_partial_function (start, 0, NULL, &end_pc);
2389 body_pc = std::min (end_pc, body_pc);
2390 }
2391 else
2392 body_pc = std::min (pc, body_pc);
2393
2394 cache->call0 = 1;
2395 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2396
2397 isa = xtensa_default_isa;
2398 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2399 ins = xtensa_insnbuf_alloc (isa);
2400 slot = xtensa_insnbuf_alloc (isa);
2401
2402 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2403 {
2404 /* (Re)fill instruction buffer from memory if necessary, but do not
2405 read memory beyond PC to be sure we stay within text section
2406 (this protection only works if a non-zero pc is supplied). */
2407
2408 if (ia + xtensa_isa_maxlength (isa) > bt)
2409 {
2410 ba = ia;
2411 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2412 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2413 error (_("Unable to read target memory ..."));
2414 }
2415
2416 /* Decode format information. */
2417
2418 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2419 ifmt = xtensa_format_decode (isa, ins);
2420 if (ifmt == XTENSA_UNDEFINED)
2421 {
2422 fail = 1;
2423 goto done;
2424 }
2425 ilen = xtensa_format_length (isa, ifmt);
2426 if (ilen == XTENSA_UNDEFINED)
2427 {
2428 fail = 1;
2429 goto done;
2430 }
2431 islots = xtensa_format_num_slots (isa, ifmt);
2432 if (islots == XTENSA_UNDEFINED)
2433 {
2434 fail = 1;
2435 goto done;
2436 }
2437
2438 /* Analyze a bundle or a single instruction, using a snapshot of
2439 the register tracking info as input for the entire bundle so that
2440 register changes do not take effect within this bundle. */
2441
2442 for (j = 0; j < nregs; ++j)
2443 rtmp[j] = cache->c0.c0_rt[j];
2444
2445 for (is = 0; is < islots; ++is)
2446 {
2447 /* Decode a slot and classify the opcode. */
2448
2449 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2450 if (fail)
2451 goto done;
2452
2453 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2454 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2455 (unsigned)ia, opc);
2456 if (opc == XTENSA_UNDEFINED)
2457 opclass = c0opc_illegal;
2458 else
2459 opclass = call0_classify_opcode (isa, opc);
2460
2461 /* Decide whether to track this opcode, ignore it, or bail out. */
2462
2463 switch (opclass)
2464 {
2465 case c0opc_illegal:
2466 case c0opc_break:
2467 fail = 1;
2468 goto done;
2469
2471 continue;
2472
2473 case c0opc_flow: /* Flow control instructions stop analysis. */
2474 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2475 goto done;
2476
2477 case c0opc_entry:
2478 cache->call0 = 0;
2479 ia += ilen; /* Skip over 'entry' insn. */
2480 goto done;
2481
2482 default:
2483 cache->call0 = 1;
2484 }
2485
2486 /* Only expected opcodes should get this far. */
2487
2488 /* Extract and decode the operands. */
2489 nods = xtensa_opcode_num_operands (isa, opc);
2490 if (nods == XTENSA_UNDEFINED)
2491 {
2492 fail = 1;
2493 goto done;
2494 }
2495
2496 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2497 {
2498 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2499 is, slot, &odv[j]);
2500 if (fail)
2501 goto done;
2502
2503 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2504 if (fail)
2505 goto done;
2506 }
2507
2508 /* Check operands to verify use of 'mov' assembler macro. */
2509 if (opclass == c0opc_mov && nods == 3)
2510 {
2511 if (odv[2] == odv[1])
2512 {
2513 nods = 2;
2514 if ((odv[0] == 1) && (odv[1] != 1))
2515 /* OR A1, An, An , where n != 1.
2516 This means we are inside epilogue already. */
2517 goto done;
2518 }
2519 else
2520 {
2521 opclass = c0opc_uninteresting;
2522 continue;
2523 }
2524 }
2525
2526 /* Track register movement and modification for this operation. */
2527 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2528 opclass, nods, odv, ia, 1, cache);
2529 if (fail)
2530 goto done;
2531 }
2532 }
2533done:
2534 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2535 (unsigned)ia, fail ? "failed" : "succeeded");
2536 xtensa_insnbuf_free(isa, slot);
2537 xtensa_insnbuf_free(isa, ins);
2538 return fail ? XTENSA_ISA_BADPC : ia;
2539}
2540
2541/* Initialize frame cache for the current frame in CALL0 ABI. */
2542
2543static void
2545 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2546{
2547 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2548 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2549 CORE_ADDR start_pc; /* The beginning of the function. */
2550 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2551 CORE_ADDR sp, fp, ra;
2552 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2553 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2554
2556 (this_frame, tdep->a0_base + 1);
2557 fp = sp; /* Assume FP == SP until proven otherwise. */
2558
2559 /* Find the beginning of the prologue of the function containing the PC
2560 and analyze it up to the PC or the end of the prologue. */
2561
2562 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2563 {
2564 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2565
2566 if (body_pc == XTENSA_ISA_BADPC)
2567 {
2568 warning_once ();
2569 ra = 0;
2570 goto finish_frame_analysis;
2571 }
2572 }
2573
2574 /* Get the frame information and FP (if used) at the current PC.
2575 If PC is in the prologue, the prologue analysis is more reliable
2576 than DWARF info. We don't not know for sure, if PC is in the prologue,
2577 but we do know no calls have yet taken place, so we can almost
2578 certainly rely on the prologue analysis. */
2579
2580 if (body_pc <= pc)
2581 {
2582 /* Prologue analysis was successful up to the PC.
2583 It includes the cases when PC == START_PC. */
2584 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2585 /* c0_hasfp == true means there is a frame pointer because
2586 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2587 was derived from SP. Otherwise, it would be C0_FP. */
2588 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2589 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2590 fp_regnum += tdep->a0_base;
2591 }
2592 else /* No data from the prologue analysis. */
2593 {
2594 c0_hasfp = 0;
2595 fp_regnum = tdep->a0_base + C0_SP;
2596 c0_frmsz = 0;
2597 start_pc = pc;
2598 }
2599
2600 if (cache->c0.c0_fpalign)
2601 {
2602 /* This frame has a special prologue with a dynamic stack adjustment
2603 to force an alignment, which is bigger than standard 16 bytes. */
2604
2605 CORE_ADDR unaligned_sp;
2606
2607 if (cache->c0.c0_old_sp == C0_INEXP)
2608 /* This can't be. Prologue code should be consistent.
2609 Unaligned stack pointer should be saved in a spare register. */
2610 {
2611 warning_once ();
2612 ra = 0;
2613 goto finish_frame_analysis;
2614 }
2615
2616 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2617 /* Saved unaligned value of SP is kept in a register. */
2618 unaligned_sp = get_frame_register_unsigned
2619 (this_frame, tdep->a0_base + cache->c0.c0_old_sp);
2620 else
2621 /* Get the value from stack. */
2622 unaligned_sp = (CORE_ADDR)
2623 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2624
2625 prev_sp = unaligned_sp + c0_frmsz;
2626 }
2627 else
2628 prev_sp = fp + c0_frmsz;
2629
2630 /* Frame size from debug info or prologue tracking does not account for
2631 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2632 if (c0_hasfp)
2633 {
2634 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2635
2636 /* Update the stack frame size. */
2637 c0_frmsz += fp - sp;
2638 }
2639
2640 /* Get the return address (RA) from the stack if saved,
2641 or try to get it from a register. */
2642
2643 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2644 if (to_stk != C0_NOSTK)
2645 ra = (CORE_ADDR)
2646 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2647 4, byte_order);
2648
2649 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2650 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2651 {
2652 /* Special case for terminating backtrace at a function that wants to
2653 be seen as the outermost one. Such a function will clear it's RA (A0)
2654 register to 0 in the prologue instead of saving its original value. */
2655 ra = 0;
2656 }
2657 else
2658 {
2659 /* RA was copied to another register or (before any function call) may
2660 still be in the original RA register. This is not always reliable:
2661 even in a leaf function, register tracking stops after prologue, and
2662 even in prologue, non-prologue instructions (not tracked) may overwrite
2663 RA or any register it was copied to. If likely in prologue or before
2664 any call, use retracking info and hope for the best (compiler should
2665 have saved RA in stack if not in a leaf function). If not in prologue,
2666 too bad. */
2667
2668 int i;
2669 for (i = 0;
2670 (i < C0_NREGS)
2671 && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2672 ++i);
2673 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2674 i = C0_RA;
2675 if (i < C0_NREGS)
2676 {
2678 (this_frame,
2679 tdep->a0_base + cache->c0.c0_rt[i].fr_reg);
2680 }
2681 else ra = 0;
2682 }
2683
2684 finish_frame_analysis:
2685 cache->pc = start_pc;
2686 cache->ra = ra;
2687 /* RA == 0 marks the outermost frame. Do not go past it. */
2688 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2689 cache->c0.fp_regnum = fp_regnum;
2690 cache->c0.c0_frmsz = c0_frmsz;
2691 cache->c0.c0_hasfp = c0_hasfp;
2692 cache->c0.c0_fp = fp;
2693}
2695static CORE_ADDR a0_saved;
2696static CORE_ADDR a7_saved;
2697static CORE_ADDR a11_saved;
2698static int a0_was_saved;
2699static int a7_was_saved;
2700static int a11_was_saved;
2701
2702/* Simulate L32E instruction: AT <-- ref (AS + offset). */
2703static void
2704execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2705{
2706 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2707 int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb);
2708 int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb);
2709 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2710 unsigned int spilled_value
2712
2713 if ((at == 0) && !a0_was_saved)
2714 {
2716 a0_was_saved = 1;
2717 }
2718 else if ((at == 7) && !a7_was_saved)
2719 {
2721 a7_was_saved = 1;
2722 }
2723 else if ((at == 11) && !a11_was_saved)
2724 {
2726 a11_was_saved = 1;
2727 }
2728
2729 xtensa_write_register (atreg, spilled_value);
2730}
2731
2732/* Simulate S32E instruction: AT --> ref (AS + offset). */
2733static void
2734execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2735{
2736 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2737 int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb);
2738 int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb);
2739 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2740 ULONGEST spilled_value = xtensa_read_register (atreg);
2741
2744 spilled_value);
2745}
2747#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2754};
2755
2756/* Execute instruction stream from current PC until hitting RFWU or RFWO.
2757 Return type of Xtensa Window Interrupt Handler on success. */
2759execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2760{
2761 xtensa_isa isa;
2762 xtensa_insnbuf ins, slot;
2763 gdb_byte ibuf[XTENSA_ISA_BSZ];
2764 CORE_ADDR ia, bt, ba;
2765 xtensa_format ifmt;
2766 int ilen, islots, is;
2767 xtensa_opcode opc;
2768 int insn_num = 0;
2769 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2770 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2771
2772 uint32_t at, as, offset;
2773
2774 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2775 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2776
2777 isa = xtensa_default_isa;
2778 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2779 ins = xtensa_insnbuf_alloc (isa);
2780 slot = xtensa_insnbuf_alloc (isa);
2781 ba = 0;
2782 ia = current_pc;
2783 bt = ia;
2784
2785 a0_was_saved = 0;
2786 a7_was_saved = 0;
2787 a11_was_saved = 0;
2788
2789 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2790 {
2791 if (ia + xtensa_isa_maxlength (isa) > bt)
2792 {
2793 ba = ia;
2794 bt = (ba + XTENSA_ISA_BSZ);
2795 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2796 return xtNoExceptionHandler;
2797 }
2798 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2799 ifmt = xtensa_format_decode (isa, ins);
2800 if (ifmt == XTENSA_UNDEFINED)
2801 return xtNoExceptionHandler;
2802 ilen = xtensa_format_length (isa, ifmt);
2803 if (ilen == XTENSA_UNDEFINED)
2804 return xtNoExceptionHandler;
2805 islots = xtensa_format_num_slots (isa, ifmt);
2806 if (islots == XTENSA_UNDEFINED)
2807 return xtNoExceptionHandler;
2808 for (is = 0; is < islots; ++is)
2809 {
2810 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2811 return xtNoExceptionHandler;
2812 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2813 if (opc == XTENSA_UNDEFINED)
2814 return xtNoExceptionHandler;
2815 switch (call0_classify_opcode (isa, opc))
2816 {
2817 case c0opc_illegal:
2818 case c0opc_flow:
2819 case c0opc_entry:
2820 case c0opc_break:
2821 /* We expect none of them here. */
2822 return xtNoExceptionHandler;
2823 case c0opc_l32e:
2825 break;
2826 case c0opc_s32e:
2828 break;
2829 case c0opc_rfwo: /* RFWO. */
2830 /* Here, we return from WindowOverflow handler and,
2831 if we stopped at the very beginning, which means
2832 A0 was saved, we have to restore it now. */
2833 if (a0_was_saved)
2834 {
2835 int arreg = arreg_number (gdbarch,
2836 tdep->a0_base,
2837 wb);
2839 }
2840 return xtWindowOverflow;
2841 case c0opc_rfwu: /* RFWU. */
2842 /* Here, we return from WindowUnderflow handler.
2843 Let's see if either A7 or A11 has to be restored. */
2844 if (WindowUnderflow12)
2845 {
2846 if (a11_was_saved)
2847 {
2848 int arreg = arreg_number (gdbarch,
2849 tdep->a0_base + 11,
2850 wb);
2852 }
2853 }
2854 else if (a7_was_saved)
2855 {
2856 int arreg = arreg_number (gdbarch,
2857 tdep->a0_base + 7,
2858 wb);
2860 }
2861 return xtWindowUnderflow;
2862 default: /* Simply skip this insns. */
2863 continue;
2864 }
2865
2866 /* Decode arguments for L32E / S32E and simulate their execution. */
2867 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2868 return xtNoExceptionHandler;
2869 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2870 return xtNoExceptionHandler;
2871 if (xtensa_operand_decode (isa, opc, 0, &at))
2872 return xtNoExceptionHandler;
2873 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2874 return xtNoExceptionHandler;
2875 if (xtensa_operand_decode (isa, opc, 1, &as))
2876 return xtNoExceptionHandler;
2877 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2878 return xtNoExceptionHandler;
2879 if (xtensa_operand_decode (isa, opc, 2, &offset))
2880 return xtNoExceptionHandler;
2881
2882 (*func) (gdbarch, at, as, offset, wb);
2883 }
2884
2885 ia += ilen;
2886 }
2887 return xtNoExceptionHandler;
2888}
2889
2890/* Handle Window Overflow / Underflow exception frames. */
2891
2892static void
2894 xtensa_frame_cache_t *cache,
2895 CORE_ADDR pc)
2896{
2897 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2898 CORE_ADDR ps, wb, ws, ra;
2899 int epc1_regnum, i, regnum;
2901 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2902
2903 /* Read PS, WB, and WS from the hardware. Note that PS register
2904 must be present, if Windowed ABI is supported. */
2906 wb = xtensa_read_register (tdep->wb_regnum);
2907 ws = xtensa_read_register (tdep->ws_regnum);
2908
2909 /* Execute all the remaining instructions from Window Interrupt Handler
2910 by simulating them on the remote protocol level. On return, set the
2911 type of Xtensa Window Interrupt Handler, or report an error. */
2912 eh_type = execute_code (gdbarch, pc, wb);
2913 if (eh_type == xtNoExceptionHandler)
2914 error (_("\
2915Unable to decode Xtensa Window Interrupt Handler's code."));
2916
2917 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2918 cache->call0 = 0; /* It's Windowed ABI. */
2919
2920 /* All registers for the cached frame will be alive. */
2921 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2922 cache->wd.aregs[i] = -1;
2923
2924 if (eh_type == xtWindowOverflow)
2925 cache->wd.ws = ws ^ (1 << wb);
2926 else /* eh_type == xtWindowUnderflow. */
2927 cache->wd.ws = ws | (1 << wb);
2928
2929 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2931 cache->wd.wb);
2933 cache->wd.callsize = WINSIZE (ra);
2934 cache->prev_sp = xtensa_read_register (regnum + 1);
2935 /* Set regnum to a frame pointer of the frame being cached. */
2938 tdep->a0_base + regnum,
2939 cache->wd.wb);
2940 cache->base = get_frame_register_unsigned (this_frame, regnum);
2941
2942 /* Read PC of interrupted function from EPC1 register. */
2943 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2944 if (epc1_regnum < 0)
2945 error(_("Unable to read Xtensa register EPC1"));
2946 cache->ra = xtensa_read_register (epc1_regnum);
2947 cache->pc = get_frame_func (this_frame);
2948}
2949
2950
2951/* Skip function prologue.
2952
2953 Return the pc of the first instruction after prologue. GDB calls this to
2954 find the address of the first line of the function or (if there is no line
2955 number information) to skip the prologue for planting breakpoints on
2956 function entries. Use debug info (if present) or prologue analysis to skip
2957 the prologue to achieve reliable debugging behavior. For windowed ABI,
2958 only the 'entry' instruction is skipped. It is not strictly necessary to
2959 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2960 backtrace at any point in the prologue, however certain potential hazards
2961 are avoided and a more "normal" debugging experience is ensured by
2962 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2963 For example, if we don't skip the prologue:
2964 - Some args may not yet have been saved to the stack where the debug
2965 info expects to find them (true anyway when only 'entry' is skipped);
2966 - Software breakpoints ('break' instrs) may not have been unplanted
2967 when the prologue analysis is done on initializing the frame cache,
2968 and breaks in the prologue will throw off the analysis.
2969
2970 If we have debug info ( line-number info, in particular ) we simply skip
2971 the code associated with the first function line effectively skipping
2972 the prologue code. It works even in cases like
2973
2974 int main()
2975 { int local_var = 1;
2976 ....
2977 }
2978
2979 because, for this source code, both Xtensa compilers will generate two
2980 separate entries ( with the same line number ) in dwarf line-number
2981 section to make sure there is a boundary between the prologue code and
2982 the rest of the function.
2983
2984 If there is no debug info, we need to analyze the code. */
2985
2986/* #define DONT_SKIP_PROLOGUE */
2987
2988static CORE_ADDR
2989xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2990{
2991 struct symtab_and_line prologue_sal;
2992 CORE_ADDR body_pc;
2993
2994 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2995
2996#if DONT_SKIP_PROLOGUE
2997 return start_pc;
2998#endif
2999
3000 /* Try to find first body line from debug info. */
3001
3002 prologue_sal = find_pc_line (start_pc, 0);
3003 if (prologue_sal.line != 0) /* Found debug info. */
3004 {
3005 /* In Call0, it is possible to have a function with only one instruction
3006 ('ret') resulting from a one-line optimized function that does nothing.
3007 In that case, prologue_sal.end may actually point to the start of the
3008 next function in the text section, causing a breakpoint to be set at
3009 the wrong place. Check, if the end address is within a different
3010 function, and if so return the start PC. We know we have symbol
3011 information. */
3012
3013 CORE_ADDR end_func;
3014
3015 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3016 if ((tdep->call_abi == CallAbiCall0Only)
3017 && call0_ret (start_pc, prologue_sal.end))
3018 return start_pc;
3019
3020 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3021 if (end_func != start_pc)
3022 return start_pc;
3023
3024 return prologue_sal.end;
3025 }
3026
3027 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3028 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3030 return body_pc != 0 ? body_pc : start_pc;
3031}
3032
3033/* Verify the current configuration. */
3034static void
3036{
3037 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3038 string_file log;
3039
3040 /* Verify that we got a reasonable number of AREGS. */
3041 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3042 log.printf (_("\
3043\n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3044 tdep->num_aregs);
3045
3046 /* Verify that certain registers exist. */
3047
3048 if (tdep->pc_regnum == -1)
3049 log.printf (_("\n\tpc_regnum: No PC register"));
3050 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3051 log.printf (_("\n\tps_regnum: No PS register"));
3052
3054 {
3055 if (tdep->wb_regnum == -1)
3056 log.printf (_("\n\twb_regnum: No WB register"));
3057 if (tdep->ws_regnum == -1)
3058 log.printf (_("\n\tws_regnum: No WS register"));
3059 if (tdep->ar_base == -1)
3060 log.printf (_("\n\tar_base: No AR registers"));
3061 }
3062
3063 if (tdep->a0_base == -1)
3064 log.printf (_("\n\ta0_base: No Ax registers"));
3065
3066 if (!log.empty ())
3067 internal_error (_("the following are invalid: %s"), log.c_str ());
3068}
3069
3070
3071/* Derive specific register numbers from the array of registers. */
3072
3073static void
3075{
3076 xtensa_register_t* rmap;
3077 int n, max_size = 4;
3078
3079 tdep->num_regs = 0;
3080 tdep->num_nopriv_regs = 0;
3081
3082/* Special registers 0..255 (core). */
3083#define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3084/* User registers 0..255. */
3085#define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3086
3087 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3088 {
3089 if (rmap->target_number == 0x0020)
3090 tdep->pc_regnum = n;
3091 else if (rmap->target_number == 0x0100)
3092 tdep->ar_base = n;
3093 else if (rmap->target_number == 0x0000)
3094 tdep->a0_base = n;
3095 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3096 tdep->wb_regnum = n;
3097 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3098 tdep->ws_regnum = n;
3099 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3100 tdep->debugcause_regnum = n;
3101 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3102 tdep->exccause_regnum = n;
3103 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3104 tdep->excvaddr_regnum = n;
3105 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3106 tdep->lbeg_regnum = n;
3107 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3108 tdep->lend_regnum = n;
3109 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3110 tdep->lcount_regnum = n;
3111 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3112 tdep->sar_regnum = n;
3113 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3114 tdep->litbase_regnum = n;
3115 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3116 tdep->ps_regnum = n;
3117 else if (rmap->target_number == XTENSA_DBREGN_UREG(231))
3118 tdep->threadptr_regnum = n;
3119#if 0
3120 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3121 tdep->interrupt_regnum = n;
3122 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3123 tdep->interrupt2_regnum = n;
3124 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3125 tdep->cpenable_regnum = n;
3126#endif
3127
3128 if (rmap->byte_size > max_size)
3129 max_size = rmap->byte_size;
3130 if (rmap->mask != 0 && tdep->num_regs == 0)
3131 tdep->num_regs = n;
3132 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3133 && tdep->num_nopriv_regs == 0)
3134 tdep->num_nopriv_regs = n;
3135 }
3136 if (tdep->num_regs == 0)
3137 tdep->num_regs = tdep->num_nopriv_regs;
3138
3139 /* Number of pseudo registers. */
3140 tdep->num_pseudo_regs = n - tdep->num_regs;
3141
3142 /* Empirically determined maximum sizes. */
3143 tdep->max_register_raw_size = max_size;
3144 tdep->max_register_virtual_size = max_size;
3145}
3146
3147/* Module "constructor" function. */
3148
3150
3151static struct gdbarch *
3153{
3154 DEBUGTRACE ("gdbarch_init()\n");
3155
3156 if (!xtensa_default_isa)
3157 xtensa_default_isa = xtensa_isa_init (0, 0);
3158
3159 /* We have to set the byte order before we call gdbarch_alloc. */
3160 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3161
3163 = gdbarch_alloc (&info,
3165 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3166 xtensa_derive_tdep (tdep);
3167
3168 /* Verify our configuration. */
3171
3172 set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3174
3175 /* Pseudo-Register read/write. */
3178
3179 /* Set target information. */
3185
3186 /* Renumber registers for known formats (stabs and dwarf2). */
3189
3190 /* We provide our own function to get register information. */
3193
3194 /* To call functions from GDB using dummy frame. */
3196
3198
3200
3201 /* Advance PC across any prologue instructions to reach "real" code. */
3203
3204 /* Stack grows downward. */
3206
3207 /* Set breakpoints. */
3212
3213 /* After breakpoint instruction or illegal instruction, pc still
3214 points at break instruction, so don't decrement. */
3216
3217 /* We don't skip args. */
3219
3221
3223
3225
3226 /* Frame handling. */
3230
3232
3235
3238
3241
3242 /* Hook in the ABI-specific overrides, if they have been registered. */
3244
3245 return gdbarch;
3246}
3247
3248static void
3249xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3250{
3251 error (_("xtensa_dump_tdep(): not implemented"));
3252}
3253
3255void
3257{
3260
3261 add_setshow_zuinteger_cmd ("xtensa",
3264 _("Set Xtensa debugging."),
3265 _("Show Xtensa debugging."), _("\
3266When non-zero, Xtensa-specific debugging is enabled. \
3267Can be 1, 2, 3, or 4 indicating the level of debugging."),
3268 NULL,
3269 NULL,
3271}
int regnum
const char *const name
int code
Definition ada-lex.l:670
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep, gdbarch_supports_arch_info_ftype *supports_arch_info)
static std::vector< const char * > arches
Definition arch-utils.c:685
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition arch-utils.c:177
struct_return
Definition arm-tdep.h:84
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
Definition blockframe.c:373
frame_info * get() const
Definition frame.h:294
enum register_status raw_read(int regnum, gdb_byte *buf)
Definition regcache.c:611
enum register_status raw_read_part(int regnum, int offset, int len, gdb_byte *buf)
Definition regcache.c:1022
enum register_status cooked_read(int regnum, gdb_byte *buf)
Definition regcache.c:698
gdbarch * arch() const
Definition regcache.c:231
void raw_supply(int regnum, const void *buf) override
Definition regcache.c:1062
void cooked_write(int regnum, const gdb_byte *buf)
Definition regcache.c:870
void raw_write_part(int regnum, int offset, int len, const gdb_byte *buf)
Definition regcache.c:1032
void raw_write(int regnum, const gdb_byte *buf)
Definition regcache.c:833
void printf(const char *,...) ATTRIBUTE_PRINTF(2
Definition ui-file.c:40
struct cmd_list_element * showdebuglist
Definition cli-cmds.c:167
struct cmd_list_element * setdebuglist
Definition cli-cmds.c:165
set_show_commands add_setshow_zuinteger_cmd(const char *name, enum command_class theclass, unsigned int *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
@ class_maintenance
Definition command.h:65
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition corefile.c:347
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition corefile.c:306
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
Definition corefile.c:380
void read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition corefile.c:238
int safe_read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, LONGEST *return_value)
Definition corefile.c:264
LONGEST read_memory_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition corefile.c:296
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition defs.h:515
CORE_ADDR extract_typed_address(const gdb_byte *buf, struct type *type)
Definition findvar.c:152
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition defs.h:480
return_value_convention
Definition defs.h:257
@ RETURN_VALUE_REGISTER_CONVENTION
Definition defs.h:260
@ RETURN_VALUE_STRUCT_CONVENTION
Definition defs.h:267
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition frame.c:1369
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition frame-base.c:93
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
struct value * frame_unwind_got_memory(frame_info_ptr frame, int regnum, CORE_ADDR addr)
struct value * frame_unwind_got_register(frame_info_ptr frame, int regnum, int new_regnum)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
Definition frame.c:1399
CORE_ADDR get_frame_pc(frame_info_ptr frame)
Definition frame.c:2712
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition frame.c:736
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition frame.c:3027
void frame_unwind_register(frame_info_ptr next_frame, int regnum, gdb_byte *buf)
Definition frame.c:1243
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
Definition frame.c:1098
@ NORMAL_FRAME
Definition frame.h:187
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition frame.h:825
@ fp_regnum
Definition frv-tdep.h:36
void set_gdbarch_stab_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_stab_reg_to_regnum_ftype *stab_reg_to_regnum)
int gdbarch_pc_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2054
void set_gdbarch_unwind_pc(struct gdbarch *gdbarch, gdbarch_unwind_pc_ftype *unwind_pc)
void set_gdbarch_ps_regnum(struct gdbarch *gdbarch, int ps_regnum)
Definition gdbarch.c:2081
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition gdbarch.c:1396
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_wchar_bit(struct gdbarch *gdbarch, int wchar_bit)
Definition gdbarch.c:1680
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_decr_pc_after_break(struct gdbarch *gdbarch, CORE_ADDR decr_pc_after_break)
Definition gdbarch.c:2913
void set_gdbarch_believe_pcc_promotion(struct gdbarch *gdbarch, int believe_pcc_promotion)
Definition gdbarch.c:2470
void set_gdbarch_wchar_signed(struct gdbarch *gdbarch, int wchar_signed)
Definition gdbarch.c:1698
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
Definition gdbarch.c:3574
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition gdbarch.c:1930
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition gdbarch.c:2047
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition gdbarch.c:2064
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *register_type)
int gdbarch_ps_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2071
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition gdbarch.c:1958
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition gdbarch.c:1941
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_dummy_id(struct gdbarch *gdbarch, gdbarch_dummy_id_ftype *dummy_id)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
void set_gdbarch_iterate_over_regset_sections(struct gdbarch *gdbarch, gdbarch_iterate_over_regset_sections_ftype *iterate_over_regset_sections)
void set_gdbarch_frame_args_skip(struct gdbarch *gdbarch, CORE_ADDR frame_args_skip)
Definition gdbarch.c:3012
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, gdbarch_tdep_up tdep)
Definition gdbarch.c:266
std::unique_ptr< gdbarch_tdep_base > gdbarch_tdep_up
Definition gdbarch.h:73
void iterate_over_regset_sections_cb(const char *sect_name, int supply_size, int collect_size, const struct regset *regset, const char *human_name, void *cb_data)
Definition gdbarch.h:104
static int gdbarch_num_cooked_regs(gdbarch *arch)
Definition gdbarch.h:390
function_call_return_method
Definition gdbarch.h:114
@ return_method_struct
Definition gdbarch.h:126
struct type * init_integer_type(type_allocator &alloc, int bit, int unsigned_p, const char *name)
Definition gdbtypes.c:3355
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
Definition gdbtypes.c:6168
struct type * check_typedef(struct type *type)
Definition gdbtypes.c:2966
mach_port_t kern_return_t mach_port_t mach_msg_type_name_t msgportsPoly mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
Definition gnu-nat.c:1861
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition gnu-nat.c:1790
size_t size
Definition go32-nat.c:239
info(Component c)
Definition gdbarch.py:41
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition osabi.c:382
int value
Definition py-param.c:79
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:649
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:796
void regcache_raw_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:677
struct regcache * get_current_regcache(void)
Definition regcache.c:429
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:825
const reggroup *const general_reggroup
Definition reggroups.c:251
const reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition reggroups.c:34
const reggroup *const system_reggroup
Definition reggroups.c:253
const reggroup *const float_reggroup
Definition reggroups.c:252
const reggroup *const save_reggroup
Definition reggroups.c:256
const reggroup *const all_reggroup
Definition reggroups.c:255
void reggroup_add(struct gdbarch *gdbarch, const reggroup *group)
Definition reggroups.c:124
const reggroup *const restore_reggroup
Definition reggroups.c:257
const reggroup *const vector_reggroup
Definition reggroups.c:254
@ USER_REGGROUP
Definition reggroups.h:32
void(* func)(remote_target *remote, char *)
constexpr gdb_byte little_breakpoint[]
constexpr gdb_byte big_breakpoint[]
void set_solib_svr4_fetch_link_map_offsets(struct gdbarch *gdbarch, struct link_map_offsets *(*flmo)(void))
struct link_map_offsets * svr4_ilp32_fetch_link_map_offsets(void)
struct type * builtin_uint16
Definition gdbtypes.h:2116
struct type * builtin_double
Definition gdbtypes.h:2090
struct type * builtin_uint128
Definition gdbtypes.h:2124
struct type * builtin_long
Definition gdbtypes.h:2081
struct type * builtin_data_ptr
Definition gdbtypes.h:2135
struct type * builtin_uint32
Definition gdbtypes.h:2120
struct type * builtin_uint64
Definition gdbtypes.h:2122
struct type * builtin_int
Definition gdbtypes.h:2080
struct type * builtin_uint8
Definition gdbtypes.h:2114
struct type * virtual_type
struct ctype_cache * next
CORE_ADDR pc
Definition symtab.h:2337
CORE_ADDR end
Definition symtab.h:2338
type_code code() const
Definition gdbtypes.h:956
ULONGEST length() const
Definition gdbtypes.h:983
Definition value.h:130
gdb::array_view< const gdb_byte > contents()
Definition value.c:1262
struct type * type() const
Definition value.h:180
xtensa_c0reg_t c0_rt[C0_NREGS]
xtensa_elf_greg_t ar[64]
Definition xtensa.h:40
xtensa_elf_greg_t lcount
Definition xtensa.h:34
xtensa_elf_greg_t ps
Definition xtensa.h:31
xtensa_elf_greg_t pc
Definition xtensa.h:30
xtensa_elf_greg_t lbeg
Definition xtensa.h:32
xtensa_elf_greg_t windowstart
Definition xtensa.h:36
xtensa_elf_greg_t lend
Definition xtensa.h:33
xtensa_elf_greg_t sar
Definition xtensa.h:35
xtensa_elf_greg_t windowbase
Definition xtensa.h:37
xtensa_call0_frame_cache_t c0
xtensa_windowed_frame_cache_t wd
unsigned int isa_use_density_instructions
unsigned int num_pseudo_regs
unsigned int num_aregs
unsigned int target_flags
unsigned int num_nopriv_regs
xtensa_register_t * regmap
unsigned int isa_use_exceptions
unsigned int num_regs
unsigned int isa_use_windowed_registers
struct ctype_cache * type_entries
struct type * ctype
xtensa_register_group_t group
unsigned int target_number
xtensa_register_type_t type
const char * name
const xtensa_mask_t * mask
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]
struct symtab_and_line find_pc_line(CORE_ADDR pc, int notcurrent)
Definition symtab.c:3295
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition target.c:1785
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition utils.c:1886
#define gdb_stdlog
Definition utils.h:190
struct value * value_cast(struct type *type, struct value *arg2)
Definition valops.c:403
static xtensa_insn_kind call0_classify_opcode(xtensa_isa isa, xtensa_opcode opc)
static int rwx_special_register(const char *opcname)
xtensa_exception_handler_t
@ xtNoExceptionHandler
@ xtWindowOverflow
@ xtWindowUnderflow
static void xtensa_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buffer)
static const char * xtensa_register_name(struct gdbarch *gdbarch, int regnum)
static struct xtensa_frame_cache * xtensa_alloc_frame_cache(int windowed)
#define SAVE_REST_VALID
struct xtensa_windowed_frame_cache xtensa_windowed_frame_cache_t
static enum return_value_convention xtensa_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static int xtensa_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
struct xtensa_call0_frame_cache xtensa_call0_frame_cache_t
static void xtensa_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
#define DEBUGVERB(args...)
Definition xtensa-tdep.c:62
static unsigned int xtensa_debug_level
Definition xtensa-tdep.c:48
static struct gdbarch * xtensa_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
#define XTENSA_ISA_BADPC
static int call0_ret(CORE_ADDR start_pc, CORE_ADDR finish_pc)
static unsigned int xtensa_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR current_pc)
#define SAVE_REST_FLAGS
static CORE_ADDR xtensa_frame_align(struct gdbarch *gdbarch, CORE_ADDR address)
#define XTENSA_NUM_SAVED_AREGS
static int extract_call_winsize(struct gdbarch *gdbarch, CORE_ADDR pc)
xtensa_register_t xtensa_rmap[]
#define TX_PS
Definition xtensa-tdep.c:86
#define DEBUGTRACE(args...)
Definition xtensa-tdep.c:58
#define BIG_BREAKPOINT
static void xtensa_init_reggroups(void)
static const reggroup * xtensa_ar_reggroup
#define RETURN_FP
static const reggroup * xtensa_user_reggroup
static CORE_ADDR a11_saved
#define C0_RA
static void call0_frame_cache(frame_info_ptr this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static CORE_ADDR a7_saved
#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
static CORE_ADDR call0_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR pc, int nregs, xtensa_frame_cache_t *cache)
#define C0_NOSTK
#define XTENSA_MAX_REGISTER_SIZE
#define LITTLE_BREAKPOINT
#define ARG_NOF(tdep)
Definition xtensa-tdep.c:89
#define DENSITY_BIG_BREAKPOINT
static unsigned long xtensa_read_register(int regnum)
#define C0_INEXP
static void xtensa_add_reggroups(struct gdbarch *gdbarch)
static int xtensa_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
static void xtensa_window_interrupt_frame_cache(frame_info_ptr this_frame, xtensa_frame_cache_t *cache, CORE_ADDR pc)
static CORE_ADDR a0_saved
#define XTENSA_DBREGN_UREG(n)
void _initialize_xtensa_tdep()
static void xtensa_write_register(int regnum, ULONGEST value)
#define C0_MAXOPDS
static void xtensa_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
static const reggroup * xtensa_cp[XTENSA_MAX_COPROCESSOR]
#define CALLINC(ps)
Definition xtensa-tdep.c:80
static struct value * xtensa_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static void xtensa_store_return_value(struct type *type, struct regcache *regcache, const void *dst)
static int a7_was_saved
static int call0_track_op(struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], xtensa_insn_kind opclass, int nods, unsigned odv[], CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
#define PS_CALLINC_SHIFT
Definition xtensa-tdep.c:78
xtensa_insn_kind
@ c0opc_sub
@ c0opc_s32e
@ c0opc_add
@ c0opc_movi
@ c0opc_l32e
@ c0opc_addi
@ c0opc_mov
@ c0opc_l32r
@ c0opc_rwxsr
@ c0opc_entry
@ c0opc_rfwu
@ c0opc_uninteresting
@ c0opc_flow
@ c0opc_illegal
@ c0opc_and
@ c0opc_break
@ c0opc_s32i
@ c0opc_NrOf
@ c0opc_rfwo
static int areg_number(struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
static xtensa_exception_handler_t execute_code(struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
static void execute_l32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
static const struct frame_unwind xtensa_unwind
static int arreg_number(struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
#define XTENSA_DBREGN_SREG(n)
static void execute_s32e(struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
#define C0_SP
static CORE_ADDR xtensa_frame_base_address(frame_info_ptr this_frame, void **this_cache)
static CORE_ADDR xtensa_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
#define ARG_1ST(tdep)
Definition xtensa-tdep.c:92
#define DEBUGINFO(args...)
Definition xtensa-tdep.c:54
struct xtensa_c0reg xtensa_c0reg_t
static const struct frame_base xtensa_frame_base
static struct regset xtensa_gregset
static int xtensa_find_register_by_name(struct gdbarch *gdbarch, const char *name)
static int xtensa_coprocessor_register_group(const struct reggroup *group)
static const gdb_byte * xtensa_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
struct xtensa_frame_cache xtensa_frame_cache_t
static int windowing_enabled(struct gdbarch *gdbarch, unsigned int ps)
static struct xtensa_frame_cache * xtensa_frame_cache(frame_info_ptr this_frame, void **this_cache)
#define XTENSA_ISA_BSZ
static int xtensa_session_once_reported
static const reggroup * xtensa_vectra_reggroup
#define WINSIZE(ra)
Definition xtensa-tdep.c:81
static int a11_was_saved
static void xtensa_derive_tdep(xtensa_gdbarch_tdep *tdep)
static void xtensa_verify_config(struct gdbarch *gdbarch)
#define REGISTER_SIZE
Definition xtensa-tdep.c:74
static void xtensa_supply_gregset(const struct regset *regset, struct regcache *rc, int regnum, const void *gregs, size_t len)
static struct frame_id xtensa_dummy_id(struct gdbarch *gdbarch, frame_info_ptr this_frame)
#define C0_FP
#define XTENSA_IS_ENTRY(gdbarch, op1)
static enum register_status xtensa_register_read_masked(readable_regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer)
static enum register_status xtensa_pseudo_register_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buffer)
static void xtensa_extract_return_value(struct type *type, struct regcache *regcache, void *dst)
#define SP_ALIGNMENT
Definition xtensa-tdep.c:68
#define C0_ARGS
xtensa_isa xtensa_default_isa
static struct type * xtensa_register_type(struct gdbarch *gdbarch, int regnum)
static CORE_ADDR xtensa_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR start_pc)
#define PS_EXC
static int xtensa_reg_to_regnum(struct gdbarch *gdbarch, int regnum)
#define RETURN_RET
#define PS_WOE
#define DENSITY_LITTLE_BREAKPOINT
static void xtensa_register_write_masked(struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer)
static CORE_ADDR xtensa_unwind_pc(struct gdbarch *gdbarch, frame_info_ptr next_frame)
#define C0_CONST
static void xtensa_iterate_over_regset_sections(struct gdbarch *gdbarch, iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache)
static void warning_once(void)
static int xtensa_window_interrupt_insn(struct gdbarch *gdbarch, CORE_ADDR pc)
static int a0_was_saved
#define WB_SHIFT
#define XTENSA_MAX_COPROCESSOR
Definition xtensa-tdep.h:51
xtensa_register_group_t
Definition xtensa-tdep.h:54
@ xtRegisterGroupUser
Definition xtensa-tdep.h:63
@ xtRegisterGroupState
Definition xtensa-tdep.h:60
@ xtRegisterGroupFloat
Definition xtensa-tdep.h:64
@ xtRegisterGroupVectra
Definition xtensa-tdep.h:65
@ xtRegisterGroupCP0
Definition xtensa-tdep.h:69
@ xtRegisterGroupAddrReg
Definition xtensa-tdep.h:57
@ xtRegisterGroupGeneral
Definition xtensa-tdep.h:62
@ CallAbiCall0Only
xtensa_register_type_t
Definition xtensa-tdep.h:35
@ xtRegisterTypeUnknown
Definition xtensa-tdep.h:45
@ xtRegisterTypeMapped
Definition xtensa-tdep.h:41
@ xtRegisterTypeTieRegfile
Definition xtensa-tdep.h:39
@ xtRegisterTypeUnmapped
Definition xtensa-tdep.h:42
@ xtRegisterTypeTieState
Definition xtensa-tdep.h:40
@ xtTargetFlagsNonVisibleRegs
Definition xtensa-tdep.h:85
@ xtTargetFlagsUseFetchStore
Definition xtensa-tdep.h:86
#define XTENSA_REGISTER_FLAGS_PRIVILEGED
#define C0_NREGS
Definition xtensa.h:46