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x86-dregs.c
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1/* Debug register code for x86 (i386 and x86-64).
2
3 Copyright (C) 2001-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "gdbsupport/common-defs.h"
21#include "x86-dregs.h"
22#include "gdbsupport/break-common.h"
23
24/* Support for hardware watchpoints and breakpoints using the x86
25 debug registers.
26
27 This provides several functions for inserting and removing
28 hardware-assisted breakpoints and watchpoints, testing if one or
29 more of the watchpoints triggered and at what address, checking
30 whether a given region can be watched, etc.
31
32 The functions below implement debug registers sharing by reference
33 counts, and allow to watch regions up to 16 bytes long. */
34
35/* Accessor macros for low-level function vector. */
36
37/* Can we update the inferior's debug registers? */
38
39static bool
41{
42 return x86_dr_low.set_addr != nullptr;
43}
44
45/* Update the inferior's debug register REGNUM from STATE. */
46
47static void
48x86_dr_low_set_addr (struct x86_debug_reg_state *new_state, int i)
49{
50 x86_dr_low.set_addr (i, new_state->dr_mirror[i]);
51}
52
53/* Return the inferior's debug register REGNUM. */
54
55static CORE_ADDR
57{
58 return x86_dr_low.get_addr (i);
59}
60
61/* Can we update the inferior's DR7 control register? */
62
63static bool
65{
66 return x86_dr_low.set_control != nullptr;
67}
68
69/* Update the inferior's DR7 debug control register from STATE. */
70
71static void
76
77/* Return the value of the inferior's DR7 debug control register. */
78
79static unsigned long
84
85/* Return the value of the inferior's DR6 debug status register. */
86
87static unsigned long
92
93/* Return the debug register size, in bytes. */
94
95static int
100
101/* Support for 8-byte wide hw watchpoints. */
102#define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8)
103
104/* DR7 Debug Control register fields. */
105
106/* How many bits to skip in DR7 to get to R/W and LEN fields. */
107#define DR_CONTROL_SHIFT 16
108/* How many bits in DR7 per R/W and LEN field for each watchpoint. */
109#define DR_CONTROL_SIZE 4
110
111/* Watchpoint/breakpoint read/write fields in DR7. */
112#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
113#define DR_RW_WRITE (0x1) /* Break on data writes. */
114#define DR_RW_READ (0x3) /* Break on data reads or writes. */
115
116/* This is here for completeness. No platform supports this
117 functionality yet (as of March 2001). Note that the DE flag in the
118 CR4 register needs to be set to support this. */
119#ifndef DR_RW_IORW
120#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
121#endif
122
123/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
124 is so we could OR this with the read/write field defined above. */
125#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
126#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
127#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
128#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
129
130/* Local and Global Enable flags in DR7.
131
132 When the Local Enable flag is set, the breakpoint/watchpoint is
133 enabled only for the current task; the processor automatically
134 clears this flag on every task switch. When the Global Enable flag
135 is set, the breakpoint/watchpoint is enabled for all tasks; the
136 processor never clears this flag.
137
138 Currently, all watchpoint are locally enabled. If you need to
139 enable them globally, read the comment which pertains to this in
140 x86_insert_aligned_watchpoint below. */
141#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
142#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
143#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
144
145/* Local and global exact breakpoint enable flags (a.k.a. slowdown
146 flags). These are only required on i386, to allow detection of the
147 exact instruction which caused a watchpoint to break; i486 and
148 later processors do that automatically. We set these flags for
149 backwards compatibility. */
150#define DR_LOCAL_SLOWDOWN (0x100)
151#define DR_GLOBAL_SLOWDOWN (0x200)
152
153/* Fields reserved by Intel. This includes the GD (General Detect
154 Enable) flag, which causes a debug exception to be generated when a
155 MOV instruction accesses one of the debug registers.
156
157 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
158#define DR_CONTROL_RESERVED (0xFC00)
159
160/* Auxiliary helper macros. */
161
162/* A value that masks all fields in DR7 that are reserved by Intel. */
163#define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
164
165/* The I'th debug register is vacant if its Local and Global Enable
166 bits are reset in the Debug Control register. */
167#define X86_DR_VACANT(state, i) \
168 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
169
170/* Locally enable the break/watchpoint in the I'th debug register. */
171#define X86_DR_LOCAL_ENABLE(state, i) \
172 do { \
173 (state)->dr_control_mirror |= \
174 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
175 } while (0)
176
177/* Globally enable the break/watchpoint in the I'th debug register. */
178#define X86_DR_GLOBAL_ENABLE(state, i) \
179 do { \
180 (state)->dr_control_mirror |= \
181 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
182 } while (0)
183
184/* Disable the break/watchpoint in the I'th debug register. */
185#define X86_DR_DISABLE(state, i) \
186 do { \
187 (state)->dr_control_mirror &= \
188 ~(3 << (DR_ENABLE_SIZE * (i))); \
189 } while (0)
190
191/* Set in DR7 the RW and LEN fields for the I'th debug register. */
192#define X86_DR_SET_RW_LEN(state, i, rwlen) \
193 do { \
194 (state)->dr_control_mirror &= \
195 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
196 (state)->dr_control_mirror |= \
197 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
198 } while (0)
199
200/* Get from DR7 the RW and LEN fields for the I'th debug register. */
201#define X86_DR_GET_RW_LEN(dr7, i) \
202 (((dr7) \
203 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
204
205/* Did the watchpoint whose address is in the I'th register break? */
206#define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
207
208/* Types of operations supported by x86_handle_nonaligned_watchpoint. */
210
211/* Print the values of the mirrored debug registers. */
212
213static void
215 const char *func, CORE_ADDR addr,
216 int len, enum target_hw_bp_type type)
217{
218 int i;
219
220 debug_printf ("%s", func);
221 if (addr || len)
222 debug_printf (" (addr=%s, len=%d, type=%s)",
223 phex (addr, 8), len,
224 type == hw_write ? "data-write"
225 : (type == hw_read ? "data-read"
226 : (type == hw_access ? "data-read/write"
227 : (type == hw_execute ? "instruction-execute"
228 /* FIXME: if/when I/O read/write
229 watchpoints are supported, add them
230 here. */
231 : "??unknown??"))));
232 debug_printf (":\n");
233
234 debug_printf ("\tCONTROL (DR7): 0x%s\n", phex (state->dr_control_mirror, 8));
235 debug_printf ("\tSTATUS (DR6): 0x%s\n", phex (state->dr_status_mirror, 8));
236
238 {
239 debug_printf ("\tDR%d: addr=0x%s, ref.count=%d\n",
240 i, phex (state->dr_mirror[i],
242 state->dr_ref_count[i]);
243 }
244}
245
246/* Return the value of a 4-bit field for DR7 suitable for watching a
247 region of LEN bytes for accesses of type TYPE. LEN is assumed to
248 have the value of 1, 2, or 4. */
249
250static unsigned
251x86_length_and_rw_bits (int len, enum target_hw_bp_type type)
252{
253 unsigned rw;
254
255 switch (type)
256 {
257 case hw_execute:
258 rw = DR_RW_EXECUTE;
259 break;
260 case hw_write:
261 rw = DR_RW_WRITE;
262 break;
263 case hw_read:
264 internal_error (_("The i386 doesn't support "
265 "data-read watchpoints.\n"));
266 case hw_access:
267 rw = DR_RW_READ;
268 break;
269#if 0
270 /* Not yet supported. */
271 case hw_io_access:
272 rw = DR_RW_IORW;
273 break;
274#endif
275 default:
276 internal_error (_("\
277Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"),
278 (int) type);
279 }
280
281 switch (len)
282 {
283 case 1:
284 return (DR_LEN_1 | rw);
285 case 2:
286 return (DR_LEN_2 | rw);
287 case 4:
288 return (DR_LEN_4 | rw);
289 case 8:
291 return (DR_LEN_8 | rw);
292 /* FALL THROUGH */
293 default:
294 internal_error (_("\
295Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len);
296 }
297}
298
299/* Insert a watchpoint at address ADDR, which is assumed to be aligned
300 according to the length of the region to watch. LEN_RW_BITS is the
301 value of the bits from DR7 which describes the length and access
302 type of the region to be watched by this watchpoint. Return 0 on
303 success, -1 on failure. */
304
305static int
307 CORE_ADDR addr, unsigned len_rw_bits)
308{
309 int i;
310
312 return -1;
313
314 /* First, look for an occupied debug register with the same address
315 and the same RW and LEN definitions. If we find one, we can
316 reuse it for this watchpoint as well (and save a register). */
318 {
319 if (!X86_DR_VACANT (state, i)
320 && state->dr_mirror[i] == addr
321 && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
322 {
323 state->dr_ref_count[i]++;
324 return 0;
325 }
326 }
327
328 /* Next, look for a vacant debug register. */
330 {
331 if (X86_DR_VACANT (state, i))
332 break;
333 }
334
335 /* No more debug registers! */
336 if (i >= DR_NADDR)
337 return -1;
338
339 /* Now set up the register I to watch our region. */
340
341 /* Record the info in our local mirrored array. */
342 state->dr_mirror[i] = addr;
343 state->dr_ref_count[i] = 1;
344 X86_DR_SET_RW_LEN (state, i, len_rw_bits);
345 /* Note: we only enable the watchpoint locally, i.e. in the current
346 task. Currently, no x86 target allows or supports global
347 watchpoints; however, if any target would want that in the
348 future, GDB should probably provide a command to control whether
349 to enable watchpoints globally or locally, and the code below
350 should use global or local enable and slow-down flags as
351 appropriate. */
352 X86_DR_LOCAL_ENABLE (state, i);
355
356 return 0;
357}
358
359/* Remove a watchpoint at address ADDR, which is assumed to be aligned
360 according to the length of the region to watch. LEN_RW_BITS is the
361 value of the bits from DR7 which describes the length and access
362 type of the region watched by this watchpoint. Return 0 on
363 success, -1 on failure. */
364
365static int
367 CORE_ADDR addr, unsigned len_rw_bits)
368{
369 int i, retval = -1;
370 int all_vacant = 1;
371
373 {
374 if (!X86_DR_VACANT (state, i)
375 && state->dr_mirror[i] == addr
376 && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits)
377 {
378 if (--state->dr_ref_count[i] == 0) /* No longer in use? */
379 {
380 /* Reset our mirror. */
381 state->dr_mirror[i] = 0;
382 X86_DR_DISABLE (state, i);
383 /* Even though not strictly necessary, clear out all
384 bits in DR_CONTROL related to this debug register.
385 Debug output is clearer when we don't have stale bits
386 in place. This also allows the assertion below. */
387 X86_DR_SET_RW_LEN (state, i, 0);
388 }
389 retval = 0;
390 }
391
392 if (!X86_DR_VACANT (state, i))
393 all_vacant = 0;
394 }
395
396 if (all_vacant)
397 {
398 /* Even though not strictly necessary, clear out all of
399 DR_CONTROL, so that when we have no debug registers in use,
400 we end up with DR_CONTROL == 0. The Linux support relies on
401 this for an optimization. Plus, it makes for clearer debug
402 output. */
403 state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN;
404
405 gdb_assert (state->dr_control_mirror == 0);
406 }
407 return retval;
408}
409
410/* Insert or remove a (possibly non-aligned) watchpoint, or count the
411 number of debug registers required to watch a region at address
412 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
413 successful insertion or removal, a positive number when queried
414 about the number of registers, or -1 on failure. If WHAT is not a
415 valid value, bombs through internal_error. */
416
417static int
419 x86_wp_op_t what, CORE_ADDR addr, int len,
420 enum target_hw_bp_type type)
421{
422 int retval = 0;
423 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4;
424
425 static const int size_try_array[8][8] =
426 {
427 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
428 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
429 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
430 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
431 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
432 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
433 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
434 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
435 };
436
437 while (len > 0)
438 {
439 int align = addr % max_wp_len;
440 /* Four (eight on AMD64) is the maximum length a debug register
441 can watch. */
442 int attempt = (len > max_wp_len ? (max_wp_len - 1) : len - 1);
443 int size = size_try_array[attempt][align];
444
445 if (what == WP_COUNT)
446 {
447 /* size_try_array[] is defined such that each iteration
448 through the loop is guaranteed to produce an address and a
449 size that can be watched with a single debug register.
450 Thus, for counting the registers required to watch a
451 region, we simply need to increment the count on each
452 iteration. */
453 retval++;
454 }
455 else
456 {
457 unsigned len_rw = x86_length_and_rw_bits (size, type);
458
459 if (what == WP_INSERT)
460 retval = x86_insert_aligned_watchpoint (state, addr, len_rw);
461 else if (what == WP_REMOVE)
462 retval = x86_remove_aligned_watchpoint (state, addr, len_rw);
463 else
464 internal_error (_("\
465Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"),
466 (int) what);
467 if (retval)
468 break;
469 }
470
471 addr += size;
472 len -= size;
473 }
474
475 return retval;
476}
477
478/* Update the inferior debug registers state, in STATE, with the
479 new debug registers state, in NEW_STATE. */
480
481static void
483 struct x86_debug_reg_state *new_state)
484{
485 int i;
486
488 {
489 if (X86_DR_VACANT (new_state, i) != X86_DR_VACANT (state, i))
490 x86_dr_low_set_addr (new_state, i);
491 else
492 gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]);
493 }
494
495 if (new_state->dr_control_mirror != state->dr_control_mirror)
496 x86_dr_low_set_control (new_state);
497
498 *state = *new_state;
499}
500
501/* Insert a watchpoint to watch a memory region which starts at
502 address ADDR and whose length is LEN bytes. Watch memory accesses
503 of the type TYPE. Return 0 on success, -1 on failure. */
504
505int
507 enum target_hw_bp_type type,
508 CORE_ADDR addr, int len)
509{
510 int retval;
511 /* Work on a local copy of the debug registers, and on success,
512 commit the change back to the inferior. */
513 struct x86_debug_reg_state local_state = *state;
514
515 if (type == hw_read)
516 return 1; /* unsupported */
517
518 if (((len != 1 && len != 2 && len != 4)
519 && !(TARGET_HAS_DR_LEN_8 && len == 8))
520 || addr % len != 0)
521 {
522 retval = x86_handle_nonaligned_watchpoint (&local_state,
523 WP_INSERT,
524 addr, len, type);
525 }
526 else
527 {
528 unsigned len_rw = x86_length_and_rw_bits (len, type);
529
530 retval = x86_insert_aligned_watchpoint (&local_state,
531 addr, len_rw);
532 }
533
534 if (retval == 0)
535 x86_update_inferior_debug_regs (state, &local_state);
536
537 if (show_debug_regs)
538 x86_show_dr (state, "insert_watchpoint", addr, len, type);
539
540 return retval;
541}
542
543/* Remove a watchpoint that watched the memory region which starts at
544 address ADDR, whose length is LEN bytes, and for accesses of the
545 type TYPE. Return 0 on success, -1 on failure. */
546
547int
549 enum target_hw_bp_type type,
550 CORE_ADDR addr, int len)
551{
552 int retval;
553 /* Work on a local copy of the debug registers, and on success,
554 commit the change back to the inferior. */
555 struct x86_debug_reg_state local_state = *state;
556
557 if (((len != 1 && len != 2 && len != 4)
558 && !(TARGET_HAS_DR_LEN_8 && len == 8))
559 || addr % len != 0)
560 {
561 retval = x86_handle_nonaligned_watchpoint (&local_state,
562 WP_REMOVE,
563 addr, len, type);
564 }
565 else
566 {
567 unsigned len_rw = x86_length_and_rw_bits (len, type);
568
569 retval = x86_remove_aligned_watchpoint (&local_state,
570 addr, len_rw);
571 }
572
573 if (retval == 0)
574 x86_update_inferior_debug_regs (state, &local_state);
575
576 if (show_debug_regs)
577 x86_show_dr (state, "remove_watchpoint", addr, len, type);
578
579 return retval;
580}
581
582/* Return non-zero if we can watch a memory region that starts at
583 address ADDR and whose length is LEN bytes. */
584
585int
587 CORE_ADDR addr, int len)
588{
589 int nregs;
590
591 /* Compute how many aligned watchpoints we would need to cover this
592 region. */
594 addr, len, hw_write);
595 return nregs <= DR_NADDR ? 1 : 0;
596}
597
598/* If the inferior has some break/watchpoint that triggered, set the
599 address associated with that break/watchpoint and return non-zero.
600 Otherwise, return zero. */
601
602int
604 CORE_ADDR *addr_p)
605{
606 CORE_ADDR addr = 0;
607 int i;
608 int rc = 0;
609 /* The current thread's DR_STATUS. We always need to read this to
610 check whether some watchpoint caused the trap. */
611 unsigned status;
612 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
613 data breakpoint trap. Only fetch it when necessary, to avoid an
614 unnecessary extra syscall when no watchpoint triggered. */
615 int control_p = 0;
616 unsigned control = 0;
617
618 /* In non-stop/async, threads can be running while we change the
619 global dr_mirror (and friends). Say, we set a watchpoint, and
620 let threads resume. Now, say you delete the watchpoint, or
621 add/remove watchpoints such that dr_mirror changes while threads
622 are running. On targets that support non-stop,
623 inserting/deleting watchpoints updates the global dr_mirror only.
624 It does not update the real thread's debug registers; that's only
625 done prior to resume. Instead, if threads are running when the
626 mirror changes, a temporary and transparent stop on all threads
627 is forced so they can get their copy of the debug registers
628 updated on re-resume. Now, say, a thread hit a watchpoint before
629 having been updated with the new dr_mirror contents, and we
630 haven't yet handled the corresponding SIGTRAP. If we trusted
631 dr_mirror below, we'd mistake the real trapped address (from the
632 last time we had updated debug registers in the thread) with
633 whatever was currently in dr_mirror. So to fix this, dr_mirror
634 always represents intention, what we _want_ threads to have in
635 debug registers. To get at the address and cause of the trap, we
636 need to read the state the thread still has in its debug
637 registers.
638
639 In sum, always get the current debug register values the current
640 thread has, instead of trusting the global mirror. If the thread
641 was running when we last changed watchpoints, the mirror no
642 longer represents what was set in this thread's debug
643 registers. */
644 status = x86_dr_low_get_status ();
645
647 {
648 if (!X86_DR_WATCH_HIT (status, i))
649 continue;
650
651 if (!control_p)
652 {
653 control = x86_dr_low_get_control ();
654 control_p = 1;
655 }
656
657 /* This second condition makes sure DRi is set up for a data
658 watchpoint, not a hardware breakpoint. The reason is that
659 GDB doesn't call the target_stopped_data_address method
660 except for data watchpoints. In other words, I'm being
661 paranoiac. */
662 if (X86_DR_GET_RW_LEN (control, i) != 0)
663 {
664 addr = x86_dr_low_get_addr (i);
665 rc = 1;
666 if (show_debug_regs)
667 x86_show_dr (state, "watchpoint_hit", addr, -1, hw_write);
668 }
669 }
670
671 if (show_debug_regs && addr == 0)
672 x86_show_dr (state, "stopped_data_addr", 0, 0, hw_write);
673
674 if (rc)
675 *addr_p = addr;
676 return rc;
677}
678
679/* Return non-zero if the inferior has some watchpoint that triggered.
680 Otherwise return zero. */
681
682int
684{
685 CORE_ADDR addr = 0;
686 return x86_dr_stopped_data_address (state, &addr);
687}
688
689/* Return non-zero if the inferior has some hardware breakpoint that
690 triggered. Otherwise return zero. */
691
692int
694{
695 CORE_ADDR addr = 0;
696 int i;
697 int rc = 0;
698 /* The current thread's DR_STATUS. We always need to read this to
699 check whether some watchpoint caused the trap. */
700 unsigned status;
701 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
702 breakpoint trap. Only fetch it when necessary, to avoid an
703 unnecessary extra syscall when no watchpoint triggered. */
704 int control_p = 0;
705 unsigned control = 0;
706
707 /* As above, always read the current thread's debug registers rather
708 than trusting dr_mirror. */
709 status = x86_dr_low_get_status ();
710
712 {
713 if (!X86_DR_WATCH_HIT (status, i))
714 continue;
715
716 if (!control_p)
717 {
718 control = x86_dr_low_get_control ();
719 control_p = 1;
720 }
721
722 if (X86_DR_GET_RW_LEN (control, i) == 0)
723 {
724 addr = x86_dr_low_get_addr (i);
725 rc = 1;
726 if (show_debug_regs)
727 x86_show_dr (state, "watchpoint_hit", addr, -1, hw_execute);
728 }
729 }
730
731 return rc;
732}
unsigned dr_status_mirror
Definition x86-dregs.h:86
unsigned dr_control_mirror
Definition x86-dregs.h:86
CORE_ADDR dr_mirror[DR_NADDR]
Definition x86-dregs.h:85
int dr_ref_count[DR_NADDR]
Definition x86-dregs.h:89
void(* set_addr)(int, CORE_ADDR)
Definition x86-dregs.h:49
int debug_register_length
Definition x86-dregs.h:64
unsigned long(* get_control)(void)
Definition x86-dregs.h:61
unsigned long(* get_status)(void)
Definition x86-dregs.h:57
void(* set_control)(unsigned long)
Definition x86-dregs.h:45
CORE_ADDR(* get_addr)(int)
Definition x86-dregs.h:53
#define X86_DR_WATCH_HIT(dr6, i)
Definition x86-dregs.c:206
static bool x86_dr_low_can_set_control()
Definition x86-dregs.c:64
#define DR_LEN_2
Definition x86-dregs.c:126
static int x86_get_debug_register_length()
Definition x86-dregs.c:96
#define X86_DR_DISABLE(state, i)
Definition x86-dregs.c:185
int x86_dr_remove_watchpoint(struct x86_debug_reg_state *state, enum target_hw_bp_type type, CORE_ADDR addr, int len)
Definition x86-dregs.c:548
static void x86_dr_low_set_addr(struct x86_debug_reg_state *new_state, int i)
Definition x86-dregs.c:48
int x86_dr_stopped_by_hw_breakpoint(struct x86_debug_reg_state *state)
Definition x86-dregs.c:693
static void x86_dr_low_set_control(struct x86_debug_reg_state *new_state)
Definition x86-dregs.c:72
x86_wp_op_t
Definition x86-dregs.c:209
@ WP_REMOVE
Definition x86-dregs.c:209
@ WP_COUNT
Definition x86-dregs.c:209
@ WP_INSERT
Definition x86-dregs.c:209
static unsigned long x86_dr_low_get_status()
Definition x86-dregs.c:88
static void x86_show_dr(struct x86_debug_reg_state *state, const char *func, CORE_ADDR addr, int len, enum target_hw_bp_type type)
Definition x86-dregs.c:214
static void x86_update_inferior_debug_regs(struct x86_debug_reg_state *state, struct x86_debug_reg_state *new_state)
Definition x86-dregs.c:482
int x86_dr_stopped_by_watchpoint(struct x86_debug_reg_state *state)
Definition x86-dregs.c:683
int x86_dr_insert_watchpoint(struct x86_debug_reg_state *state, enum target_hw_bp_type type, CORE_ADDR addr, int len)
Definition x86-dregs.c:506
static int x86_remove_aligned_watchpoint(struct x86_debug_reg_state *state, CORE_ADDR addr, unsigned len_rw_bits)
Definition x86-dregs.c:366
int x86_dr_region_ok_for_watchpoint(struct x86_debug_reg_state *state, CORE_ADDR addr, int len)
Definition x86-dregs.c:586
#define X86_DR_GET_RW_LEN(dr7, i)
Definition x86-dregs.c:201
#define X86_DR_LOCAL_ENABLE(state, i)
Definition x86-dregs.c:171
#define X86_DR_CONTROL_MASK
Definition x86-dregs.c:163
static int x86_insert_aligned_watchpoint(struct x86_debug_reg_state *state, CORE_ADDR addr, unsigned len_rw_bits)
Definition x86-dregs.c:306
#define X86_DR_SET_RW_LEN(state, i, rwlen)
Definition x86-dregs.c:192
#define DR_RW_EXECUTE
Definition x86-dregs.c:112
static unsigned x86_length_and_rw_bits(int len, enum target_hw_bp_type type)
Definition x86-dregs.c:251
#define DR_LOCAL_SLOWDOWN
Definition x86-dregs.c:150
static bool x86_dr_low_can_set_addr()
Definition x86-dregs.c:40
int x86_dr_stopped_data_address(struct x86_debug_reg_state *state, CORE_ADDR *addr_p)
Definition x86-dregs.c:603
#define DR_RW_READ
Definition x86-dregs.c:114
static CORE_ADDR x86_dr_low_get_addr(int i)
Definition x86-dregs.c:56
#define DR_LEN_1
Definition x86-dregs.c:125
#define X86_DR_VACANT(state, i)
Definition x86-dregs.c:167
#define TARGET_HAS_DR_LEN_8
Definition x86-dregs.c:102
#define DR_RW_IORW
Definition x86-dregs.c:120
static int x86_handle_nonaligned_watchpoint(struct x86_debug_reg_state *state, x86_wp_op_t what, CORE_ADDR addr, int len, enum target_hw_bp_type type)
Definition x86-dregs.c:418
#define DR_LEN_8
Definition x86-dregs.c:128
static unsigned long x86_dr_low_get_control()
Definition x86-dregs.c:80
#define DR_LEN_4
Definition x86-dregs.c:127
#define DR_RW_WRITE
Definition x86-dregs.c:113
#define ALL_DEBUG_ADDRESS_REGISTERS(i)
Definition x86-dregs.h:93
struct x86_dr_low_type x86_dr_low
#define DR_NADDR
Definition x86-dregs.h:72