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aarch64-linux-nat.c
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1/* Native-dependent code for GNU/Linux AArch64.
2
3 Copyright (C) 2011-2023 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "inferior.h"
24#include "gdbcore.h"
25#include "regcache.h"
26#include "linux-nat.h"
27#include "target-descriptions.h"
28#include "auxv.h"
29#include "gdbcmd.h"
30#include "aarch64-nat.h"
31#include "aarch64-tdep.h"
32#include "aarch64-linux-tdep.h"
33#include "aarch32-linux-nat.h"
34#include "aarch32-tdep.h"
35#include "arch/arm.h"
36#include "nat/aarch64-linux.h"
39
40#include "elf/external.h"
41#include "elf/common.h"
42
43#include "nat/gdb_ptrace.h"
44#include <sys/utsname.h>
45#include <asm/ptrace.h>
46
47#include "gregset.h"
48#include "linux-tdep.h"
49#include "arm-tdep.h"
50
51/* Defines ps_err_e, struct ps_prochandle. */
52#include "gdb_proc_service.h"
53#include "arch-utils.h"
54
56
59
60#include <string.h>
61
62#ifndef TRAP_HWBKPT
63#define TRAP_HWBKPT 0x0004
64#endif
65
67 : public aarch64_nat_target<linux_nat_target>
68{
69public:
70 /* Add our register access methods. */
71 void fetch_registers (struct regcache *, int) override;
72 void store_registers (struct regcache *, int) override;
73
74 const struct target_desc *read_description () override;
75
76 /* Add our hardware breakpoint and watchpoint implementation. */
77 bool stopped_by_watchpoint () override;
78 bool stopped_data_address (CORE_ADDR *) override;
79
80 int can_do_single_step () override;
81
82 /* Override the GNU/Linux inferior startup hook. */
83 void post_startup_inferior (ptid_t) override;
84
85 /* Override the GNU/Linux post attach hook. */
86 void post_attach (int pid) override;
87
88 /* These three defer to common nat/ code. */
89 void low_new_thread (struct lwp_info *lp) override
91 void low_delete_thread (struct arch_lwp_info *lp) override
93 void low_prepare_to_resume (struct lwp_info *lp) override
95
96 void low_new_fork (struct lwp_info *parent, pid_t child_pid) override;
97 void low_forget_process (pid_t pid) override;
98
99 /* Add our siginfo layout converter. */
100 bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
101 override;
102
103 struct gdbarch *thread_architecture (ptid_t) override;
104
105 bool supports_memory_tagging () override;
106
107 /* Read memory allocation tags from memory via PTRACE. */
108 bool fetch_memtags (CORE_ADDR address, size_t len,
109 gdb::byte_vector &tags, int type) override;
110
111 /* Write allocation tags to memory via PTRACE. */
112 bool store_memtags (CORE_ADDR address, size_t len,
113 const gdb::byte_vector &tags, int type) override;
114};
115
117
118/* Called whenever GDB is no longer debugging process PID. It deletes
119 data structures that keep track of debug register state. */
120
121void
126
127/* Fill GDB's register array with the general-purpose register values
128 from the current thread. */
129
130static void
132{
133 int ret, tid;
134 struct gdbarch *gdbarch = regcache->arch ();
135 elf_gregset_t regs;
136 struct iovec iovec;
137
138 /* Make sure REGS can hold all registers contents on both aarch64
139 and arm. */
140 gdb_static_assert (sizeof (regs) >= 18 * 4);
141
142 tid = regcache->ptid ().lwp ();
143
144 iovec.iov_base = &regs;
145 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
146 iovec.iov_len = 18 * 4;
147 else
148 iovec.iov_len = sizeof (regs);
149
150 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
151 if (ret < 0)
152 perror_with_name (_("Unable to fetch general registers"));
153
154 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
155 aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
156 else
157 {
158 int regno;
159
160 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
161 regcache->raw_supply (regno, &regs[regno - AARCH64_X0_REGNUM]);
162 }
163}
164
165/* Store to the current thread the valid general-purpose register
166 values in the GDB's register array. */
167
168static void
170{
171 int ret, tid;
172 elf_gregset_t regs;
173 struct iovec iovec;
174 struct gdbarch *gdbarch = regcache->arch ();
175
176 /* Make sure REGS can hold all registers contents on both aarch64
177 and arm. */
178 gdb_static_assert (sizeof (regs) >= 18 * 4);
179 tid = regcache->ptid ().lwp ();
180
181 iovec.iov_base = &regs;
182 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
183 iovec.iov_len = 18 * 4;
184 else
185 iovec.iov_len = sizeof (regs);
186
187 ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
188 if (ret < 0)
189 perror_with_name (_("Unable to fetch general registers"));
190
191 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
192 aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
193 else
194 {
195 int regno;
196
197 for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
198 if (REG_VALID == regcache->get_register_status (regno))
199 regcache->raw_collect (regno, &regs[regno - AARCH64_X0_REGNUM]);
200 }
201
202 ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
203 if (ret < 0)
204 perror_with_name (_("Unable to store general registers"));
205}
206
207/* Fill GDB's register array with the fp/simd register values
208 from the current thread. */
209
210static void
212{
213 int ret, tid;
214 elf_fpregset_t regs;
215 struct iovec iovec;
216 struct gdbarch *gdbarch = regcache->arch ();
217
218 /* Make sure REGS can hold all VFP registers contents on both aarch64
219 and arm. */
220 gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
221
222 tid = regcache->ptid ().lwp ();
223
224 iovec.iov_base = &regs;
225
226 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
227 {
228 iovec.iov_len = ARM_VFP3_REGS_SIZE;
229
230 ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
231 if (ret < 0)
232 perror_with_name (_("Unable to fetch VFP registers"));
233
234 aarch32_vfp_regcache_supply (regcache, (gdb_byte *) &regs, 32);
235 }
236 else
237 {
238 int regno;
239
240 iovec.iov_len = sizeof (regs);
241
242 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
243 if (ret < 0)
244 perror_with_name (_("Unable to fetch vFP/SIMD registers"));
245
246 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
247 regcache->raw_supply (regno, &regs.vregs[regno - AARCH64_V0_REGNUM]);
248
251 }
252}
253
254/* Store to the current thread the valid fp/simd register
255 values in the GDB's register array. */
256
257static void
259{
260 int ret, tid;
261 elf_fpregset_t regs;
262 struct iovec iovec;
263 struct gdbarch *gdbarch = regcache->arch ();
264
265 /* Make sure REGS can hold all VFP registers contents on both aarch64
266 and arm. */
267 gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
268 tid = regcache->ptid ().lwp ();
269
270 iovec.iov_base = &regs;
271
272 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
273 {
274 iovec.iov_len = ARM_VFP3_REGS_SIZE;
275
276 ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
277 if (ret < 0)
278 perror_with_name (_("Unable to fetch VFP registers"));
279
280 aarch32_vfp_regcache_collect (regcache, (gdb_byte *) &regs, 32);
281 }
282 else
283 {
284 int regno;
285
286 iovec.iov_len = sizeof (regs);
287
288 ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
289 if (ret < 0)
290 perror_with_name (_("Unable to fetch FP/SIMD registers"));
291
292 for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
293 if (REG_VALID == regcache->get_register_status (regno))
295 (regno, (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);
296
298 regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
300 regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);
301 }
302
303 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
304 {
305 ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
306 if (ret < 0)
307 perror_with_name (_("Unable to store VFP registers"));
308 }
309 else
310 {
311 ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
312 if (ret < 0)
313 perror_with_name (_("Unable to store FP/SIMD registers"));
314 }
315}
316
317/* Fill GDB's REGCACHE with the valid SVE register values from the thread
318 associated with REGCACHE.
319
320 This function handles reading data from SVE or SSVE states, depending
321 on which state is active at the moment. */
322
323static void
325{
326 /* Fetch SVE state from the thread and copy it into the register cache. */
328}
329
330/* Store the valid SVE register values from GDB's REGCACHE to the thread
331 associated with REGCACHE.
332
333 This function handles writing data to SVE or SSVE states, depending
334 on which state is active at the moment. */
335
336static void
338{
339 /* Fetch SVE state from the register cache and update the thread TID with
340 it. */
342}
343
344/* Fill GDB's REGCACHE with the ZA register set contents from the
345 thread associated with REGCACHE. If there is no active ZA register state,
346 make the ZA register contents zero. */
347
348static void
350{
352 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
353
354 /* Read ZA state from the thread to the register cache. */
356 regcache,
357 tdep->sme_za_regnum,
358 tdep->sme_svg_regnum,
359 tdep->sme_svcr_regnum);
360}
361
362/* Store the NT_ARM_ZA register set contents from GDB's REGCACHE to the thread
363 associated with REGCACHE. */
364
365static void
367{
369 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
370
371 /* Write ZA state from the register cache to the thread. */
373 regcache,
374 tdep->sme_za_regnum,
375 tdep->sme_svg_regnum,
376 tdep->sme_svcr_regnum);
377}
378
379/* Fill GDB's REGCACHE with the ZT register set contents from the
380 thread associated with REGCACHE. If there is no active ZA register state,
381 make the ZT register contents zero. */
382
383static void
385{
387 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
388
389 /* Read ZT state from the thread to the register cache. */
391 regcache,
392 tdep->sme2_zt0_regnum);
393}
394
395/* Store the NT_ARM_ZT register set contents from GDB's REGCACHE to the
396 thread associated with REGCACHE. */
397
398static void
400{
402 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
403
404 /* Write ZT state from the register cache to the thread. */
406 regcache,
407 tdep->sme2_zt0_regnum);
408}
409
410/* Fill GDB's register array with the pointer authentication mask values from
411 the current thread. */
412
413static void
415{
417 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
418 int ret;
419 struct iovec iovec;
420 uint64_t pauth_regset[2] = {0, 0};
421 int tid = regcache->ptid ().lwp ();
422
423 iovec.iov_base = &pauth_regset;
424 iovec.iov_len = sizeof (pauth_regset);
425
426 ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
427 if (ret != 0)
428 perror_with_name (_("unable to fetch pauth registers"));
429
431 &pauth_regset[0]);
433 &pauth_regset[1]);
434}
435
436/* Fill GDB's register array with the MTE register values from
437 the current thread. */
438
439static void
441{
443 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
444 int regno = tdep->mte_reg_base;
445
446 gdb_assert (regno != -1);
447
448 uint64_t tag_ctl = 0;
449 struct iovec iovec;
450
451 iovec.iov_base = &tag_ctl;
452 iovec.iov_len = sizeof (tag_ctl);
453
454 int tid = get_ptrace_pid (regcache->ptid ());
455 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
456 perror_with_name (_("unable to fetch MTE registers"));
457
458 regcache->raw_supply (regno, &tag_ctl);
459}
460
461/* Store to the current thread the valid MTE register set in the GDB's
462 register array. */
463
464static void
466{
468 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
469 int regno = tdep->mte_reg_base;
470
471 gdb_assert (regno != -1);
472
473 uint64_t tag_ctl = 0;
474
475 if (REG_VALID != regcache->get_register_status (regno))
476 return;
477
478 regcache->raw_collect (regno, (char *) &tag_ctl);
479
480 struct iovec iovec;
481
482 iovec.iov_base = &tag_ctl;
483 iovec.iov_len = sizeof (tag_ctl);
484
485 int tid = get_ptrace_pid (regcache->ptid ());
486 if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
487 perror_with_name (_("unable to store MTE registers"));
488}
489
490/* Fill GDB's register array with the TLS register values from
491 the current thread. */
492
493static void
495{
497 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
498 int regno = tdep->tls_regnum_base;
499
500 gdb_assert (regno != -1);
501 gdb_assert (tdep->tls_register_count > 0);
502
503 uint64_t tpidrs[tdep->tls_register_count];
504 memset(tpidrs, 0, sizeof(tpidrs));
505
506 struct iovec iovec;
507 iovec.iov_base = tpidrs;
508 iovec.iov_len = sizeof (tpidrs);
509
510 int tid = get_ptrace_pid (regcache->ptid ());
511 if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
512 perror_with_name (_("unable to fetch TLS registers"));
513
514 for (int i = 0; i < tdep->tls_register_count; i++)
515 regcache->raw_supply (regno + i, &tpidrs[i]);
516}
517
518/* Store to the current thread the valid TLS register set in GDB's
519 register array. */
520
521static void
523{
525 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
526 int regno = tdep->tls_regnum_base;
527
528 gdb_assert (regno != -1);
529 gdb_assert (tdep->tls_register_count > 0);
530
531 uint64_t tpidrs[tdep->tls_register_count];
532 memset(tpidrs, 0, sizeof(tpidrs));
533
534 for (int i = 0; i < tdep->tls_register_count; i++)
535 {
536 if (REG_VALID != regcache->get_register_status (regno + i))
537 continue;
538
539 regcache->raw_collect (regno + i, (char *) &tpidrs[i]);
540 }
541
542 struct iovec iovec;
543 iovec.iov_base = &tpidrs;
544 iovec.iov_len = sizeof (tpidrs);
545
546 int tid = get_ptrace_pid (regcache->ptid ());
547 if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
548 perror_with_name (_("unable to store TLS register"));
549}
550
551/* The AArch64 version of the "fetch_registers" target_ops method. Fetch
552 REGNO from the target and place the result into REGCACHE. */
553
554static void
556{
558 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
559
560 /* Do we need to fetch all registers? */
561 if (regno == -1)
562 {
564
565 /* We attempt to fetch SVE registers if there is support for either
566 SVE or SME (due to the SSVE state of SME). */
567 if (tdep->has_sve () || tdep->has_sme ())
569 else
571
572 if (tdep->has_pauth ())
574
575 if (tdep->has_mte ())
577
578 if (tdep->has_tls ())
580
581 if (tdep->has_sme ())
583
584 if (tdep->has_sme2 ())
586 }
587 /* General purpose register? */
588 else if (regno < AARCH64_V0_REGNUM)
590 /* SVE register? */
591 else if ((tdep->has_sve () || tdep->has_sme ())
592 && regno <= AARCH64_SVE_VG_REGNUM)
594 /* FPSIMD register? */
595 else if (regno <= AARCH64_FPCR_REGNUM)
597 /* PAuth register? */
598 else if (tdep->has_pauth ()
599 && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
600 || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)))
602 /* SME register? */
603 else if (tdep->has_sme () && regno >= tdep->sme_reg_base
604 && regno < tdep->sme_reg_base + 3)
606 /* SME2 register? */
607 else if (tdep->has_sme2 () && regno == tdep->sme2_zt0_regnum)
609 /* MTE register? */
610 else if (tdep->has_mte ()
611 && (regno == tdep->mte_reg_base))
613 /* TLS register? */
614 else if (tdep->has_tls ()
615 && regno >= tdep->tls_regnum_base
616 && regno < tdep->tls_regnum_base + tdep->tls_register_count)
618}
619
620/* A version of the "fetch_registers" target_ops method used when running
621 32-bit ARM code on an AArch64 target. Fetch REGNO from the target and
622 place the result into REGCACHE. */
623
624static void
626{
627 arm_gdbarch_tdep *tdep
628 = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
629
630 if (regno == -1)
631 {
633 if (tdep->vfp_register_count > 0)
635 }
636 else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
638 else if (tdep->vfp_register_count > 0
639 && regno >= ARM_D0_REGNUM
640 && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
641 || regno == ARM_FPSCR_REGNUM))
643}
644
645/* Implement the "fetch_registers" target_ops method. */
646
647void
649 int regno)
650{
651 if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
653 else
655}
656
657/* The AArch64 version of the "store_registers" target_ops method. Copy
658 the value of register REGNO from REGCACHE into the the target. */
659
660static void
662{
664 = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
665
666 /* Do we need to store all registers? */
667 if (regno == -1)
668 {
670
671 /* We attempt to store SVE registers if there is support for either
672 SVE or SME (due to the SSVE state of SME). */
673 if (tdep->has_sve () || tdep->has_sme ())
675 else
677
678 if (tdep->has_mte ())
680
681 if (tdep->has_tls ())
683
684 if (tdep->has_sme ())
686
687 if (tdep->has_sme2 ())
689 }
690 /* General purpose register? */
691 else if (regno < AARCH64_V0_REGNUM)
693 /* SVE register? */
694 else if ((tdep->has_sve () || tdep->has_sme ())
695 && regno <= AARCH64_SVE_VG_REGNUM)
697 /* FPSIMD register? */
698 else if (regno <= AARCH64_FPCR_REGNUM)
700 /* SME register? */
701 else if (tdep->has_sme () && regno >= tdep->sme_reg_base
702 && regno < tdep->sme_reg_base + 3)
704 else if (tdep->has_sme2 () && regno == tdep->sme2_zt0_regnum)
706 /* MTE register? */
707 else if (tdep->has_mte ()
708 && (regno == tdep->mte_reg_base))
710 /* TLS register? */
711 else if (tdep->has_tls ()
712 && regno >= tdep->tls_regnum_base
713 && regno < tdep->tls_regnum_base + tdep->tls_register_count)
715
716 /* PAuth registers are read-only. */
717}
718
719/* A version of the "store_registers" target_ops method used when running
720 32-bit ARM code on an AArch64 target. Copy the value of register REGNO
721 from REGCACHE into the the target. */
722
723static void
725{
726 arm_gdbarch_tdep *tdep
727 = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
728
729 if (regno == -1)
730 {
732 if (tdep->vfp_register_count > 0)
734 }
735 else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
737 else if (tdep->vfp_register_count > 0
738 && regno >= ARM_D0_REGNUM
739 && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
740 || regno == ARM_FPSCR_REGNUM))
742}
743
744/* Implement the "store_registers" target_ops method. */
745
746void
748 int regno)
749{
750 if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
752 else
754}
755
756/* Fill register REGNO (if it is a general-purpose register) in
757 *GREGSETPS with the value in GDB's register array. If REGNO is -1,
758 do this for all registers. */
759
760void
762 gdb_gregset_t *gregsetp, int regno)
763{
765 regno, (gdb_byte *) gregsetp,
767}
768
769/* Fill GDB's register array with the general-purpose register values
770 in *GREGSETP. */
771
772void
774{
776 (const gdb_byte *) gregsetp,
778}
779
780/* Fill register REGNO (if it is a floating-point register) in
781 *FPREGSETP with the value in GDB's register array. If REGNO is -1,
782 do this for all registers. */
783
784void
786 gdb_fpregset_t *fpregsetp, int regno)
787{
789 regno, (gdb_byte *) fpregsetp,
791}
792
793/* Fill GDB's register array with the floating-point register values
794 in *FPREGSETP. */
795
796void
798{
800 (const gdb_byte *) fpregsetp,
802}
803
804/* linux_nat_new_fork hook. */
805
806void
808 pid_t child_pid)
809{
810 pid_t parent_pid;
811 struct aarch64_debug_reg_state *parent_state;
812 struct aarch64_debug_reg_state *child_state;
813
814 /* NULL means no watchpoint has ever been set in the parent. In
815 that case, there's nothing to do. */
816 if (parent->arch_private == NULL)
817 return;
818
819 /* GDB core assumes the child inherits the watchpoints/hw
820 breakpoints of the parent, and will remove them all from the
821 forked off process. Copy the debug registers mirrors into the
822 new process so that all breakpoints and watchpoints can be
823 removed together. */
824
825 parent_pid = parent->ptid.pid ();
826 parent_state = aarch64_get_debug_reg_state (parent_pid);
827 child_state = aarch64_get_debug_reg_state (child_pid);
828 *child_state = *parent_state;
829}
830
831
832/* Called by libthread_db. Returns a pointer to the thread local
833 storage (or its descriptor). */
834
835ps_err_e
837 lwpid_t lwpid, int idx, void **base)
838{
839 int is_64bit_p
840 = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64);
841
842 return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
843}
844
845
846/* Implement the virtual inf_ptrace_target::post_startup_inferior method. */
847
848void
855
856/* Implement the "post_attach" target_ops method. */
857
858void
860{
862 /* Set the hardware debug register capacity. If
863 aarch64_linux_get_debug_reg_capacity is not called
864 (as it is in aarch64_linux_child_post_startup_inferior) then
865 software watchpoints will be used instead of hardware
866 watchpoints when attaching to a target. */
869}
870
871/* Implement the "read_description" target_ops method. */
872
873const struct target_desc *
875{
876 int ret, tid;
877 gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
878 struct iovec iovec;
879
880 if (inferior_ptid == null_ptid)
881 return this->beneath ()->read_description ();
882
883 tid = inferior_ptid.pid ();
884
885 iovec.iov_base = regbuf;
886 iovec.iov_len = ARM_VFP3_REGS_SIZE;
887
888 ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
889 if (ret == 0)
890 return aarch32_read_description ();
891
892 CORE_ADDR hwcap = linux_get_hwcap ();
893 CORE_ADDR hwcap2 = linux_get_hwcap2 ();
894
895 aarch64_features features;
896 /* SVE/SSVE check. Reading VQ may return either the regular vector length
897 or the streaming vector length, depending on whether streaming mode is
898 active or not. */
899 features.vq = aarch64_sve_get_vq (tid);
900 features.pauth = hwcap & AARCH64_HWCAP_PACA;
901 features.mte = hwcap2 & HWCAP2_MTE;
902 features.tls = aarch64_tls_register_count (tid);
903 /* SME feature check. */
904 features.svq = aarch64_za_get_svq (tid);
905
906 /* Check for SME2 support. */
907 if ((hwcap2 & HWCAP2_SME2) || (hwcap2 & HWCAP2_SME2P1))
908 features.sme2 = supports_zt_registers (tid);
909
910 return aarch64_read_description (features);
911}
912
913/* Convert a native/host siginfo object, into/from the siginfo in the
914 layout of the inferiors' architecture. Returns true if any
915 conversion was done; false otherwise. If DIRECTION is 1, then copy
916 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
917 INF. */
918
919bool
921 int direction)
922{
924
925 /* Is the inferior 32-bit? If so, then do fixup the siginfo
926 object. */
927 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
928 {
929 if (direction == 0)
931 native);
932 else
934 (struct compat_siginfo *) inf);
935
936 return true;
937 }
938
939 return false;
940}
941
942/* Implement the "stopped_data_address" target_ops method. */
943
944bool
946{
947 siginfo_t siginfo;
948 struct aarch64_debug_reg_state *state;
949
950 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
951 return false;
952
953 /* This must be a hardware breakpoint. */
954 if (siginfo.si_signo != SIGTRAP
955 || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
956 return false;
957
958 /* Make sure to ignore the top byte, otherwise we may not recognize a
959 hardware watchpoint hit. The stopped data addresses coming from the
960 kernel can potentially be tagged addresses. */
962 const CORE_ADDR addr_trap
963 = gdbarch_remove_non_address_bits (gdbarch, (CORE_ADDR) siginfo.si_addr);
964
965 /* Check if the address matches any watched address. */
967 return aarch64_stopped_data_address (state, addr_trap, addr_p);
968}
969
970/* Implement the "stopped_by_watchpoint" target_ops method. */
971
972bool
974{
975 CORE_ADDR addr;
976
977 return stopped_data_address (&addr);
978}
979
980/* Implement the "can_do_single_step" target_ops method. */
981
982int
987
988/* Implement the "thread_architecture" target_ops method.
989
990 Returns the gdbarch for the thread identified by PTID. If the thread in
991 question is a 32-bit ARM thread, then the architecture returned will be
992 that of the process itself.
993
994 If the thread is an AArch64 thread then we need to check the current
995 vector length; if the vector length has changed then we need to lookup a
996 new gdbarch that matches the new vector length. */
997
998struct gdbarch *
1000{
1001 /* Find the current gdbarch the same way as process_stratum_target. */
1002 inferior *inf = find_inferior_ptid (this, ptid);
1003 gdb_assert (inf != NULL);
1004
1005 /* If this is a 32-bit architecture, then this is ARM, not AArch64.
1006 There's no SVE vectors here, so just return the inferior
1007 architecture. */
1008 if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32)
1009 return inf->gdbarch;
1010
1011 /* Only return the inferior's gdbarch if both vq and svq match the ones in
1012 the tdep. */
1014 = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->gdbarch);
1015 uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
1016 uint64_t svq = aarch64_za_get_svq (ptid.lwp ());
1017 if (vq == tdep->vq && svq == tdep->sme_svq)
1018 return inf->gdbarch;
1019
1020 /* We reach here if any vector length for the thread is different from its
1021 value at process start. Lookup gdbarch via info (potentially creating a
1022 new one) by using a target description that corresponds to the new vq/svq
1023 value and the current architecture features. */
1024
1025 const struct target_desc *tdesc = gdbarch_target_desc (inf->gdbarch);
1027 features.vq = vq;
1028 features.svq = svq;
1029
1030 /* Check for the SME2 feature. */
1031 features.sme2 = supports_zt_registers (ptid.lwp ());
1032
1033 struct gdbarch_info info;
1034 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
1035 info.target_desc = aarch64_read_description (features);
1036 return gdbarch_find_by_info (info);
1037}
1038
1039/* Implement the "supports_memory_tagging" target_ops method. */
1040
1041bool
1046
1047/* Implement the "fetch_memtags" target_ops method. */
1048
1049bool
1050aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
1051 gdb::byte_vector &tags, int type)
1052{
1053 int tid = get_ptrace_pid (inferior_ptid);
1054
1055 /* Allocation tags? */
1056 if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
1057 return aarch64_mte_fetch_memtags (tid, address, len, tags);
1058
1059 return false;
1060}
1061
1062/* Implement the "store_memtags" target_ops method. */
1063
1064bool
1065aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
1066 const gdb::byte_vector &tags, int type)
1067{
1068 int tid = get_ptrace_pid (inferior_ptid);
1069
1070 /* Allocation tags? */
1071 if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
1072 return aarch64_mte_store_memtags (tid, address, len, tags);
1073
1074 return false;
1075}
1076
1078void
void aarch32_gp_regcache_collect(const struct regcache *regcache, uint32_t *regs, int arm_apcs_32)
void aarch32_gp_regcache_supply(struct regcache *regcache, uint32_t *regs, int arm_apcs_32)
void aarch32_vfp_regcache_collect(const struct regcache *regcache, gdb_byte *regs, const int vfp_register_count)
void aarch32_vfp_regcache_supply(struct regcache *regcache, gdb_byte *regs, const int vfp_register_count)
const target_desc * aarch32_read_description()
void aarch64_linux_get_debug_reg_capacity(int tid)
static void aarch64_fetch_registers(struct regcache *regcache, int regno)
static void fetch_sveregs_from_thread(struct regcache *regcache)
static void fetch_mteregs_from_thread(struct regcache *regcache)
#define TRAP_HWBKPT
void _initialize_aarch64_linux_nat()
static void fetch_zt_from_thread(struct regcache *regcache)
void supply_gregset(struct regcache *regcache, const gdb_gregset_t *gregsetp)
void fill_gregset(const struct regcache *regcache, gdb_gregset_t *gregsetp, int regno)
static void aarch32_store_registers(struct regcache *regcache, int regno)
static void fetch_za_from_thread(struct regcache *regcache)
static void store_gregs_to_thread(const struct regcache *regcache)
static void store_zt_to_thread(struct regcache *regcache)
static void store_fpregs_to_thread(const struct regcache *regcache)
static aarch64_linux_nat_target the_aarch64_linux_nat_target
void supply_fpregset(struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
ps_err_e ps_get_thread_area(struct ps_prochandle *ph, lwpid_t lwpid, int idx, void **base)
static void store_za_to_thread(struct regcache *regcache)
static void fetch_tlsregs_from_thread(struct regcache *regcache)
static void store_mteregs_to_thread(struct regcache *regcache)
static void store_sveregs_to_thread(struct regcache *regcache)
static void fetch_fpregs_from_thread(struct regcache *regcache)
static void fetch_pauth_masks_from_thread(struct regcache *regcache)
static void aarch64_store_registers(struct regcache *regcache, int regno)
static void store_tlsregs_to_thread(struct regcache *regcache)
static void fetch_gregs_from_thread(struct regcache *regcache)
void fill_fpregset(const struct regcache *regcache, gdb_fpregset_t *fpregsetp, int regno)
static void aarch32_fetch_registers(struct regcache *regcache, int regno)
const struct regset aarch64_linux_fpregset
const struct regset aarch64_linux_gregset
#define AARCH64_LINUX_SIZEOF_GREGSET
#define AARCH64_HWCAP_PACA
#define AARCH64_LINUX_SIZEOF_FPREGSET
ps_err_e aarch64_ps_get_thread_area(struct ps_prochandle *ph, lwpid_t lwpid, int idx, void **base, int is_64bit_p)
void aarch64_linux_prepare_to_resume(struct lwp_info *lwp)
void aarch64_linux_new_thread(struct lwp_info *lwp)
void aarch64_compat_siginfo_from_siginfo(compat_siginfo_t *to, siginfo_t *from)
void aarch64_siginfo_from_compat_siginfo(siginfo_t *to, compat_siginfo_t *from)
int aarch64_tls_register_count(int tid)
void aarch64_linux_delete_thread(struct arch_lwp_info *arch_lwp)
bool aarch64_mte_store_memtags(int tid, CORE_ADDR address, size_t len, const gdb::byte_vector &tags)
bool aarch64_mte_fetch_memtags(int tid, CORE_ADDR address, size_t len, gdb::byte_vector &tags)
#define HWCAP2_MTE
void aarch64_initialize_hw_point()
struct aarch64_debug_reg_state * aarch64_get_debug_reg_state(pid_t pid)
Definition aarch64-nat.c:51
bool aarch64_stopped_data_address(const struct aarch64_debug_reg_state *state, CORE_ADDR addr_trap, CORE_ADDR *addr_p)
void aarch64_remove_debug_reg_state(pid_t pid)
Definition aarch64-nat.c:59
bool supports_zt_registers(int tid)
void aarch64_sve_regs_copy_from_reg_buf(int tid, struct reg_buffer_common *reg_buf)
void aarch64_za_regs_copy_from_reg_buf(int tid, struct reg_buffer_common *reg_buf, int za_regnum, int svg_regnum, int svcr_regnum)
uint64_t aarch64_za_get_svq(int tid)
void aarch64_zt_regs_copy_from_reg_buf(int tid, struct reg_buffer_common *reg_buf, int zt_regnum)
void aarch64_za_regs_copy_to_reg_buf(int tid, struct reg_buffer_common *reg_buf, int za_regnum, int svg_regnum, int svcr_regnum)
void aarch64_sve_regs_copy_to_reg_buf(int tid, struct reg_buffer_common *reg_buf)
uint64_t aarch64_sve_get_vq(int tid)
void aarch64_zt_regs_copy_to_reg_buf(int tid, struct reg_buffer_common *reg_buf, int zt_regnum)
#define HWCAP2_SME2
#define HWCAP2_SME2P1
aarch64_features aarch64_features_from_target_desc(const struct target_desc *tdesc)
const target_desc * aarch64_read_description(const aarch64_features &features)
#define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base)
Definition aarch64.h:159
@ AARCH64_CPSR_REGNUM
Definition aarch64.h:120
@ AARCH64_SVE_VG_REGNUM
Definition aarch64.h:131
@ AARCH64_V31_REGNUM
Definition aarch64.h:122
@ AARCH64_FPSR_REGNUM
Definition aarch64.h:125
@ AARCH64_FPCR_REGNUM
Definition aarch64.h:126
@ AARCH64_X0_REGNUM
Definition aarch64.h:115
@ AARCH64_V0_REGNUM
Definition aarch64.h:121
#define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base)
Definition aarch64.h:158
gdb_static_assert(sizeof(splay_tree_key) >=sizeof(CORE_ADDR *))
struct gdbarch * target_gdbarch(void)
struct gdbarch * gdbarch_find_by_info(struct gdbarch_info info)
#define ARM_VFP3_REGS_SIZE
Definition arm.h:170
@ ARM_FPSCR_REGNUM
Definition arm.h:64
@ ARM_PS_REGNUM
Definition arm.h:52
@ ARM_D0_REGNUM
Definition arm.h:62
@ ARM_F0_REGNUM
Definition arm.h:48
bool supports_memory_tagging() override
bool low_siginfo_fixup(siginfo_t *ptrace, gdb_byte *inf, int direction) override
void low_new_thread(struct lwp_info *lp) override
void post_startup_inferior(ptid_t) override
void low_forget_process(pid_t pid) override
const struct target_desc * read_description() override
bool stopped_data_address(CORE_ADDR *) override
void low_new_fork(struct lwp_info *parent, pid_t child_pid) override
void low_delete_thread(struct arch_lwp_info *lp) override
void fetch_registers(struct regcache *, int) override
bool stopped_by_watchpoint() override
void store_registers(struct regcache *, int) override
void low_prepare_to_resume(struct lwp_info *lp) override
void post_attach(int pid) override
struct gdbarch * thread_architecture(ptid_t) override
bool store_memtags(CORE_ADDR address, size_t len, const gdb::byte_vector &tags, int type) override
bool fetch_memtags(CORE_ADDR address, size_t len, gdb::byte_vector &tags, int type) override
const target_info & info() const override
Definition inf-child.c:49
void post_startup_inferior(ptid_t) override
Definition linux-nat.c:402
void post_attach(int) override
Definition linux-nat.c:394
gdbarch * arch() const
Definition regcache.c:231
void raw_collect(int regnum, void *buf) const override
Definition regcache.c:1127
void raw_supply(int regnum, const void *buf) override
Definition regcache.c:1062
enum register_status get_register_status(int regnum) const override
Definition regcache.c:304
ptid_t ptid() const
Definition regcache.h:408
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition frame.c:3027
frame_info_ptr get_current_frame(void)
Definition frame.c:1670
#define ptrace(request, pid, addr, data)
Definition gdb_ptrace.h:141
const struct target_desc * gdbarch_target_desc(struct gdbarch *gdbarch)
Definition gdbarch.c:1423
CORE_ADDR gdbarch_remove_non_address_bits(struct gdbarch *gdbarch, CORE_ADDR pointer)
Definition gdbarch.c:3169
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
Definition gdbarch.c:1387
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int int rusage_t pid_t pid
Definition gnu-nat.c:1791
GDB_FPREGSET_T gdb_fpregset_t
Definition gregset.h:35
GDB_GREGSET_T gdb_gregset_t
Definition gregset.h:34
void add_inf_child_target(inf_child_target *target)
Definition inf-child.c:418
pid_t get_ptrace_pid(ptid_t ptid)
Definition inf-ptrace.c:238
ptid_t inferior_ptid
Definition infcmd.c:74
struct inferior * find_inferior_ptid(process_stratum_target *targ, ptid_t ptid)
Definition inferior.c:406
bool linux_nat_get_siginfo(ptid_t ptid, siginfo_t *siginfo)
Definition linux-nat.c:4479
struct linux_nat_target * linux_target
Definition linux-nat.c:189
#define PTRACE_SETREGSET
#define PTRACE_GETREGSET
CORE_ADDR linux_get_hwcap2()
CORE_ADDR linux_get_hwcap()
void regcache_collect_regset(const struct regset *regset, const struct regcache *regcache, int regnum, void *buf, size_t size)
Definition regcache.c:1273
void regcache_supply_regset(const struct regset *regset, struct regcache *regcache, int regnum, const void *buf, size_t size)
Definition regcache.c:1251
uint64_t vq
Definition aarch64.h:34
uint8_t svq
Definition aarch64.h:50
uint8_t tls
Definition aarch64.h:39
bool has_sme2() const
bool has_pauth() const
Definition gnu-nat.c:153
ptid_t ptid
Definition linux-nat.h:211
struct arch_lwp_info * arch_private
Definition linux-nat.h:282
target_ops * beneath() const
Definition target.c:3041
virtual const struct target_desc * read_description() TARGET_DEFAULT_RETURN(NULL)