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nds32-tdep.c
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1/* Target-dependent code for the NDS32 architecture, for GDB.
2
3 Copyright (C) 2013-2023 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22#include "frame.h"
23#include "frame-unwind.h"
24#include "frame-base.h"
25#include "symtab.h"
26#include "gdbtypes.h"
27#include "gdbcore.h"
28#include "value.h"
29#include "reggroups.h"
30#include "inferior.h"
31#include "osabi.h"
32#include "arch-utils.h"
33#include "regcache.h"
34#include "dis-asm.h"
35#include "user-regs.h"
36#include "elf-bfd.h"
37#include "dwarf2/frame.h"
38#include "remote.h"
39#include "target-descriptions.h"
40
41#include "nds32-tdep.h"
42#include "elf/nds32.h"
43#include "opcode/nds32.h"
44#include <algorithm>
45
46#include "features/nds32.c"
47
48/* Simple macros for instruction analysis. */
49#define CHOP_BITS(insn, n) (insn & ~__MASK (n))
50#define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
51#define N32_SMW_ADM \
52 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
53#define N32_LMW_BIM \
54 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
55#define N32_FLDI_SP \
56 N32_TYPE2 (LDC, 0, REG_SP, 0)
57
58/* Use an invalid address value as 'not available' marker. */
59enum { REG_UNAVAIL = (CORE_ADDR) -1 };
60
61/* Use an impossible value as invalid offset. */
62enum { INVALID_OFFSET = (CORE_ADDR) -1 };
63
64/* Instruction groups for NDS32 epilogue analysis. */
65enum
66{
67 /* Instructions used everywhere, not only in epilogue. */
69 /* Instructions used to reset sp for local vars, arguments, etc. */
71 /* Instructions used to recover saved regs and to recover padding. */
73 /* Instructions used to return to the caller. */
75 /* Instructions used to recover saved regs and to return to the caller. */
77};
78
79static const char *const nds32_register_names[] =
80{
81 /* 32 GPRs. */
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
86 /* PC. */
87 "pc",
88};
89
90static const char *const nds32_fdr_register_names[] =
91{
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
96};
97
98static const char *const nds32_fsr_register_names[] =
99{
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
104};
105
106/* The number of registers for four FPU configuration options. */
107const int num_fdr_map[] = { 4, 8, 16, 32 };
108const int num_fsr_map[] = { 8, 16, 32, 32 };
109
110/* Aliases for registers. */
111static const struct
112{
113 const char *name;
114 const char *alias;
116{
117 {"r15", "ta"},
118 {"r26", "p0"},
119 {"r27", "p1"},
120 {"fp", "r28"},
121 {"gp", "r29"},
122 {"lp", "r30"},
123 {"sp", "r31"},
124
125 {"cr0", "cpu_ver"},
126 {"cr1", "icm_cfg"},
127 {"cr2", "dcm_cfg"},
128 {"cr3", "mmu_cfg"},
129 {"cr4", "msc_cfg"},
130 {"cr5", "core_id"},
131 {"cr6", "fucop_exist"},
132 {"cr7", "msc_cfg2"},
133
134 {"ir0", "psw"},
135 {"ir1", "ipsw"},
136 {"ir2", "p_psw"},
137 {"ir3", "ivb"},
138 {"ir4", "eva"},
139 {"ir5", "p_eva"},
140 {"ir6", "itype"},
141 {"ir7", "p_itype"},
142 {"ir8", "merr"},
143 {"ir9", "ipc"},
144 {"ir10", "p_ipc"},
145 {"ir11", "oipc"},
146 {"ir12", "p_p0"},
147 {"ir13", "p_p1"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
150 {"ir16", "sp_usr"},
151 {"ir17", "sp_priv"},
152 {"ir18", "int_pri"},
153 {"ir19", "int_ctrl"},
154 {"ir20", "sp_usr1"},
155 {"ir21", "sp_priv1"},
156 {"ir22", "sp_usr2"},
157 {"ir23", "sp_priv2"},
158 {"ir24", "sp_usr3"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
164
165 {"mr0", "mmu_ctl"},
166 {"mr1", "l1_pptb"},
167 {"mr2", "tlb_vpn"},
168 {"mr3", "tlb_data"},
169 {"mr4", "tlb_misc"},
170 {"mr5", "vlpt_idx"},
171 {"mr6", "ilmb"},
172 {"mr7", "dlmb"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
177
178 {"dr0", "bpc0"},
179 {"dr1", "bpc1"},
180 {"dr2", "bpc2"},
181 {"dr3", "bpc3"},
182 {"dr4", "bpc4"},
183 {"dr5", "bpc5"},
184 {"dr6", "bpc6"},
185 {"dr7", "bpc7"},
186 {"dr8", "bpa0"},
187 {"dr9", "bpa1"},
188 {"dr10", "bpa2"},
189 {"dr11", "bpa3"},
190 {"dr12", "bpa4"},
191 {"dr13", "bpa5"},
192 {"dr14", "bpa6"},
193 {"dr15", "bpa7"},
194 {"dr16", "bpam0"},
195 {"dr17", "bpam1"},
196 {"dr18", "bpam2"},
197 {"dr19", "bpam3"},
198 {"dr20", "bpam4"},
199 {"dr21", "bpam5"},
200 {"dr22", "bpam6"},
201 {"dr23", "bpam7"},
202 {"dr24", "bpv0"},
203 {"dr25", "bpv1"},
204 {"dr26", "bpv2"},
205 {"dr27", "bpv3"},
206 {"dr28", "bpv4"},
207 {"dr29", "bpv5"},
208 {"dr30", "bpv6"},
209 {"dr31", "bpv7"},
210 {"dr32", "bpcid0"},
211 {"dr33", "bpcid1"},
212 {"dr34", "bpcid2"},
213 {"dr35", "bpcid3"},
214 {"dr36", "bpcid4"},
215 {"dr37", "bpcid5"},
216 {"dr38", "bpcid6"},
217 {"dr39", "bpcid7"},
218 {"dr40", "edm_cfg"},
219 {"dr41", "edmsw"},
220 {"dr42", "edm_ctl"},
221 {"dr43", "edm_dtr"},
222 {"dr44", "bpmtc"},
223 {"dr45", "dimbr"},
224 {"dr46", "tecr0"},
225 {"dr47", "tecr1"},
226
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
230
231 {"pfr0", "pfmc0"},
232 {"pfr1", "pfmc1"},
233 {"pfr2", "pfmc2"},
234 {"pfr3", "pfm_ctl"},
235 {"pfr4", "pft_ctl"},
236
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
250
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
253
254 {"idr0", "sdz_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
257
258 {"secur0", "sfcr"},
259 {"secur1", "sign"},
260 {"secur2", "isign"},
261 {"secur3", "p_isign"},
263
264/* Value of a register alias. BATON is the regnum of the corresponding
265 register. */
266
267static struct value *
268value_of_nds32_reg (frame_info_ptr frame, const void *baton)
269{
270 return value_of_register ((int) (intptr_t) baton, frame);
271}
272
273/* Implement the "frame_align" gdbarch method. */
274
275static CORE_ADDR
276nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
277{
278 /* 8-byte aligned. */
279 return align_down (sp, 8);
280}
281
282/* The same insn machine code is used for little-endian and big-endian. */
283constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
284
285typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
286
287/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
288
289static int
290nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
291{
292 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
293 const int FSR = 38;
294 const int FDR = FSR + 32;
295
296 if (num >= 0 && num < 32)
297 {
298 /* General-purpose registers (R0 - R31). */
299 return num;
300 }
301 else if (num >= FSR && num < FSR + 32)
302 {
303 /* Single precision floating-point registers (FS0 - FS31). */
304 return num - FSR + tdep->fs0_regnum;
305 }
306 else if (num >= FDR && num < FDR + 32)
307 {
308 /* Double precision floating-point registers (FD0 - FD31). */
309 return num - FDR + NDS32_FD0_REGNUM;
310 }
311
312 /* No match, return a inaccessible register number. */
313 return -1;
314}
315
316/* NDS32 register groups. */
327
328static void
342
343static void
358
359/* Implement the "register_reggroup_p" gdbarch method. */
360
361static int
363 const struct reggroup *reggroup)
364{
365 const char *reg_name;
366 const char *group_name;
367 int ret;
368
369 if (reggroup == all_reggroup)
370 return 1;
371
372 /* General reggroup contains only GPRs and PC. */
374 return regnum <= NDS32_PC_REGNUM;
375
378 {
380 if (ret != -1)
381 return ret;
382
384 }
385
387 return (regnum > NDS32_PC_REGNUM)
389
390 /* The NDS32 reggroup contains registers whose name is prefixed
391 by reggroup name. */
393 group_name = reggroup->name ();
394 return !strncmp (reg_name, group_name, strlen (group_name));
395}
396
397/* Implement the "pseudo_register_type" tdesc_arch_data method. */
398
399static struct type *
401{
403
404 /* Currently, only FSRs could be defined as pseudo registers. */
406 {
407 type_allocator alloc (gdbarch);
408 return init_float_type (alloc, -1, "builtin_type_ieee_single",
410 }
411
412 warning (_("Unknown nds32 pseudo register %d."), regnum);
413 return NULL;
414}
415
416/* Implement the "pseudo_register_name" tdesc_arch_data method. */
417
418static const char *
420{
422
423 /* Currently, only FSRs could be defined as pseudo registers. */
424 gdb_assert (regnum < gdbarch_num_pseudo_regs (gdbarch));
426}
427
428/* Implement the "pseudo_register_read" gdbarch method. */
429
430static enum register_status
433 gdb_byte *buf)
434{
435 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
436 gdb_byte reg_buf[8];
437 int offset, fdr_regnum;
438 enum register_status status;
439
440 /* This function is registered in nds32_gdbarch_init only after these are
441 set. */
442 gdb_assert (tdep->fpu_freg != -1);
443 gdb_assert (tdep->use_pseudo_fsrs != 0);
444
446
447 /* Currently, only FSRs could be defined as pseudo registers. */
449 {
450 /* fs0 is always the most significant half of fd0. */
451 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
452 offset = (regnum & 1) ? 4 : 0;
453 else
454 offset = (regnum & 1) ? 0 : 4;
455
456 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
457 status = regcache->raw_read (fdr_regnum, reg_buf);
458 if (status == REG_VALID)
459 memcpy (buf, reg_buf + offset, 4);
460
461 return status;
462 }
463
464 gdb_assert_not_reached ("invalid pseudo register number");
465}
466
467/* Implement the "pseudo_register_write" gdbarch method. */
468
469static void
471 struct regcache *regcache, int regnum,
472 const gdb_byte *buf)
473{
474 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
475 gdb_byte reg_buf[8];
476 int offset, fdr_regnum;
477
478 /* This function is registered in nds32_gdbarch_init only after these are
479 set. */
480 gdb_assert (tdep->fpu_freg != -1);
481 gdb_assert (tdep->use_pseudo_fsrs != 0);
482
484
485 /* Currently, only FSRs could be defined as pseudo registers. */
487 {
488 /* fs0 is always the most significant half of fd0. */
489 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
490 offset = (regnum & 1) ? 4 : 0;
491 else
492 offset = (regnum & 1) ? 0 : 4;
493
494 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
495 regcache->raw_read (fdr_regnum, reg_buf);
496 memcpy (reg_buf + offset, buf, 4);
497 regcache->raw_write (fdr_regnum, reg_buf);
498 return;
499 }
500
501 gdb_assert_not_reached ("invalid pseudo register number");
502}
503
504/* Helper function for NDS32 ABI. Return true if FPRs can be used
505 to pass function arguments and return value. */
506
507static int
508nds32_abi_use_fpr (int elf_abi)
509{
510 return elf_abi == E_NDS_ABI_V2FP_PLUS;
511}
512
513/* Helper function for NDS32 ABI. Return true if GPRs and stack
514 can be used together to pass an argument. */
515
516static int
517nds32_abi_split (int elf_abi)
518{
519 return elf_abi == E_NDS_ABI_AABI;
520}
521
522#define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
523
525{
526 /* The previous frame's inner most stack address. Used as this
527 frame ID's stack_addr. */
528 CORE_ADDR prev_sp;
529
530 /* The frame's base, optionally used by the high-level debug info. */
531 CORE_ADDR base;
532
533 /* During prologue analysis, keep how far the SP and FP have been offset
534 from the start of the stack frame (as defined by the previous frame's
535 stack pointer).
536 During epilogue analysis, keep how far the SP has been offset from the
537 current stack pointer. */
538 CORE_ADDR sp_offset;
539 CORE_ADDR fp_offset;
540
541 /* The address of the first instruction in this function. */
542 CORE_ADDR pc;
543
544 /* Saved registers. */
546};
547
548/* Allocate and initialize a frame cache. */
549
550static struct nds32_frame_cache *
552{
553 struct nds32_frame_cache *cache;
554 int i;
555
557
558 /* Initialize fp_offset to check if FP is set in prologue. */
559 cache->fp_offset = INVALID_OFFSET;
560
561 /* Saved registers. We initialize these to -1 since zero is a valid
562 offset. */
563 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
564 cache->saved_regs[i] = REG_UNAVAIL;
565
566 return cache;
567}
568
569/* Helper function for instructions used to push multiple words. */
570
571static void
572nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
573 int enable4)
574{
575 CORE_ADDR sp_offset = cache->sp_offset;
576 int i;
577
578 /* Check LP, GP, FP in enable4. */
579 for (i = 1; i <= 3; i++)
580 {
581 if ((enable4 >> i) & 0x1)
582 {
583 sp_offset += 4;
585 }
586 }
587
588 /* Skip case where re == rb == sp. */
589 if ((rb < REG_FP) && (re < REG_FP))
590 {
591 for (i = re; i >= rb; i--)
592 {
593 sp_offset += 4;
594 cache->saved_regs[i] = sp_offset;
595 }
596 }
597
598 /* For sp, update the offset. */
599 cache->sp_offset = sp_offset;
600}
601
602/* Analyze the instructions within the given address range. If CACHE
603 is non-NULL, fill it in. Return the first address beyond the given
604 address range. If CACHE is NULL, return the first address not
605 recognized as a prologue instruction. */
606
607static CORE_ADDR
609 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
610{
611 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
612 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
613 /* Current scanning status. */
614 int in_prologue_bb = 0;
615 int val_ta = 0;
616 uint32_t insn, insn_len;
617
618 for (; pc < limit_pc; pc += insn_len)
619 {
620 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
621
622 if ((insn & 0x80000000) == 0)
623 {
624 /* 32-bit instruction */
625 insn_len = 4;
626
627 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
628 {
629 /* addi $sp, $sp, imm15s */
630 int imm15s = N32_IMM15S (insn);
631
632 if (imm15s < 0)
633 {
634 if (cache != NULL)
635 cache->sp_offset += -imm15s;
636
637 in_prologue_bb = 1;
638 continue;
639 }
640 }
641 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
642 {
643 /* addi $fp, $sp, imm15s */
644 int imm15s = N32_IMM15S (insn);
645
646 if (imm15s > 0)
647 {
648 if (cache != NULL)
649 cache->fp_offset = cache->sp_offset - imm15s;
650
651 in_prologue_bb = 1;
652 continue;
653 }
654 }
655 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
656 && N32_RA5 (insn) == REG_SP)
657 {
658 /* smw.adm Rb, [$sp], Re, enable4 */
659 if (cache != NULL)
660 nds32_push_multiple_words (cache, N32_RT5 (insn),
661 N32_RB5 (insn),
662 N32_LSMW_ENABLE4 (insn));
663 in_prologue_bb = 1;
664 continue;
665 }
666 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
667 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
668 {
669 /* add $sp, $sp, $ta */
670 /* add $sp, $ta, $sp */
671 if (val_ta < 0)
672 {
673 if (cache != NULL)
674 cache->sp_offset += -val_ta;
675
676 in_prologue_bb = 1;
677 continue;
678 }
679 }
680 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
681 {
682 /* movi $ta, imm20s */
683 if (cache != NULL)
684 val_ta = N32_IMM20S (insn);
685
686 continue;
687 }
688 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
689 {
690 /* sethi $ta, imm20u */
691 if (cache != NULL)
692 val_ta = N32_IMM20U (insn) << 12;
693
694 continue;
695 }
696 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
697 {
698 /* ori $ta, $ta, imm15u */
699 if (cache != NULL)
700 val_ta |= N32_IMM15U (insn);
701
702 continue;
703 }
704 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
705 {
706 /* addi $ta, $ta, imm15s */
707 if (cache != NULL)
708 val_ta += N32_IMM15S (insn);
709
710 continue;
711 }
712 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
713 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
714 {
715 /* add $gp, $ta, $gp */
716 /* add $gp, $gp, $ta */
717 in_prologue_bb = 1;
718 continue;
719 }
720 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
721 {
722 /* movi $gp, imm20s */
723 in_prologue_bb = 1;
724 continue;
725 }
726 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
727 {
728 /* sethi $gp, imm20u */
729 in_prologue_bb = 1;
730 continue;
731 }
732 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
733 {
734 /* ori $gp, $gp, imm15u */
735 in_prologue_bb = 1;
736 continue;
737 }
738 else
739 {
740 /* Jump/Branch insns never appear in prologue basic block.
741 The loop can be escaped early when these insns are met. */
742 if (in_prologue_bb == 1)
743 {
744 int op = N32_OP6 (insn);
745
746 if (op == N32_OP6_JI
747 || op == N32_OP6_JREG
748 || op == N32_OP6_BR1
749 || op == N32_OP6_BR2
750 || op == N32_OP6_BR3)
751 break;
752 }
753 }
754
755 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
756 && __GF (insn, 12, 3) == 0)
757 {
758 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
759 normal form (bit [12] == 0) is used. */
760
761 /* fsdi FDt, [$sp + (imm12s << 2)] */
762 if (N32_RA5 (insn) == REG_SP)
763 continue;
764 }
765
766 /* The optimizer might shove anything into the prologue, if
767 we build up cache (cache != NULL) from analyzing prologue,
768 we just skip what we don't recognize and analyze further to
769 make cache as complete as possible. However, if we skip
770 prologue, we'll stop immediately on unrecognized
771 instruction. */
772 if (cache == NULL)
773 break;
774 }
775 else
776 {
777 /* 16-bit instruction */
778 insn_len = 2;
779
780 insn >>= 16;
781
782 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
783 {
784 /* addi10s.sp */
785 int imm10s = N16_IMM10S (insn);
786
787 if (imm10s < 0)
788 {
789 if (cache != NULL)
790 cache->sp_offset += -imm10s;
791
792 in_prologue_bb = 1;
793 continue;
794 }
795 }
796 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
797 {
798 /* push25 */
799 if (cache != NULL)
800 {
801 int imm8u = (insn & 0x1f) << 3;
802 int re = (insn >> 5) & 0x3;
803 const int reg_map[] = { 6, 8, 10, 14 };
804
805 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
806 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
807
808 /* Operation 2 -- sp = sp - (imm5u << 3) */
809 cache->sp_offset += imm8u;
810 }
811
812 in_prologue_bb = 1;
813 continue;
814 }
815 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
816 {
817 /* add5.pc $gp */
818 in_prologue_bb = 1;
819 continue;
820 }
821 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
822 {
823 /* movi55 $gp, imm5s */
824 in_prologue_bb = 1;
825 continue;
826 }
827 else
828 {
829 /* Jump/Branch insns never appear in prologue basic block.
830 The loop can be escaped early when these insns are met. */
831 if (in_prologue_bb == 1)
832 {
833 uint32_t insn5 = CHOP_BITS (insn, 5);
834 uint32_t insn8 = CHOP_BITS (insn, 8);
835 uint32_t insn38 = CHOP_BITS (insn, 11);
836
837 if (insn5 == N16_TYPE5 (JR5, 0)
838 || insn5 == N16_TYPE5 (JRAL5, 0)
839 || insn5 == N16_TYPE5 (RET5, 0)
840 || insn8 == N16_TYPE8 (J8, 0)
841 || insn8 == N16_TYPE8 (BEQZS8, 0)
842 || insn8 == N16_TYPE8 (BNEZS8, 0)
843 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
844 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
845 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
846 || insn38 == N16_TYPE38 (BNES38, 0, 0))
847 break;
848 }
849 }
850
851 /* The optimizer might shove anything into the prologue, if
852 we build up cache (cache != NULL) from analyzing prologue,
853 we just skip what we don't recognize and analyze further to
854 make cache as complete as possible. However, if we skip
855 prologue, we'll stop immediately on unrecognized
856 instruction. */
857 if (cache == NULL)
858 break;
859 }
860 }
861
862 return pc;
863}
864
865/* Implement the "skip_prologue" gdbarch method.
866
867 Find the end of function prologue. */
868
869static CORE_ADDR
871{
872 CORE_ADDR func_addr, limit_pc;
873
874 /* See if we can determine the end of the prologue via the symbol table.
875 If so, then return either PC, or the PC after the prologue, whichever
876 is greater. */
877 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
878 {
879 CORE_ADDR post_prologue_pc
880 = skip_prologue_using_sal (gdbarch, func_addr);
881 if (post_prologue_pc != 0)
882 return std::max (pc, post_prologue_pc);
883 }
884
885 /* Can't determine prologue from the symbol table, need to examine
886 instructions. */
887
888 /* Find an upper limit on the function prologue using the debug
889 information. If the debug information could not be used to provide
890 that bound, then use an arbitrary large number as the upper bound. */
891 limit_pc = skip_prologue_using_sal (gdbarch, pc);
892 if (limit_pc == 0)
893 limit_pc = pc + 128; /* Magic. */
894
895 /* Find the end of prologue. */
896 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
897}
898
899/* Allocate and fill in *THIS_CACHE with information about the prologue of
900 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
901 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
902
903static struct nds32_frame_cache *
904nds32_frame_cache (frame_info_ptr this_frame, void **this_cache)
905{
906 struct gdbarch *gdbarch = get_frame_arch (this_frame);
907 struct nds32_frame_cache *cache;
908 CORE_ADDR current_pc;
909 ULONGEST prev_sp;
910 ULONGEST this_base;
911 int i;
912
913 if (*this_cache)
914 return (struct nds32_frame_cache *) *this_cache;
915
916 cache = nds32_alloc_frame_cache ();
917 *this_cache = cache;
918
919 cache->pc = get_frame_func (this_frame);
920 current_pc = get_frame_pc (this_frame);
921 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
922
923 /* Compute the previous frame's stack pointer (which is also the
924 frame's ID's stack address), and this frame's base pointer. */
925 if (cache->fp_offset != INVALID_OFFSET)
926 {
927 /* FP is set in prologue, so it can be used to calculate other info. */
928 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
929 prev_sp = this_base + cache->fp_offset;
930 }
931 else
932 {
933 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
934 prev_sp = this_base + cache->sp_offset;
935 }
936
937 cache->prev_sp = prev_sp;
938 cache->base = this_base;
939
940 /* Adjust all the saved registers such that they contain addresses
941 instead of offsets. */
942 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
943 if (cache->saved_regs[i] != REG_UNAVAIL)
944 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
945
946 return cache;
947}
948
949/* Implement the "this_id" frame_unwind method.
950
951 Our frame ID for a normal frame is the current function's starting
952 PC and the caller's SP when we were called. */
953
954static void
956 void **this_cache, struct frame_id *this_id)
957{
958 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
959
960 /* This marks the outermost frame. */
961 if (cache->prev_sp == 0)
962 return;
963
964 *this_id = frame_id_build (cache->prev_sp, cache->pc);
965}
966
967/* Implement the "prev_register" frame_unwind method. */
968
969static struct value *
970nds32_frame_prev_register (frame_info_ptr this_frame, void **this_cache,
971 int regnum)
972{
973 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
974
975 if (regnum == NDS32_SP_REGNUM)
976 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
977
978 /* The PC of the previous frame is stored in the LP register of
979 the current frame. */
980 if (regnum == NDS32_PC_REGNUM)
982
983 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
984 return frame_unwind_got_memory (this_frame, regnum,
985 cache->saved_regs[regnum]);
986
987 return frame_unwind_got_register (this_frame, regnum, regnum);
988}
989
990static const struct frame_unwind nds32_frame_unwind =
991{
992 "nds32 prologue",
997 NULL,
999};
1000
1001/* Return the frame base address of *THIS_FRAME. */
1002
1003static CORE_ADDR
1004nds32_frame_base_address (frame_info_ptr this_frame, void **this_cache)
1005{
1006 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1007
1008 return cache->base;
1009}
1010
1018
1019/* Helper function for instructions used to pop multiple words. */
1020
1021static void
1022nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1023 int enable4)
1024{
1025 CORE_ADDR sp_offset = cache->sp_offset;
1026 int i;
1027
1028 /* Skip case where re == rb == sp. */
1029 if ((rb < REG_FP) && (re < REG_FP))
1030 {
1031 for (i = rb; i <= re; i++)
1032 {
1033 cache->saved_regs[i] = sp_offset;
1034 sp_offset += 4;
1035 }
1036 }
1037
1038 /* Check FP, GP, LP in enable4. */
1039 for (i = 3; i >= 1; i--)
1040 {
1041 if ((enable4 >> i) & 0x1)
1042 {
1043 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1044 sp_offset += 4;
1045 }
1046 }
1047
1048 /* For sp, update the offset. */
1049 cache->sp_offset = sp_offset;
1050}
1051
1052/* The instruction sequences in NDS32 epilogue are
1053
1054 INSN_RESET_SP (optional)
1055 (If exists, this must be the first instruction in epilogue
1056 and the stack has not been destroyed.).
1057 INSN_RECOVER (optional).
1058 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1059
1060/* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1061 the necessary information will be recorded. */
1062
1063static inline int
1064nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1065 struct nds32_frame_cache *cache)
1066{
1067 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1068 && N32_IMM15S (insn) > 0)
1069 /* addi $sp, $sp, imm15s */
1070 return INSN_RESET_SP;
1071 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1072 && N32_IMM15S (insn) < 0)
1073 /* addi $sp, $fp, imm15s */
1074 return INSN_RESET_SP;
1075 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1076 && N32_RA5 (insn) == REG_SP)
1077 {
1078 /* lmw.bim Rb, [$sp], Re, enable4 */
1079 if (cache != NULL)
1080 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1081 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1082
1083 return INSN_RECOVER;
1084 }
1085 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1086 /* ret $lp */
1087 return INSN_RETURN;
1088 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1089 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1090 /* add $sp, $sp, $ta */
1091 /* add $sp, $ta, $sp */
1092 return INSN_RESET_SP;
1093 else if (abi_use_fpr
1094 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1095 {
1096 if (__GF (insn, 12, 1) == 0)
1097 /* fldi FDt, [$sp + (imm12s << 2)] */
1098 return INSN_RECOVER;
1099 else
1100 {
1101 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1102 int offset = N32_IMM12S (insn) << 2;
1103
1104 if (offset == 8 || offset == 12)
1105 {
1106 if (cache != NULL)
1107 cache->sp_offset += offset;
1108
1109 return INSN_RECOVER;
1110 }
1111 }
1112 }
1113
1114 return INSN_NORMAL;
1115}
1116
1117/* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1118 the necessary information will be recorded. */
1119
1120static inline int
1122{
1123 if (insn == N16_TYPE5 (RET5, REG_LP))
1124 /* ret5 $lp */
1125 return INSN_RETURN;
1126 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1127 {
1128 /* addi10s.sp */
1129 int imm10s = N16_IMM10S (insn);
1130
1131 if (imm10s > 0)
1132 {
1133 if (cache != NULL)
1134 cache->sp_offset += imm10s;
1135
1136 return INSN_RECOVER;
1137 }
1138 }
1139 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1140 {
1141 /* pop25 */
1142 if (cache != NULL)
1143 {
1144 int imm8u = (insn & 0x1f) << 3;
1145 int re = (insn >> 5) & 0x3;
1146 const int reg_map[] = { 6, 8, 10, 14 };
1147
1148 /* Operation 1 -- sp = sp + (imm5u << 3) */
1149 cache->sp_offset += imm8u;
1150
1151 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1152 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1153 }
1154
1155 /* Operation 3 -- ret $lp */
1156 return INSN_RECOVER_RETURN;
1157 }
1158
1159 return INSN_NORMAL;
1160}
1161
1162/* Analyze a reasonable amount of instructions from the given PC to find
1163 the instruction used to return to the caller. Return 1 if the 'return'
1164 instruction could be found, 0 otherwise.
1165
1166 If CACHE is non-NULL, fill it in. */
1167
1168static int
1170 struct nds32_frame_cache *cache)
1171{
1172 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1173 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1174 CORE_ADDR limit_pc;
1175 uint32_t insn, insn_len;
1176 int insn_type = INSN_NORMAL;
1177
1178 if (abi_use_fpr)
1179 limit_pc = pc + 48;
1180 else
1181 limit_pc = pc + 16;
1182
1183 for (; pc < limit_pc; pc += insn_len)
1184 {
1185 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1186
1187 if ((insn & 0x80000000) == 0)
1188 {
1189 /* 32-bit instruction */
1190 insn_len = 4;
1191
1192 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1193 if (insn_type == INSN_RETURN)
1194 return 1;
1195 else if (insn_type == INSN_RECOVER)
1196 continue;
1197 }
1198 else
1199 {
1200 /* 16-bit instruction */
1201 insn_len = 2;
1202
1203 insn >>= 16;
1204 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1205 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1206 return 1;
1207 else if (insn_type == INSN_RECOVER)
1208 continue;
1209 }
1210
1211 /* Stop the scan if this is an unexpected instruction. */
1212 break;
1213 }
1214
1215 return 0;
1216}
1217
1218/* Implement the "stack_frame_destroyed_p" gdbarch method. */
1219
1220static int
1222{
1223 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1224 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1225 int insn_type = INSN_NORMAL;
1226 int ret_found = 0;
1227 uint32_t insn;
1228
1229 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1230
1231 if ((insn & 0x80000000) == 0)
1232 {
1233 /* 32-bit instruction */
1234
1235 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1236 }
1237 else
1238 {
1239 /* 16-bit instruction */
1240
1241 insn >>= 16;
1242 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1243 }
1244
1245 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1246 return 0;
1247
1248 /* Search the required 'return' instruction within the following reasonable
1249 instructions. */
1250 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1251 if (ret_found == 0)
1252 return 0;
1253
1254 /* Scan backwards to make sure that the last instruction has adjusted
1255 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1256 just a heuristic, so the false positives will be acceptable. */
1257 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1258
1259 /* Only 16-bit instructions are possible at addr - 2. */
1260 if ((insn & 0x80000000) != 0)
1261 {
1262 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1263
1264 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1265 if (insn_type == INSN_RECOVER)
1266 return 1;
1267 }
1268
1269 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1270
1271 /* If this is a 16-bit instruction at addr - 4, then there must be another
1272 16-bit instruction at addr - 2, so only 32-bit instructions need to
1273 be analyzed here. */
1274 if ((insn & 0x80000000) == 0)
1275 {
1276 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1277
1278 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1279 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1280 return 1;
1281 }
1282
1283 return 0;
1284}
1285
1286/* Implement the "sniffer" frame_unwind method. */
1287
1288static int
1290 frame_info_ptr this_frame, void **this_cache)
1291{
1292 if (frame_relative_level (this_frame) == 0)
1293 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1294 get_frame_pc (this_frame));
1295 else
1296 return 0;
1297}
1298
1299/* Allocate and fill in *THIS_CACHE with information needed to unwind
1300 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1301 allocated. Return a pointer to the current nds32_frame_cache in
1302 *THIS_CACHE. */
1303
1304static struct nds32_frame_cache *
1305nds32_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache)
1306{
1307 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1308 struct nds32_frame_cache *cache;
1309 CORE_ADDR current_pc, current_sp;
1310 int i;
1311
1312 if (*this_cache)
1313 return (struct nds32_frame_cache *) *this_cache;
1314
1315 cache = nds32_alloc_frame_cache ();
1316 *this_cache = cache;
1317
1318 cache->pc = get_frame_func (this_frame);
1319 current_pc = get_frame_pc (this_frame);
1320 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1321
1322 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1323 cache->prev_sp = current_sp + cache->sp_offset;
1324
1325 /* Adjust all the saved registers such that they contain addresses
1326 instead of offsets. */
1327 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1328 if (cache->saved_regs[i] != REG_UNAVAIL)
1329 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1330
1331 return cache;
1332}
1333
1334/* Implement the "this_id" frame_unwind method. */
1335
1336static void
1338 void **this_cache, struct frame_id *this_id)
1339{
1340 struct nds32_frame_cache *cache
1341 = nds32_epilogue_frame_cache (this_frame, this_cache);
1342
1343 /* This marks the outermost frame. */
1344 if (cache->prev_sp == 0)
1345 return;
1346
1347 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1348}
1349
1350/* Implement the "prev_register" frame_unwind method. */
1351
1352static struct value *
1354 void **this_cache, int regnum)
1355{
1356 struct nds32_frame_cache *cache
1357 = nds32_epilogue_frame_cache (this_frame, this_cache);
1358
1359 if (regnum == NDS32_SP_REGNUM)
1360 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1361
1362 /* The PC of the previous frame is stored in the LP register of
1363 the current frame. */
1364 if (regnum == NDS32_PC_REGNUM)
1366
1367 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1368 return frame_unwind_got_memory (this_frame, regnum,
1369 cache->saved_regs[regnum]);
1370
1371 return frame_unwind_got_register (this_frame, regnum, regnum);
1372}
1373
1384
1385
1386/* Floating type and struct type that has only one floating type member
1387 can pass value using FPU registers (when FPU ABI is used). */
1388
1389static int
1391{
1392 struct type *t;
1393 enum type_code typecode;
1394
1395 t = type;
1396 while (1)
1397 {
1398 t = check_typedef (t);
1399 typecode = t->code ();
1400 if (typecode != TYPE_CODE_STRUCT)
1401 break;
1402 else if (t->num_fields () != 1)
1403 return 0;
1404 else
1405 t = t->field (0).type ();
1406 }
1407
1408 return typecode == TYPE_CODE_FLT;
1409}
1410
1411/* Implement the "push_dummy_call" gdbarch method. */
1412
1413static CORE_ADDR
1414nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1415 struct regcache *regcache, CORE_ADDR bp_addr,
1416 int nargs, struct value **args, CORE_ADDR sp,
1417 function_call_return_method return_method,
1418 CORE_ADDR struct_addr)
1419{
1420 const int REND = 6; /* End for register offset. */
1421 int goff = 0; /* Current gpr offset for argument. */
1422 int foff = 0; /* Current fpr offset for argument. */
1423 int soff = 0; /* Current stack offset for argument. */
1424 int i;
1425 ULONGEST regval;
1426 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1427 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1428 struct type *func_type = function->type ();
1429 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1430 int abi_split = nds32_abi_split (tdep->elf_abi);
1431
1432 /* Set the return address. For the NDS32, the return breakpoint is
1433 always at BP_ADDR. */
1435
1436 /* If STRUCT_RETURN is true, then the struct return address (in
1437 STRUCT_ADDR) will consume the first argument-passing register.
1438 Both adjust the register count and store that value. */
1439 if (return_method == return_method_struct)
1440 {
1442 goff++;
1443 }
1444
1445 /* Now make sure there's space on the stack */
1446 for (i = 0; i < nargs; i++)
1447 {
1448 struct type *type = args[i]->type ();
1449 int align = type_align (type);
1450
1451 /* If align is zero, it may be an empty struct.
1452 Just ignore the argument of empty struct. */
1453 if (align == 0)
1454 continue;
1455
1456 sp -= type->length ();
1457 sp = align_down (sp, align);
1458 }
1459
1460 /* Stack must be 8-byte aligned. */
1461 sp = align_down (sp, 8);
1462
1463 soff = 0;
1464 for (i = 0; i < nargs; i++)
1465 {
1466 const gdb_byte *val;
1467 int align, len;
1468 struct type *type;
1469 int calling_use_fpr;
1470 int use_fpr = 0;
1471
1472 type = args[i]->type ();
1473 calling_use_fpr = nds32_check_calling_use_fpr (type);
1474 len = type->length ();
1475 align = type_align (type);
1476 val = args[i]->contents ().data ();
1477
1478 /* The size of a composite type larger than 4 bytes will be rounded
1479 up to the nearest multiple of 4. */
1480 if (len > 4)
1481 len = align_up (len, 4);
1482
1483 /* Variadic functions are handled differently between AABI and ABI2FP+.
1484
1485 For AABI, the caller pushes arguments in registers, callee stores
1486 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1487 Therefore, we don't have to handle variadic functions specially.
1488
1489 For ABI2FP+, the caller pushes only named arguments in registers
1490 and pushes all unnamed arguments in stack. */
1491
1492 if (abi_use_fpr && func_type->has_varargs ()
1493 && i >= func_type->num_fields ())
1494 goto use_stack;
1495
1496 /* Try to use FPRs to pass arguments only when
1497 1. The program is built using toolchain with FPU support.
1498 2. The type of this argument can use FPR to pass value. */
1499 use_fpr = abi_use_fpr && calling_use_fpr;
1500
1501 if (use_fpr)
1502 {
1503 if (tdep->fpu_freg == -1)
1504 goto error_no_fpr;
1505
1506 /* Adjust alignment. */
1507 if ((align >> 2) > 0)
1508 foff = align_up (foff, align >> 2);
1509
1510 if (foff < REND)
1511 {
1512 switch (len)
1513 {
1514 case 4:
1515 regcache->cooked_write (tdep->fs0_regnum + foff, val);
1516 foff++;
1517 break;
1518 case 8:
1519 regcache->cooked_write (NDS32_FD0_REGNUM + (foff >> 1), val);
1520 foff += 2;
1521 break;
1522 default:
1523 /* Long double? */
1524 internal_error ("Do not know how to handle %d-byte double.\n",
1525 len);
1526 break;
1527 }
1528 continue;
1529 }
1530 }
1531 else
1532 {
1533 /*
1534 When passing arguments using GPRs,
1535
1536 * A composite type not larger than 4 bytes is passed in $rN.
1537 The format is as if the value is loaded with load instruction
1538 of corresponding size (e.g., LB, LH, LW).
1539
1540 For example,
1541
1542 r0
1543 31 0
1544 LITTLE: [x x b a]
1545 BIG: [x x a b]
1546
1547 * Otherwise, a composite type is passed in consecutive registers.
1548 The size is rounded up to the nearest multiple of 4.
1549 The successive registers hold the parts of the argument as if
1550 were loaded using lmw instructions.
1551
1552 For example,
1553
1554 r0 r1
1555 31 0 31 0
1556 LITTLE: [d c b a] [x x x e]
1557 BIG: [a b c d] [e x x x]
1558 */
1559
1560 /* Adjust alignment. */
1561 if ((align >> 2) > 0)
1562 goff = align_up (goff, align >> 2);
1563
1564 if (len <= (REND - goff) * 4)
1565 {
1566 /* This argument can be passed wholly via GPRs. */
1567 while (len > 0)
1568 {
1569 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1570 byte_order);
1572 NDS32_R0_REGNUM + goff,
1573 regval);
1574 len -= 4;
1575 val += 4;
1576 goff++;
1577 }
1578 continue;
1579 }
1580 else if (abi_split)
1581 {
1582 /* Some parts of this argument can be passed via GPRs. */
1583 while (goff < REND)
1584 {
1585 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1586 byte_order);
1588 NDS32_R0_REGNUM + goff,
1589 regval);
1590 len -= 4;
1591 val += 4;
1592 goff++;
1593 }
1594 }
1595 }
1596
1597use_stack:
1598 /*
1599 When pushing (split parts of) an argument into stack,
1600
1601 * A composite type not larger than 4 bytes is copied to different
1602 base address.
1603 In little-endian, the first byte of this argument is aligned
1604 at the low address of the next free word.
1605 In big-endian, the last byte of this argument is aligned
1606 at the high address of the next free word.
1607
1608 For example,
1609
1610 sp [ - ] [ c ] hi
1611 [ c ] [ b ]
1612 [ b ] [ a ]
1613 [ a ] [ - ] lo
1614 LITTLE BIG
1615 */
1616
1617 /* Adjust alignment. */
1618 soff = align_up (soff, align);
1619
1620 while (len > 0)
1621 {
1622 int rlen = (len > 4) ? 4 : len;
1623
1624 if (byte_order == BFD_ENDIAN_BIG)
1625 write_memory (sp + soff + 4 - rlen, val, rlen);
1626 else
1627 write_memory (sp + soff, val, rlen);
1628
1629 len -= 4;
1630 val += 4;
1631 soff += 4;
1632 }
1633 }
1634
1635 /* Finally, update the SP register. */
1637
1638 return sp;
1639
1640error_no_fpr:
1641 /* If use_fpr, but no floating-point register exists,
1642 then it is an error. */
1643 error (_("Fail to call. FPU registers are required."));
1644}
1645
1646/* Read, for architecture GDBARCH, a function return value of TYPE
1647 from REGCACHE, and copy that into VALBUF. */
1648
1649static void
1651 struct regcache *regcache, gdb_byte *valbuf)
1652{
1653 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1654 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1655 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1656 int calling_use_fpr;
1657 int len;
1658
1659 calling_use_fpr = nds32_check_calling_use_fpr (type);
1660 len = type->length ();
1661
1662 if (abi_use_fpr && calling_use_fpr)
1663 {
1664 if (len == 4)
1665 regcache->cooked_read (tdep->fs0_regnum, valbuf);
1666 else if (len == 8)
1668 else
1669 internal_error (_("Cannot extract return value of %d bytes "
1670 "long floating-point."), len);
1671 }
1672 else
1673 {
1674 /*
1675 When returning result,
1676
1677 * A composite type not larger than 4 bytes is returned in $r0.
1678 The format is as if the result is loaded with load instruction
1679 of corresponding size (e.g., LB, LH, LW).
1680
1681 For example,
1682
1683 r0
1684 31 0
1685 LITTLE: [x x b a]
1686 BIG: [x x a b]
1687
1688 * Otherwise, a composite type not larger than 8 bytes is returned
1689 in $r0 and $r1.
1690 In little-endian, the first word is loaded in $r0.
1691 In big-endian, the last word is loaded in $r1.
1692
1693 For example,
1694
1695 r0 r1
1696 31 0 31 0
1697 LITTLE: [d c b a] [x x x e]
1698 BIG: [x x x a] [b c d e]
1699 */
1700
1701 ULONGEST tmp;
1702
1703 if (len < 4)
1704 {
1705 /* By using store_unsigned_integer we avoid having to do
1706 anything special for small big-endian values. */
1708 store_unsigned_integer (valbuf, len, byte_order, tmp);
1709 }
1710 else if (len == 4)
1711 {
1713 }
1714 else if (len < 8)
1715 {
1716 int len1, len2;
1717
1718 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1719 len2 = len - len1;
1720
1722 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1723
1725 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1726 }
1727 else
1728 {
1730 regcache->cooked_read (NDS32_R0_REGNUM + 1, valbuf + 4);
1731 }
1732 }
1733}
1734
1735/* Write, for architecture GDBARCH, a function return value of TYPE
1736 from VALBUF into REGCACHE. */
1737
1738static void
1740 struct regcache *regcache, const gdb_byte *valbuf)
1741{
1742 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1743 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1744 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1745 int calling_use_fpr;
1746 int len;
1747
1748 calling_use_fpr = nds32_check_calling_use_fpr (type);
1749 len = type->length ();
1750
1751 if (abi_use_fpr && calling_use_fpr)
1752 {
1753 if (len == 4)
1754 regcache->cooked_write (tdep->fs0_regnum, valbuf);
1755 else if (len == 8)
1757 else
1758 internal_error (_("Cannot store return value of %d bytes "
1759 "long floating-point."), len);
1760 }
1761 else
1762 {
1763 ULONGEST regval;
1764
1765 if (len < 4)
1766 {
1767 regval = extract_unsigned_integer (valbuf, len, byte_order);
1769 }
1770 else if (len == 4)
1771 {
1773 }
1774 else if (len < 8)
1775 {
1776 int len1, len2;
1777
1778 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1779 len2 = len - len1;
1780
1781 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1783
1784 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1786 regval);
1787 }
1788 else
1789 {
1791 regcache->cooked_write (NDS32_R0_REGNUM + 1, valbuf + 4);
1792 }
1793 }
1794}
1795
1796/* Implement the "return_value" gdbarch method.
1797
1798 Determine, for architecture GDBARCH, how a return value of TYPE
1799 should be returned. If it is supposed to be returned in registers,
1800 and READBUF is non-zero, read the appropriate value from REGCACHE,
1801 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1802 from WRITEBUF into REGCACHE. */
1803
1804static enum return_value_convention
1806 struct type *type, struct regcache *regcache,
1807 gdb_byte *readbuf, const gdb_byte *writebuf)
1808{
1809 if (type->length () > 8)
1810 {
1812 }
1813 else
1814 {
1815 if (readbuf != NULL)
1817 if (writebuf != NULL)
1819
1821 }
1822}
1823
1824/* Implement the "get_longjmp_target" gdbarch method. */
1825
1826static int
1828{
1829 gdb_byte buf[4];
1830 CORE_ADDR jb_addr;
1831 struct gdbarch *gdbarch = get_frame_arch (frame);
1832 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1833
1835
1836 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1837 return 0;
1838
1839 *pc = extract_unsigned_integer (buf, 4, byte_order);
1840 return 1;
1841}
1842
1843/* Validate the given TDESC, and fixed-number some registers in it.
1844 Return 0 if the given TDESC does not contain the required feature
1845 or not contain required registers. */
1846
1847static int
1850 int *fpu_freg, int *use_pseudo_fsrs)
1851{
1852 const struct tdesc_feature *feature;
1853 int i, valid_p;
1854
1855 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1856 if (feature == NULL)
1857 return 0;
1858
1859 valid_p = 1;
1860 /* Validate and fixed-number R0-R10. */
1861 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1862 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1864
1865 /* Validate R15. */
1866 valid_p &= tdesc_unnumbered_register (feature,
1868
1869 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1870 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1871 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1873
1874 if (!valid_p)
1875 return 0;
1876
1877 /* Fixed-number R11-R27. */
1878 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1880
1881 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1882 if (feature != NULL)
1883 {
1884 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1885 int freg = -1;
1886
1887 /* Guess FPU configuration via listed registers. */
1888 if (tdesc_unnumbered_register (feature, "fd31"))
1889 freg = 3;
1890 else if (tdesc_unnumbered_register (feature, "fd15"))
1891 freg = 2;
1892 else if (tdesc_unnumbered_register (feature, "fd7"))
1893 freg = 1;
1894 else if (tdesc_unnumbered_register (feature, "fd3"))
1895 freg = 0;
1896
1897 if (freg == -1)
1898 /* Required FDR is not found. */
1899 return 0;
1900 else
1901 *fpu_freg = freg;
1902
1903 /* Validate and fixed-number required FDRs. */
1904 num_fdr_regs = num_fdr_map[freg];
1905 for (i = 0; i < num_fdr_regs; i++)
1906 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1907 NDS32_FD0_REGNUM + i,
1909 if (!valid_p)
1910 return 0;
1911
1912 /* Count the number of listed FSRs, and fixed-number them if present. */
1913 num_fsr_regs = num_fsr_map[freg];
1914 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1915 num_listed_fsr = 0;
1916 for (i = 0; i < num_fsr_regs; i++)
1917 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1918 fs0_regnum + i,
1920
1921 if (num_listed_fsr == 0)
1922 /* No required FSRs are listed explicitly, make them pseudo registers
1923 of FDRs. */
1924 *use_pseudo_fsrs = 1;
1925 else if (num_listed_fsr == num_fsr_regs)
1926 /* All required FSRs are listed explicitly. */
1927 *use_pseudo_fsrs = 0;
1928 else
1929 /* Some required FSRs are missing. */
1930 return 0;
1931 }
1932
1933 return 1;
1934}
1935
1936/* Initialize the current architecture based on INFO. If possible,
1937 re-use an architecture from ARCHES, which is a list of
1938 architectures already created during this debugging session.
1939
1940 Called e.g. at program startup, when reading a core file, and when
1941 reading a binary file. */
1942
1943static struct gdbarch *
1945{
1946 struct gdbarch_list *best_arch;
1948 const struct target_desc *tdesc = info.target_desc;
1949 int elf_abi = E_NDS_ABI_AABI;
1950 int fpu_freg = -1;
1951 int use_pseudo_fsrs = 0;
1952 int i, num_regs, maxregs;
1953
1954 /* Extract the elf_flags if available. */
1955 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1956 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
1957
1958 /* If there is already a candidate, use it. */
1959 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
1960 best_arch != NULL;
1961 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
1962 {
1963 nds32_gdbarch_tdep *idep
1964 = gdbarch_tdep<nds32_gdbarch_tdep> (best_arch->gdbarch);
1965
1966 if (idep->elf_abi != elf_abi)
1967 continue;
1968
1969 /* Found a match. */
1970 break;
1971 }
1972
1973 if (best_arch != NULL)
1974 return best_arch->gdbarch;
1975
1976 if (!tdesc_has_registers (tdesc))
1977 tdesc = tdesc_nds32;
1978
1980
1981 if (!nds32_validate_tdesc_p (tdesc, tdesc_data.get (), &fpu_freg,
1982 &use_pseudo_fsrs))
1983 return NULL;
1984
1985 /* Allocate space for the new architecture. */
1988 nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1989
1990 tdep->fpu_freg = fpu_freg;
1991 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
1992 tdep->fs0_regnum = -1;
1993 tdep->elf_abi = elf_abi;
1994
1997
1998 if (fpu_freg == -1)
1999 num_regs = NDS32_NUM_REGS;
2000 else if (use_pseudo_fsrs == 1)
2001 {
2007
2008 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2009 }
2010 else
2011 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2012
2013 set_gdbarch_num_regs (gdbarch, num_regs);
2014 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
2015
2016 /* Cache the register number of fs0. */
2017 if (fpu_freg != -1)
2018 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2019
2020 /* Add NDS32 register aliases. To avoid search in user register name space,
2021 user_reg_map_name_to_regnum is not used. */
2022 maxregs = gdbarch_num_cooked_regs (gdbarch);
2023 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2024 {
2025 int regnum, j;
2026
2027 regnum = -1;
2028 /* Search register name space. */
2029 for (j = 0; j < maxregs; j++)
2030 {
2031 const char *regname = gdbarch_register_name (gdbarch, j);
2032
2033 if (strcmp (regname, nds32_register_aliases[i].name) == 0)
2034 {
2035 regnum = j;
2036 break;
2037 }
2038 }
2039
2040 /* Try next alias entry if the given name can not be found in register
2041 name space. */
2042 if (regnum == -1)
2043 continue;
2044
2046 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2047 }
2048
2050
2051 /* Hook in ABI-specific overrides, if they have been registered. */
2052 info.tdesc_data = tdesc_data.get ();
2054
2055 /* Override tdesc_register callbacks for system registers. */
2057
2061 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2062
2065
2069 nds32_breakpoint::kind_from_pc);
2071 nds32_breakpoint::bp_from_kind);
2072
2075
2076 /* Handle longjmp. */
2078
2079 /* The order of appending is the order it check frame. */
2083
2084 return gdbarch;
2085}
2086
2088void
2090{
2091 /* Initialize gdbarch. */
2092 gdbarch_register (bfd_arch_nds32, nds32_gdbarch_init);
2093
2096}
@ ADD
int regnum
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep, gdbarch_supports_arch_info_ftype *supports_arch_info)
static std::vector< const char * > arches
Definition arch-utils.c:685
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
Definition arch-utils.c:177
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
#define BP_MANIPULATION(BREAK_INSN)
Definition arch-utils.h:70
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
Definition blockframe.c:373
enum register_status raw_read(int regnum, gdb_byte *buf)
Definition regcache.c:611
enum register_status cooked_read(int regnum, gdb_byte *buf)
Definition regcache.c:698
void cooked_write(int regnum, const gdb_byte *buf)
Definition regcache.c:870
void raw_write(int regnum, const gdb_byte *buf)
Definition regcache.c:833
void * get(unsigned key)
Definition registry.h:211
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
Definition corefile.c:347
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
Definition corefile.c:306
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
Definition defs.h:515
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
Definition defs.h:480
return_value_convention
Definition defs.h:257
@ RETURN_VALUE_REGISTER_CONVENTION
Definition defs.h:260
@ RETURN_VALUE_STRUCT_CONVENTION
Definition defs.h:267
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
Definition frame.c:1369
struct value * value_of_register(int regnum, frame_info_ptr frame)
Definition findvar.c:253
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
Definition frame-base.c:93
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
struct value * frame_unwind_got_memory(frame_info_ptr frame, int regnum, CORE_ADDR addr)
struct value * frame_unwind_got_register(frame_info_ptr frame, int regnum, int new_regnum)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
int frame_relative_level(frame_info_ptr fi)
Definition frame.c:2946
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
Definition frame.c:1399
CORE_ADDR get_frame_pc(frame_info_ptr frame)
Definition frame.c:2712
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
Definition frame.c:736
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
Definition frame.c:3027
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
Definition frame.c:1098
@ NORMAL_FRAME
Definition frame.h:187
#define FRAME_OBSTACK_ZALLOC(TYPE)
Definition frame.h:825
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
Definition gdbarch.c:1396
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
Definition gdbarch.c:2173
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype *get_longjmp_target)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_wchar_bit(struct gdbarch *gdbarch, int wchar_bit)
Definition gdbarch.c:1680
void set_gdbarch_return_value(struct gdbarch *gdbarch, gdbarch_return_value_ftype *return_value)
void set_gdbarch_wchar_signed(struct gdbarch *gdbarch, int wchar_signed)
Definition gdbarch.c:1698
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition gdbarch.c:1930
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
Definition gdbarch.c:2047
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
Definition gdbarch.c:2064
int gdbarch_num_pseudo_regs(struct gdbarch *gdbarch)
Definition gdbarch.c:1948
void set_gdbarch_stack_frame_destroyed_p(struct gdbarch *gdbarch, gdbarch_stack_frame_destroyed_p_ftype *stack_frame_destroyed_p)
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
Definition gdbarch.c:1958
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
Definition gdbarch.c:1941
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, gdbarch_tdep_up tdep)
Definition gdbarch.c:266
std::unique_ptr< gdbarch_tdep_base > gdbarch_tdep_up
Definition gdbarch.h:73
static int gdbarch_num_cooked_regs(gdbarch *arch)
Definition gdbarch.h:390
function_call_return_method
Definition gdbarch.h:114
@ return_method_struct
Definition gdbarch.h:126
const struct floatformat * floatformats_ieee_single[BFD_ENDIAN_UNKNOWN]
Definition gdbtypes.c:85
struct type * init_float_type(type_allocator &alloc, int bit, const char *name, const struct floatformat **floatformats, enum bfd_endian byte_order)
Definition gdbtypes.c:3408
unsigned type_align(struct type *type)
Definition gdbtypes.c:3527
struct type * check_typedef(struct type *type)
Definition gdbtypes.c:2966
type_code
Definition gdbtypes.h:82
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
Definition gnu-nat.c:1790
info(Component c)
Definition gdbarch.py:41
#define N32_LMW_BIM
Definition nds32-tdep.c:53
static struct value * nds32_epilogue_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static int nds32_abi_use_fpr(int elf_abi)
Definition nds32-tdep.c:508
static CORE_ADDR nds32_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
static const char *const nds32_fdr_register_names[]
Definition nds32-tdep.c:90
static void nds32_store_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, const gdb_byte *valbuf)
static const struct frame_unwind nds32_frame_unwind
Definition nds32-tdep.c:990
static const reggroup * nds32_hspr_reggroup
Definition nds32-tdep.c:322
static int nds32_analyze_epilogue_insn32(int abi_use_fpr, uint32_t insn, struct nds32_frame_cache *cache)
static int nds32_validate_tdesc_p(const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, int *fpu_freg, int *use_pseudo_fsrs)
static int nds32_abi_split(int elf_abi)
Definition nds32-tdep.c:517
static int nds32_check_calling_use_fpr(struct type *type)
static void nds32_pop_multiple_words(struct nds32_frame_cache *cache, int rb, int re, int enable4)
static struct nds32_frame_cache * nds32_frame_cache(frame_info_ptr this_frame, void **this_cache)
Definition nds32-tdep.c:904
static CORE_ADDR nds32_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
Definition nds32-tdep.c:276
#define N32_SMW_ADM
Definition nds32-tdep.c:51
static struct nds32_frame_cache * nds32_epilogue_frame_cache(frame_info_ptr this_frame, void **this_cache)
static int nds32_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR addr)
static void nds32_extract_return_value(struct gdbarch *gdbarch, struct type *type, struct regcache *regcache, gdb_byte *valbuf)
static int nds32_analyze_epilogue(struct gdbarch *gdbarch, CORE_ADDR pc, struct nds32_frame_cache *cache)
static struct value * nds32_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
Definition nds32-tdep.c:970
@ REG_UNAVAIL
Definition nds32-tdep.c:59
static const reggroup * nds32_dr_reggroup
Definition nds32-tdep.c:320
static void nds32_push_multiple_words(struct nds32_frame_cache *cache, int rb, int re, int enable4)
Definition nds32-tdep.c:572
static const struct @139 nds32_register_aliases[]
static struct type * nds32_pseudo_register_type(struct gdbarch *gdbarch, int regnum)
Definition nds32-tdep.c:400
constexpr gdb_byte nds32_break_insn[]
Definition nds32-tdep.c:283
static const reggroup * nds32_mr_reggroup
Definition nds32-tdep.c:319
static enum register_status nds32_pseudo_register_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
Definition nds32-tdep.c:431
static struct value * value_of_nds32_reg(frame_info_ptr frame, const void *baton)
Definition nds32-tdep.c:268
void _initialize_nds32_tdep()
static int nds32_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *reggroup)
Definition nds32-tdep.c:362
static const reggroup * nds32_idr_reggroup
Definition nds32-tdep.c:325
static void nds32_add_reggroups(struct gdbarch *gdbarch)
Definition nds32-tdep.c:344
static enum return_value_convention nds32_return_value(struct gdbarch *gdbarch, struct value *func_type, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf)
static const struct frame_unwind nds32_epilogue_frame_unwind
static CORE_ADDR nds32_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
Definition nds32-tdep.c:870
#define N32_LSMW_ENABLE4(insn)
Definition nds32-tdep.c:50
static const reggroup * nds32_ir_reggroup
Definition nds32-tdep.c:318
static const char *const nds32_fsr_register_names[]
Definition nds32-tdep.c:98
static void nds32_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
Definition nds32-tdep.c:955
const char * name
Definition nds32-tdep.c:113
static void nds32_pseudo_register_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
Definition nds32-tdep.c:470
#define CHOP_BITS(insn, n)
Definition nds32-tdep.c:49
static const struct frame_base nds32_frame_base
static CORE_ADDR nds32_frame_base_address(frame_info_ptr this_frame, void **this_cache)
static const reggroup * nds32_pfr_reggroup
Definition nds32-tdep.c:321
const char * alias
Definition nds32-tdep.c:114
const int num_fdr_map[]
Definition nds32-tdep.c:107
static CORE_ADDR nds32_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
Definition nds32-tdep.c:608
static const reggroup * nds32_secur_reggroup
Definition nds32-tdep.c:326
static int nds32_analyze_epilogue_insn16(uint32_t insn, struct nds32_frame_cache *cache)
#define NDS32_NUM_SAVED_REGS
Definition nds32-tdep.c:522
static void nds32_epilogue_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static struct gdbarch * nds32_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
static const reggroup * nds32_cr_reggroup
Definition nds32-tdep.c:317
const int num_fsr_map[]
Definition nds32-tdep.c:108
@ INSN_RETURN
Definition nds32-tdep.c:74
@ INSN_RECOVER
Definition nds32-tdep.c:72
@ INSN_NORMAL
Definition nds32-tdep.c:68
@ INSN_RECOVER_RETURN
Definition nds32-tdep.c:76
@ INSN_RESET_SP
Definition nds32-tdep.c:70
static const char *const nds32_register_names[]
Definition nds32-tdep.c:79
static const reggroup * nds32_dmar_reggroup
Definition nds32-tdep.c:323
static int nds32_get_longjmp_target(frame_info_ptr frame, CORE_ADDR *pc)
static void nds32_init_reggroups(void)
Definition nds32-tdep.c:329
static int nds32_epilogue_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_cache)
static const char * nds32_pseudo_register_name(struct gdbarch *gdbarch, int regnum)
Definition nds32-tdep.c:419
static const reggroup * nds32_racr_reggroup
Definition nds32-tdep.c:324
@ INVALID_OFFSET
Definition nds32-tdep.c:62
#define N32_FLDI_SP
Definition nds32-tdep.c:55
static struct nds32_frame_cache * nds32_alloc_frame_cache(void)
Definition nds32-tdep.c:551
@ NDS32_R0_REGNUM
Definition nds32-tdep.h:29
@ NDS32_SP_REGNUM
Definition nds32-tdep.h:35
@ NDS32_FP_REGNUM
Definition nds32-tdep.h:32
@ NDS32_FD0_REGNUM
Definition nds32-tdep.h:42
@ NDS32_LP_REGNUM
Definition nds32-tdep.h:34
@ NDS32_NUM_REGS
Definition nds32-tdep.h:39
@ NDS32_TA_REGNUM
Definition nds32-tdep.h:31
@ NDS32_PC_REGNUM
Definition nds32-tdep.h:37
static void initialize_tdesc_nds32(void)
Definition nds32.c:10
const struct target_desc * tdesc_nds32
Definition nds32.c:8
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
Definition osabi.c:382
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
Definition regcache.c:796
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
Definition regcache.c:825
const reggroup *const general_reggroup
Definition reggroups.c:251
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
Definition reggroups.c:147
const reggroup * reggroup_new(const char *name, enum reggroup_type type)
Definition reggroups.c:34
const reggroup *const system_reggroup
Definition reggroups.c:253
const reggroup *const float_reggroup
Definition reggroups.c:252
const reggroup *const save_reggroup
Definition reggroups.c:256
const reggroup *const all_reggroup
Definition reggroups.c:255
void reggroup_add(struct gdbarch *gdbarch, const reggroup *group)
Definition reggroups.c:124
const reggroup *const restore_reggroup
Definition reggroups.c:257
@ USER_REGGROUP
Definition reggroups.h:32
enum var_types type
Definition scm-param.c:142
struct type * type() const
Definition gdbtypes.h:547
struct gdbarch * gdbarch
Definition gdbarch.h:243
struct gdbarch_list * next
Definition gdbarch.h:244
CORE_ADDR fp_offset
Definition nds32-tdep.c:539
CORE_ADDR sp_offset
Definition nds32-tdep.c:538
CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS]
Definition nds32-tdep.c:545
CORE_ADDR prev_sp
Definition nds32-tdep.c:528
const char * name() const
Definition reggroups.h:51
type_code code() const
Definition gdbtypes.h:956
ULONGEST length() const
Definition gdbtypes.h:983
struct field & field(int idx) const
Definition gdbtypes.h:1012
unsigned int num_fields() const
Definition gdbtypes.h:994
Definition value.h:130
struct type * type() const
Definition value.h:180
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
Definition symtab.c:3963
tdesc_arch_data_up tdesc_data_alloc(void)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
static const registry< gdbarch >::key< tdesc_arch_data > tdesc_data
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, tdesc_arch_data_up &&early_data, tdesc_unknown_register_ftype unk_reg_cb)
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int tdesc_has_registers(const struct target_desc *target_desc)
void set_tdesc_pseudo_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *pseudo_type)
int tdesc_unnumbered_register(const struct tdesc_feature *feature, const char *name)
int tdesc_register_in_reggroup_p(struct gdbarch *gdbarch, int regno, const struct reggroup *reggroup)
std::unique_ptr< tdesc_arch_data, tdesc_arch_data_deleter > tdesc_arch_data_up
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
Definition target.c:1785
void user_reg_add(struct gdbarch *gdbarch, const char *name, user_reg_read_ftype *xread, const void *baton)
Definition user-regs.c:122
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
Definition user-regs.c:132