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aarch64-insn.h File Reference

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Classes

struct  aarch64_register
 
struct  aarch64_memory_operand
 
struct  aarch64_insn_data
 
struct  aarch64_insn_visitor
 

Macros

#define aarch64_debug_printf(fmt, ...)    debug_prefixed_printf_cond (aarch64_debug, "aarch64", fmt, ##__VA_ARGS__)
 
#define submask(x)   ((1L << ((x) + 1)) - 1)
 
#define bits(obj, st, fn)   (((obj) >> (st)) & submask ((fn) - (st)))
 
#define bit(obj, st)   (((obj) >> (st)) & 1)
 
#define sbits(obj, st, fn)    ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
 
#define IS_BTI(instruction)   ((instruction & 0xffffff3f) == 0xd503241f)
 
#define ENCODE(val, size, offset)    ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
 
#define can_encode_int32(val, bits)    (((val) >> (bits)) == 0 || ((val) >> (bits)) == -1)
 
#define emit_b(buf, is_bl, offset)    aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0)))
 
#define emit_bcond(buf, cond, offset)
 
#define emit_cb(buf, is_cbnz, rt, offset)
 
#define emit_ldr(buf, rt, rn, operand)    aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)
 
#define emit_ldrsw(buf, rt, rn, operand)    aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)
 
#define emit_tb(buf, is_tbnz, bit, rt, offset)
 
#define emit_nop(buf)   aarch64_emit_insn (buf, NOP)
 

Enumerations

enum  aarch64_opcodes {
  B = 0x14000000 , BL = 0x80000000 | B , BCOND = 0x40000000 | B , CBZ = 0x20000000 | B ,
  CBNZ = 0x21000000 | B , TBZ = 0x36000000 | B , TBNZ = 0x37000000 | B , BR = 0xd61f0000 ,
  BLR = 0xd63f0000 , RET = 0xd65f0000 , STP = 0x28000000 , LDP = 0x28400000 ,
  STP_SIMD_VFP = 0x04000000 | STP , LDP_SIMD_VFP = 0x04000000 | LDP , STR = 0x38000000 , LDR = 0x00400000 | STR ,
  LDRSW = 0x80800000 | STR , LDAXR = 0x085ffc00 , STXR = 0x08007c00 , STLR = 0x089ffc00 ,
  MOV = 0x52800000 , MOVK = 0x20000000 | MOV , ADD = 0x01000000 , SUB = 0x40000000 | ADD ,
  SUBS = 0x20000000 | SUB , AND = 0x0a000000 , ORR = 0x20000000 | AND , ORN = 0x00200000 | ORR ,
  EOR = 0x40000000 | AND , LSLV = 0x1ac02000 , LSRV = 0x00000400 | LSLV , ASRV = 0x00000800 | LSLV ,
  SBFM = 0x13000000 , UBFM = 0x40000000 | SBFM , CSINC = 0x9a800400 , MUL = 0x1b007c00 ,
  MSR = 0xd5100000 , MRS = 0x00200000 | MSR , HINT = 0xd503201f , SEVL = (5 << 5) | HINT ,
  WFE = (2 << 5) | HINT , NOP = (0 << 5) | HINT
}
 
enum  aarch64_masks { CLEAR_Rn_MASK = 0xfffffc1f }
 
enum  aarch64_memory_operand_type { MEMORY_OPERAND_OFFSET , MEMORY_OPERAND_PREINDEX , MEMORY_OPERAND_POSTINDEX }
 

Functions

int aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp, unsigned *rd, int32_t *offset)
 
int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
 
int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
 
int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz, unsigned *rn, int32_t *offset)
 
int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit, unsigned *rt, int32_t *imm)
 
int aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w, int *is64, unsigned *rt, int32_t *offset)
 
void aarch64_relocate_instruction (uint32_t insn, const struct aarch64_insn_visitor *visitor, struct aarch64_insn_data *data)
 
int aarch64_emit_insn (uint32_t *buf, uint32_t insn)
 
int aarch64_emit_load_store (uint32_t *buf, uint32_t size, enum aarch64_opcodes opcode, struct aarch64_register rt, struct aarch64_register rn, struct aarch64_memory_operand operand)
 

Variables

bool aarch64_debug
 

Macro Definition Documentation

◆ aarch64_debug_printf

#define aarch64_debug_printf ( fmt,
... )    debug_prefixed_printf_cond (aarch64_debug, "aarch64", fmt, ##__VA_ARGS__)

◆ bit

#define bit ( obj,
st )   (((obj) >> (st)) & 1)

Definition at line 38 of file aarch64-insn.h.

Referenced by aarch64_decode_tb(), aarch64_displaced_step_copy_insn(), aarch64_displaced_step_tb(), aarch64_record_asimd_load_store(), aarch64_record_branch_except_sys(), aarch64_record_data_proc_imm(), aarch64_record_data_proc_reg(), aarch64_record_data_proc_simd_fp(), aarch64_record_decode_insn_handler(), aarch64_record_load_store(), aarch64_relocate_instruction(), aarch64_software_single_step(), arch_flags_type(), arm_copy_b_bl_blx(), arm_copy_block_xfer(), arm_copy_bx_blx_reg(), arm_copy_copro_load_store(), arm_copy_extra_ld_st(), arm_copy_ldr_str_ldrb_strb(), arm_decode_b_bl_ldmstm(), arm_decode_dp_misc(), arm_decode_ld_st_word_ubyte(), arm_decode_svc_copro(), arm_decode_unconditional(), arm_get_next_pcs_raw(), arm_instruction_changes_pc(), arm_linux_get_next_pcs_fixup(), arm_m_exception_cache(), arm_record_asimd_vfp_coproc(), arm_record_b_bl(), arm_record_coproc_data_proc(), arm_record_data_proc_misc_ld_str(), arm_record_exreg_ld_st_insn(), arm_record_extension_space(), arm_record_ld_st_imm_offset(), arm_record_ld_st_multiple(), arm_record_ld_st_reg_offset(), arm_record_media(), arm_record_vdata_transfer_insn(), arm_record_vfp_data_proc_insn(), create_enum(), darwin_set_sstep(), decode_thumb_32bit_ld_mem_hints(), init_boolean_type(), init_character_type(), init_decfloat_type(), init_fixed_point_type(), init_float_type(), init_integer_type(), init_pointer_type(), m32c_pv_pushm_one(), mips32_next_pc(), type_allocator::new_type(), value::set_bitpos(), value::set_bitsize(), shifted_reg_val(), thumb2_copy_b_bl_blx(), thumb2_copy_block_xfer(), thumb2_copy_load_literal(), thumb2_copy_preload(), thumb2_copy_table_branch(), thumb2_decode_svc_copro(), thumb2_instruction_changes_pc(), thumb2_record_asimd_struct_ld_st(), thumb2_record_coproc_insn(), thumb2_record_decode_insn_handler(), thumb2_record_ld_st_dual_ex_tbb(), thumb2_record_ld_st_multiple(), thumb2_record_str_single_data(), thumb_analyze_prologue(), thumb_copy_alu_reg(), thumb_copy_bx_blx_reg(), thumb_copy_cbnz_cbz(), thumb_copy_pc_relative_32bit(), thumb_deal_with_atomic_sequence_raw(), thumb_get_next_pcs_raw(), thumb_process_displaced_16bit_insn(), thumb_process_displaced_32bit_insn(), thumb_record_ld_st_reg_offset(), thumb_record_misc(), and verify_floatformat().

◆ bits

#define bits ( obj,
st,
fn )   (((obj) >> (st)) & submask ((fn) - (st)))

Definition at line 35 of file aarch64-insn.h.

Referenced by aarch64_record_asimd_load_store(), aarch64_record_branch_except_sys(), aarch64_record_data_proc_imm(), aarch64_record_data_proc_reg(), aarch64_record_data_proc_simd_fp(), aarch64_record_load_store(), ada_value_assign(), arm_analyze_load_stack_chk_guard(), arm_analyze_prologue(), arm_copy_alu_imm(), arm_copy_alu_reg(), arm_copy_alu_shifted_reg(), arm_copy_b_bl_blx(), arm_copy_block_xfer(), arm_copy_bx_blx_reg(), arm_copy_copro_load_store(), arm_copy_extra_ld_st(), arm_copy_ldr_str_ldrb_strb(), arm_copy_preload(), arm_copy_preload_reg(), arm_deal_with_atomic_sequence_raw(), arm_decode_dp_misc(), arm_decode_ext_reg_ld_st(), arm_decode_ld_st_word_ubyte(), arm_decode_media(), arm_decode_misc_memhint_neon(), arm_decode_miscellaneous(), arm_decode_svc_copro(), arm_decode_unconditional(), arm_get_next_pcs_raw(), arm_instruction_changes_pc(), arm_instruction_restores_sp(), arm_linux_get_next_pcs_fixup(), arm_process_record(), arm_record_asimd_vfp_coproc(), arm_record_coproc_data_proc(), arm_record_data_proc_imm(), arm_record_data_proc_misc_ld_str(), arm_record_exreg_ld_st_insn(), arm_record_extension_space(), arm_record_ld_st_imm_offset(), arm_record_ld_st_multiple(), arm_record_ld_st_reg_offset(), arm_record_media(), arm_record_strx(), arm_record_vdata_transfer_insn(), arm_record_vfp_data_proc_insn(), arm_skip_bx_reg(), arm_skip_stack_protector(), arm_stack_frame_destroyed_p_1(), selftests::bits_to_str(), compute_variant_fields_inner(), dbx_init_float_type(), decode_constrained_packed_array_type(), decode_insn(), decode_packed_array_bitsize(), decode_thumb_32bit_ld_mem_hints(), dwarf2_const_value_data(), dwarf2_init_complex_target_type(), dwarf2_init_float_type(), dwarf2_init_integer_type(), gen_extend(), hppa_low_hppa_sign_extend(), hppa_sign_extend(), locexpr_describe_location_1(), m32c_sign_ext(), amd_dbgapi_register_type_flags::make_lookup_name(), memcmp_with_bit_offsets(), opt_from_option_mask(), or1k_analyse_inst(), parse_amd_dbgapi_register_type_flags_fields(), print_bit_vector(), put_bits(), read_base_type(), read_huge_number(), read_range_type(), rgb_to_16colors(), sbo_sbz(), shifted_reg_val(), sparc64_pseudo_register_write(), thumb2_copy_alu_imm(), thumb2_copy_b_bl_blx(), thumb2_copy_block_xfer(), thumb2_copy_copro_load_store(), thumb2_copy_load_literal(), thumb2_copy_load_reg_imm(), thumb2_copy_preload(), thumb2_copy_table_branch(), thumb2_decode_dp_shift_reg(), thumb2_decode_ext_reg_ld_st(), thumb2_decode_svc_copro(), thumb2_instruction_changes_pc(), thumb2_record_asimd_struct_ld_st(), thumb2_record_branch_misc_cntrl(), thumb2_record_data_proc_sreg_mimm(), thumb2_record_decode_insn_handler(), thumb2_record_ld_mem_hints(), thumb2_record_ld_st_dual_ex_tbb(), thumb2_record_ld_st_multiple(), thumb2_record_ld_word(), thumb2_record_lmul_lmla_div(), thumb2_record_ps_dest_generic(), thumb2_record_str_single_data(), thumb_analyze_prologue(), thumb_copy_16bit_ldr_literal(), thumb_copy_alu_reg(), thumb_copy_b(), thumb_copy_bx_blx_reg(), thumb_copy_cbnz_cbz(), thumb_copy_pc_relative_32bit(), thumb_deal_with_atomic_sequence_raw(), thumb_decode_pc_relative_16bit(), thumb_get_next_pcs_raw(), thumb_process_displaced_16bit_insn(), thumb_process_displaced_32bit_insn(), thumb_record_add_sub_cmp_mov(), thumb_record_branch(), thumb_record_ld_st_imm_offset(), thumb_record_ld_st_reg_offset(), thumb_record_ld_st_stack(), thumb_record_ldm_stm_swi(), thumb_record_misc(), thumb_record_shift_add_sub(), tic6x_extract_signed_field(), value_assign_to_component(), and value_subscript_packed().

◆ can_encode_int32

#define can_encode_int32 ( val,
bits )    (((val) >> (bits)) == 0 || ((val) >> (bits)) == -1)

Definition at line 250 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_b().

◆ emit_b

#define emit_b ( buf,
is_bl,
offset )    aarch64_emit_insn (buf, ((is_bl) ? BL : B) | (ENCODE ((offset) >> 2, 26, 0)))

Definition at line 263 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_b().

◆ emit_bcond

#define emit_bcond ( buf,
cond,
offset )
Value:
BCOND | ENCODE ((offset) >> 2, 19, 5) \
| ENCODE ((cond), 4, 0))
int aarch64_emit_insn(uint32_t *buf, uint32_t insn)
@ BCOND
#define ENCODE(val, size, offset)

Definition at line 275 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_b_cond().

◆ emit_cb

#define emit_cb ( buf,
is_cbnz,
rt,
offset )
Value:
((is_cbnz) ? CBNZ : CBZ) \
| ENCODE (rt.is64, 1, 31) /* sf */ \
| ENCODE (offset >> 2, 19, 5) /* imm19 */ \
| ENCODE (rt.num, 5, 0))
@ CBNZ
@ CBZ

Definition at line 291 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_cb().

◆ emit_ldr

#define emit_ldr ( buf,
rt,
rn,
operand )    aarch64_emit_load_store (buf, rt.is64 ? 3 : 2, LDR, rt, rn, operand)

Definition at line 309 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_ldr_literal().

◆ emit_ldrsw

#define emit_ldrsw ( buf,
rt,
rn,
operand )    aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)

Definition at line 323 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_ldr_literal().

◆ emit_nop

#define emit_nop ( buf)    aarch64_emit_insn (buf, NOP)

Definition at line 349 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_adr(), and aarch64_displaced_step_b().

◆ emit_tb

#define emit_tb ( buf,
is_tbnz,
bit,
rt,
offset )
Value:
((is_tbnz) ? TBNZ: TBZ) \
| ENCODE (bit >> 5, 1, 31) /* b5 */ \
| ENCODE (bit, 5, 19) /* b40 */ \
| ENCODE (offset >> 2, 14, 5) /* imm14 */ \
| ENCODE (rt.num, 5, 0))
#define bit(obj, st)
@ TBZ
@ TBNZ

Definition at line 339 of file aarch64-insn.h.

Referenced by aarch64_displaced_step_tb().

◆ ENCODE

#define ENCODE ( val,
size,
offset )    ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))

Definition at line 182 of file aarch64-insn.h.

Referenced by aarch64_emit_load_store().

◆ IS_BTI

#define IS_BTI ( instruction)    ((instruction & 0xffffff3f) == 0xd503241f)

Definition at line 48 of file aarch64-insn.h.

Referenced by aarch64_analyze_prologue(), and thumb_analyze_prologue().

◆ sbits

#define sbits ( obj,
st,
fn )    ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))

◆ submask

#define submask ( x)    ((1L << ((x) + 1)) - 1)

Definition at line 32 of file aarch64-insn.h.

Enumeration Type Documentation

◆ aarch64_masks

Enumerator
CLEAR_Rn_MASK 

Definition at line 139 of file aarch64-insn.h.

◆ aarch64_memory_operand_type

Enumerator
MEMORY_OPERAND_OFFSET 
MEMORY_OPERAND_PREINDEX 
MEMORY_OPERAND_POSTINDEX 

Definition at line 155 of file aarch64-insn.h.

◆ aarch64_opcodes

Enumerator
BL 
BCOND 
CBZ 
CBNZ 
TBZ 
TBNZ 
BR 
BLR 
RET 
STP 
LDP 
STP_SIMD_VFP 
LDP_SIMD_VFP 
STR 
LDR 
LDRSW 
LDAXR 
STXR 
STLR 
MOV 
MOVK 
ADD 
SUB 
SUBS 
AND 
ORR 
ORN 
EOR 
LSLV 
LSRV 
ASRV 
SBFM 
UBFM 
CSINC 
MUL 
MSR 
MRS 
HINT 
SEVL 
WFE 
NOP 

Definition at line 53 of file aarch64-insn.h.

Function Documentation

◆ aarch64_decode_adr()

int aarch64_decode_adr ( CORE_ADDR addr,
uint32_t insn,
int * is_adrp,
unsigned * rd,
int32_t * offset )

Definition at line 50 of file aarch64-insn.c.

References aarch64_debug_printf, decode_masked_match(), and sbits.

Referenced by aarch64_relocate_instruction().

◆ aarch64_decode_b()

int aarch64_decode_b ( CORE_ADDR addr,
uint32_t insn,
int * is_bl,
int32_t * offset )

Definition at line 91 of file aarch64-insn.c.

References aarch64_debug, decode_masked_match(), and sbits.

Referenced by aarch64_relocate_instruction().

◆ aarch64_decode_bcond()

int aarch64_decode_bcond ( CORE_ADDR addr,
uint32_t insn,
unsigned * cond,
int32_t * offset )

Definition at line 125 of file aarch64-insn.c.

References aarch64_debug, decode_masked_match(), and sbits.

Referenced by aarch64_relocate_instruction().

◆ aarch64_decode_cb()

int aarch64_decode_cb ( CORE_ADDR addr,
uint32_t insn,
int * is64,
int * is_cbnz,
unsigned * rn,
int32_t * offset )

Definition at line 157 of file aarch64-insn.c.

References aarch64_debug, decode_masked_match(), and sbits.

Referenced by aarch64_relocate_instruction().

◆ aarch64_decode_ldr_literal()

int aarch64_decode_ldr_literal ( CORE_ADDR addr,
uint32_t insn,
int * is_w,
int * is64,
unsigned * rt,
int32_t * offset )

Definition at line 230 of file aarch64-insn.c.

References aarch64_debug, and sbits.

Referenced by aarch64_relocate_instruction().

◆ aarch64_decode_tb()

int aarch64_decode_tb ( CORE_ADDR addr,
uint32_t insn,
int * is_tbnz,
unsigned * bit,
unsigned * rt,
int32_t * imm )

Definition at line 193 of file aarch64-insn.c.

References aarch64_debug, bit, decode_masked_match(), and sbits.

Referenced by aarch64_relocate_instruction().

◆ aarch64_emit_insn()

int aarch64_emit_insn ( uint32_t * buf,
uint32_t insn )

Definition at line 314 of file aarch64-insn.c.

Referenced by aarch64_displaced_step_others(), and aarch64_emit_load_store().

◆ aarch64_emit_load_store()

int aarch64_emit_load_store ( uint32_t * buf,
uint32_t size,
enum aarch64_opcodes opcode,
struct aarch64_register rt,
struct aarch64_register rn,
struct aarch64_memory_operand operand )

◆ aarch64_relocate_instruction()

void aarch64_relocate_instruction ( uint32_t insn,
const struct aarch64_insn_visitor * visitor,
struct aarch64_insn_data * data )

Variable Documentation

◆ aarch64_debug

bool aarch64_debug
extern