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mips-linux-nat.c
Go to the documentation of this file.
1/* Native-dependent code for GNU/Linux on MIPS processors.
2
3 Copyright (C) 2001-2023 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "command.h"
22#include "gdbcmd.h"
23#include "inferior.h"
24#include "mips-tdep.h"
25#include "target.h"
26#include "regcache.h"
27#include "linux-nat-trad.h"
28#include "mips-linux-tdep.h"
29#include "target-descriptions.h"
30
31#include "gdb_proc_service.h"
32#include "gregset.h"
33
34#include <sgidefs.h>
35#include "nat/gdb_ptrace.h"
36#include <asm/ptrace.h>
37#include "inf-ptrace.h"
38
40
41#ifndef PTRACE_GET_THREAD_AREA
42#define PTRACE_GET_THREAD_AREA 25
43#endif
44
46{
47public:
48 /* Add our register access methods. */
49 void fetch_registers (struct regcache *, int) override;
50 void store_registers (struct regcache *, int) override;
51
52 void close () override;
53
54 int can_use_hw_breakpoint (enum bptype, int, int) override;
55
56 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
57 struct expression *) override;
58
59 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
60 struct expression *) override;
61
62 bool stopped_by_watchpoint () override;
63
64 bool stopped_data_address (CORE_ADDR *) override;
65
66 int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
67
68 const struct target_desc *read_description () override;
69
70protected:
71 /* Override linux_nat_trad_target methods. */
72 CORE_ADDR register_u_offset (struct gdbarch *gdbarch,
73 int regno, int store_p) override;
74
75 /* Override linux_nat_target low methods. */
76 void low_new_thread (struct lwp_info *lp) override;
77
78private:
79 /* Helpers. See definitions. */
81 int regno);
83 int regno);
84};
85
87
88/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
89 we'll clear this and use PTRACE_PEEKUSER instead. */
90static int have_ptrace_regsets = 1;
91
92/* Map gdb internal register number to ptrace ``address''.
93 These ``addresses'' are normally defined in <asm/ptrace.h>.
94
95 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
96 and there's no point in reading or setting MIPS_ZERO_REGNUM.
97 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
98
99static CORE_ADDR
100mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
101{
102 CORE_ADDR regaddr;
103
104 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
105 error (_("Bogon register number %d."), regno);
106
107 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
108 regaddr = regno;
109 else if ((regno >= mips_regnum (gdbarch)->fp0)
110 && (regno < mips_regnum (gdbarch)->fp0 + 32))
111 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
112 else if (regno == mips_regnum (gdbarch)->pc)
113 regaddr = PC;
114 else if (regno == mips_regnum (gdbarch)->cause)
115 regaddr = store? (CORE_ADDR) -1 : CAUSE;
116 else if (regno == mips_regnum (gdbarch)->badvaddr)
117 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
118 else if (regno == mips_regnum (gdbarch)->lo)
119 regaddr = MMLO;
120 else if (regno == mips_regnum (gdbarch)->hi)
121 regaddr = MMHI;
122 else if (regno == mips_regnum (gdbarch)->fp_control_status)
123 regaddr = FPC_CSR;
125 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
126 else if (mips_regnum (gdbarch)->dspacc != -1
127 && regno >= mips_regnum (gdbarch)->dspacc
128 && regno < mips_regnum (gdbarch)->dspacc + 6)
129 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
130 else if (regno == mips_regnum (gdbarch)->dspctl)
131 regaddr = DSP_CONTROL;
133 regaddr = 0;
134 else
135 regaddr = (CORE_ADDR) -1;
136
137 return regaddr;
138}
139
140static CORE_ADDR
141mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
142{
143 CORE_ADDR regaddr;
144
145 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
146 error (_("Bogon register number %d."), regno);
147
148 /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR
149 or PTRACE_POKEUSR. */
150 if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET))
151 return (CORE_ADDR) -1;
152
153 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
154 regaddr = regno;
155 else if ((regno >= mips_regnum (gdbarch)->fp0)
156 && (regno < mips_regnum (gdbarch)->fp0 + 32))
157 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
158 else if (regno == mips_regnum (gdbarch)->pc)
159 regaddr = MIPS64_PC;
160 else if (regno == mips_regnum (gdbarch)->cause)
161 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
162 else if (regno == mips_regnum (gdbarch)->badvaddr)
163 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
164 else if (regno == mips_regnum (gdbarch)->lo)
165 regaddr = MIPS64_MMLO;
166 else if (regno == mips_regnum (gdbarch)->hi)
167 regaddr = MIPS64_MMHI;
168 else if (regno == mips_regnum (gdbarch)->fp_control_status)
169 regaddr = MIPS64_FPC_CSR;
171 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
172 else if (mips_regnum (gdbarch)->dspacc != -1
173 && regno >= mips_regnum (gdbarch)->dspacc
174 && regno < mips_regnum (gdbarch)->dspacc + 6)
175 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
176 else if (regno == mips_regnum (gdbarch)->dspctl)
177 regaddr = DSP_CONTROL;
179 regaddr = 0;
180 else
181 regaddr = (CORE_ADDR) -1;
182
183 return regaddr;
184}
185
186/* Fetch the thread-local storage pointer for libthread_db. */
187
188ps_err_e
190 lwpid_t lwpid, int idx, void **base)
191{
192 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
193 return PS_ERR;
194
195 /* IDX is the bias from the thread pointer to the beginning of the
196 thread descriptor. It has to be subtracted due to implementation
197 quirks in libthread_db. */
198 *base = (void *) ((char *)*base - idx);
199
200 return PS_OK;
201}
202
203/* Wrapper functions. These are only used by libthread_db. */
204
205void
207{
208 if (mips_isa_regsize (regcache->arch ()) == 4)
209 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
210 else
212}
213
214void
216 gdb_gregset_t *gregsetp, int regno)
217{
218 if (mips_isa_regsize (regcache->arch ()) == 4)
219 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
220 else
222}
223
224void
226{
228}
229
230void
232 gdb_fpregset_t *fpregsetp, int regno)
233{
235}
236
237
238/* Fetch REGNO (or all registers if REGNO == -1) from the target
239 using PTRACE_GETREGS et al. */
240
241void
243 (struct regcache *regcache, int regno)
244{
245 struct gdbarch *gdbarch = regcache->arch ();
246 int is_fp, is_dsp;
247 int have_dsp;
248 int regi;
249 int tid;
250
251 if (regno >= mips_regnum (gdbarch)->fp0
252 && regno <= mips_regnum (gdbarch)->fp0 + 32)
253 is_fp = 1;
254 else if (regno == mips_regnum (gdbarch)->fp_control_status)
255 is_fp = 1;
256 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
257 is_fp = 1;
258 else
259 is_fp = 0;
260
261 /* DSP registers are optional and not a part of any set. */
262 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
263 if (!have_dsp)
264 is_dsp = 0;
265 else if (regno >= mips_regnum (gdbarch)->dspacc
266 && regno < mips_regnum (gdbarch)->dspacc + 6)
267 is_dsp = 1;
268 else if (regno == mips_regnum (gdbarch)->dspctl)
269 is_dsp = 1;
270 else
271 is_dsp = 0;
272
273 tid = get_ptrace_pid (regcache->ptid ());
274
275 if (regno == -1 || (!is_fp && !is_dsp))
276 {
278
279 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
280 {
281 if (errno == EIO)
282 {
284 return;
285 }
286 perror_with_name (_("Couldn't get registers"));
287 }
288
290 (const mips64_elf_gregset_t *) &regs);
291 }
292
293 if (regno == -1 || is_fp)
294 {
295 mips64_elf_fpregset_t fp_regs;
296
297 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
298 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
299 {
300 if (errno == EIO)
301 {
303 return;
304 }
305 perror_with_name (_("Couldn't get FP registers"));
306 }
307
309 (const mips64_elf_fpregset_t *) &fp_regs);
310 }
311
312 if (is_dsp)
314 else if (regno == -1 && have_dsp)
315 {
316 for (regi = mips_regnum (gdbarch)->dspacc;
317 regi < mips_regnum (gdbarch)->dspacc + 6;
318 regi++)
321 mips_regnum (gdbarch)->dspctl);
322 }
323}
324
325/* Store REGNO (or all registers if REGNO == -1) to the target
326 using PTRACE_SETREGS et al. */
327
328void
330 (struct regcache *regcache, int regno)
331{
332 struct gdbarch *gdbarch = regcache->arch ();
333 int is_fp, is_dsp;
334 int have_dsp;
335 int regi;
336 int tid;
337
338 if (regno >= mips_regnum (gdbarch)->fp0
339 && regno <= mips_regnum (gdbarch)->fp0 + 32)
340 is_fp = 1;
341 else if (regno == mips_regnum (gdbarch)->fp_control_status)
342 is_fp = 1;
343 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
344 is_fp = 1;
345 else
346 is_fp = 0;
347
348 /* DSP registers are optional and not a part of any set. */
349 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
350 if (!have_dsp)
351 is_dsp = 0;
352 else if (regno >= mips_regnum (gdbarch)->dspacc
353 && regno < mips_regnum (gdbarch)->dspacc + 6)
354 is_dsp = 1;
355 else if (regno == mips_regnum (gdbarch)->dspctl)
356 is_dsp = 1;
357 else
358 is_dsp = 0;
359
360 tid = get_ptrace_pid (regcache->ptid ());
361
362 if (regno == -1 || (!is_fp && !is_dsp))
363 {
365
366 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
367 perror_with_name (_("Couldn't get registers"));
368
369 mips64_fill_gregset (regcache, &regs, regno);
370
371 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
372 perror_with_name (_("Couldn't set registers"));
373 }
374
375 if (regno == -1 || is_fp)
376 {
377 mips64_elf_fpregset_t fp_regs;
378
379 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
380 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
381 perror_with_name (_("Couldn't get FP registers"));
382
383 mips64_fill_fpregset (regcache, &fp_regs, regno);
384
385 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
386 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
387 perror_with_name (_("Couldn't set FP registers"));
388 }
389
390 if (is_dsp)
392 else if (regno == -1 && have_dsp)
393 {
394 for (regi = mips_regnum (gdbarch)->dspacc;
395 regi < mips_regnum (gdbarch)->dspacc + 6;
396 regi++)
399 mips_regnum (gdbarch)->dspctl);
400 }
401}
402
403/* Fetch REGNO (or all registers if REGNO == -1) from the target
404 using any working method. */
405
406void
408{
409 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
412
413 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
414 back to PTRACE_PEEKUSER. */
416 {
418
419 /* Fill the inaccessible zero register with zero. */
420 if (regnum == MIPS_ZERO_REGNUM || regnum == -1)
422 }
423}
424
425/* Store REGNO (or all registers if REGNO == -1) to the target
426 using any working method. */
427
428void
430{
431 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
434
435 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
436 back to PTRACE_PEEKUSER. */
439}
440
441/* Return the address in the core dump or inferior of register
442 REGNO. */
443
444CORE_ADDR
446 int regno, int store_p)
447{
448 if (mips_abi_regsize (gdbarch) == 8)
449 return mips64_linux_register_addr (gdbarch, regno, store_p);
450 else
451 return mips_linux_register_addr (gdbarch, regno, store_p);
452}
453
454const struct target_desc *
456{
457 static int have_dsp = -1;
458
459 if (have_dsp < 0)
460 {
461 /* Assume no DSP if there is no inferior to inspect with ptrace. */
462 if (inferior_ptid == null_ptid)
463 return _MIPS_SIM == _ABIO32 ? tdesc_mips_linux : tdesc_mips64_linux;
464
465 int tid = get_ptrace_pid (inferior_ptid);
466
467 errno = 0;
468 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
469 switch (errno)
470 {
471 case 0:
472 have_dsp = 1;
473 break;
474 case EIO:
475 have_dsp = 0;
476 break;
477 default:
478 perror_with_name (_("Couldn't check DSP support"));
479 break;
480 }
481 }
482
483 /* Report that target registers are a size we know for sure
484 that we can get from ptrace. */
485 if (_MIPS_SIM == _ABIO32)
486 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
487 else
488 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
489}
490
491/* -1 if the kernel and/or CPU do not support watch registers.
492 1 if watch_readback is valid and we can read style, num_valid
493 and the masks.
494 0 if we need to read the watch_readback. */
495
497
498/* Cached watch register read values. */
499
501
503
504/* The current set of watch register values for writing the
505 registers. */
506
508
509static void
510mips_show_dr (const char *func, CORE_ADDR addr,
511 int len, enum target_hw_bp_type type)
512{
513 int i;
514
516 if (addr || len)
518 " (addr=%s, len=%d, type=%s)",
519 paddress (target_gdbarch (), addr), len,
520 type == hw_write ? "data-write"
521 : (type == hw_read ? "data-read"
522 : (type == hw_access ? "data-read/write"
523 : (type == hw_execute ? "instruction-execute"
524 : "??unknown??"))));
525 gdb_puts (":\n", gdb_stdlog);
526
527 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
528 gdb_printf (gdb_stdlog, "\tDR%d: lo=%s, hi=%s\n", i,
531 i)),
534 i)));
535}
536
537/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
538 handle the specified watch type. */
539
540int
542 int cnt, int ot)
543{
544 int i;
545 uint32_t wanted_mask, irw_mask;
546
550 return 0;
551
552 switch (type)
553 {
555 wanted_mask = W_MASK;
556 break;
558 wanted_mask = R_MASK;
559 break;
561 wanted_mask = R_MASK | W_MASK;
562 break;
563 default:
564 return 0;
565 }
566
567 for (i = 0;
569 i++)
570 {
572 if ((irw_mask & wanted_mask) == wanted_mask)
573 cnt--;
574 }
575 return (cnt == 0) ? 1 : 0;
576}
577
578/* Target to_stopped_by_watchpoint implementation. Return 1 if
579 stopped by watchpoint. The watchhi R and W bits indicate the watch
580 register triggered. */
581
582bool
584{
585 int n;
586 int num_valid;
587
591 return false;
592
594
595 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
597 return true;
598
599 return false;
600}
601
602/* Target to_stopped_data_address implementation. Set the address
603 where the watch triggered (if known). Return 1 if the address was
604 known. */
605
606bool
608{
609 /* On mips we don't know the low order 3 bits of the data address,
610 so we must return false. */
611 return false;
612}
613
614/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
615 the specified region can be covered by the watch registers. */
616
617int
619{
620 struct pt_watch_regs dummy_regs;
621 int i;
622
626 return 0;
627
628 dummy_regs = watch_readback;
629 /* Clear them out. */
630 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
631 mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
632 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
633}
634
635/* Write the mirrored watch register values for each thread. */
636
637static int
639{
640 for (const lwp_info *lp : all_lwps ())
641 {
642 int tid = lp->ptid.lwp ();
643 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
644 perror_with_name (_("Couldn't write debug register"));
645 }
646 return 0;
647}
648
649/* linux_nat_target::low_new_thread implementation. Write the
650 mirrored watch register values for the new thread. */
651
652void
654{
655 long tid = lp->ptid.lwp ();
656
660 return;
661
662 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
663 perror_with_name (_("Couldn't write debug register"));
664}
665
666/* Target to_insert_watchpoint implementation. Try to insert a new
667 watch. Return zero on success. */
668
669int
671 enum target_hw_bp_type type,
672 struct expression *cond)
673{
674 struct pt_watch_regs regs;
675 struct mips_watchpoint *new_watch;
676 struct mips_watchpoint **pw;
677
678 int retval;
679
683 return -1;
684
685 if (len <= 0)
686 return -1;
687
688 regs = watch_readback;
689 /* Add the current watches. */
691
692 /* Now try to add the new watch. */
693 if (!mips_linux_watch_try_one_watch (&regs, addr, len,
695 return -1;
696
697 /* It fit. Stick it on the end of the list. */
698 new_watch = XNEW (struct mips_watchpoint);
699 new_watch->addr = addr;
700 new_watch->len = len;
701 new_watch->type = type;
702 new_watch->next = NULL;
703
704 pw = &current_watches;
705 while (*pw != NULL)
706 pw = &(*pw)->next;
707 *pw = new_watch;
708
709 watch_mirror = regs;
710 retval = write_watchpoint_regs ();
711
712 if (show_debug_regs)
713 mips_show_dr ("insert_watchpoint", addr, len, type);
714
715 return retval;
716}
717
718/* Target to_remove_watchpoint implementation. Try to remove a watch.
719 Return zero on success. */
720
721int
723 enum target_hw_bp_type type,
724 struct expression *cond)
725{
726 int retval;
727 int deleted_one;
728
729 struct mips_watchpoint **pw;
730 struct mips_watchpoint *w;
731
732 /* Search for a known watch that matches. Then unlink and free
733 it. */
734 deleted_one = 0;
735 pw = &current_watches;
736 while ((w = *pw))
737 {
738 if (w->addr == addr && w->len == len && w->type == type)
739 {
740 *pw = w->next;
741 xfree (w);
742 deleted_one = 1;
743 break;
744 }
745 pw = &(w->next);
746 }
747
748 if (!deleted_one)
749 return -1; /* We don't know about it, fail doing nothing. */
750
751 /* At this point watch_readback is known to be valid because we
752 could not have added the watch without reading it. */
753 gdb_assert (watch_readback_valid == 1);
754
757
758 retval = write_watchpoint_regs ();
759
760 if (show_debug_regs)
761 mips_show_dr ("remove_watchpoint", addr, len, type);
762
763 return retval;
764}
765
766/* Target to_close implementation. Free any watches and call the
767 super implementation. */
768
769void
771{
772 struct mips_watchpoint *w;
773 struct mips_watchpoint *nw;
774
775 /* Clean out the current_watches list. */
776 w = current_watches;
777 while (w)
778 {
779 nw = w->next;
780 xfree (w);
781 w = nw;
782 }
783 current_watches = NULL;
784
786}
787
789void
791{
792 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
793 &show_debug_regs, _("\
794Set whether to show variables that mirror the mips debug registers."), _("\
795Show whether to show variables that mirror the mips debug registers."), _("\
796Use \"on\" to enable, \"off\" to disable.\n\
797If enabled, the debug registers values are shown when GDB inserts\n\
798or removes a hardware breakpoint or watchpoint, and when the inferior\n\
799triggers a breakpoint or watchpoint."),
800 NULL,
801 NULL,
804
807}
int regnum
void xfree(void *)
struct gdbarch * target_gdbarch(void)
bptype
Definition breakpoint.h:84
@ bp_read_watchpoint
Definition breakpoint.h:93
@ bp_access_watchpoint
Definition breakpoint.h:94
@ bp_hardware_watchpoint
Definition breakpoint.h:92
void close() override
Definition inf-child.c:183
void fetch_registers(struct regcache *, int) override
void store_registers(struct regcache *, int) override
int region_ok_for_hw_watchpoint(CORE_ADDR, int) override
void store_registers(struct regcache *, int) override
int can_use_hw_breakpoint(enum bptype, int, int) override
bool stopped_data_address(CORE_ADDR *) override
int remove_watchpoint(CORE_ADDR, int, enum target_hw_bp_type, struct expression *) override
bool stopped_by_watchpoint() override
void low_new_thread(struct lwp_info *lp) override
const struct target_desc * read_description() override
void close() override
void mips64_regsets_store_registers(struct regcache *regcache, int regno)
void fetch_registers(struct regcache *, int) override
int insert_watchpoint(CORE_ADDR, int, enum target_hw_bp_type, struct expression *) override
void mips64_regsets_fetch_registers(struct regcache *regcache, int regno)
CORE_ADDR register_u_offset(struct gdbarch *gdbarch, int regno, int store_p) override
gdbarch * arch() const
Definition regcache.c:231
void raw_supply_zeroed(int regnum)
Definition regcache.c:1110
ptid_t ptid() const
Definition regcache.h:408
struct cmd_list_element * maintenance_show_cmdlist
Definition maint.c:752
struct cmd_list_element * maintenance_set_cmdlist
Definition maint.c:751
set_show_commands add_setshow_boolean_cmd(const char *name, enum command_class theclass, bool *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
Definition cli-decode.c:809
@ class_maintenance
Definition command.h:65
#define PTRACE_TYPE_RET
Definition config.h:675
#define ptrace(request, pid, addr, data)
Definition gdb_ptrace.h:141
int gdbarch_num_regs(struct gdbarch *gdbarch)
Definition gdbarch.c:1930
int gdbarch_fp0_regnum(struct gdbarch *gdbarch)
Definition gdbarch.c:2088
GDB_FPREGSET_T gdb_fpregset_t
Definition gregset.h:35
GDB_GREGSET_T gdb_gregset_t
Definition gregset.h:34
@ L
Definition ia64-tdep.c:85
void add_inf_child_target(inf_child_target *target)
Definition inf-child.c:418
pid_t get_ptrace_pid(ptid_t ptid)
Definition inf-ptrace.c:238
ptid_t inferior_ptid
Definition infcmd.c:74
lwp_info_range all_lwps()
Definition linux-nat.c:638
struct linux_nat_target * linux_target
Definition linux-nat.c:189
#define PTRACE_TYPE_ARG3
const struct target_desc * tdesc_mips_dsp_linux
#define PTRACE_GET_THREAD_AREA
static mips_linux_nat_target the_mips_linux_nat_target
void supply_gregset(struct regcache *regcache, const gdb_gregset_t *gregsetp)
static CORE_ADDR mips_linux_register_addr(struct gdbarch *gdbarch, int regno, int store)
void fill_gregset(const struct regcache *regcache, gdb_gregset_t *gregsetp, int regno)
static struct mips_watchpoint * current_watches
void _initialize_mips_linux_nat()
void supply_fpregset(struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
ps_err_e ps_get_thread_area(struct ps_prochandle *ph, lwpid_t lwpid, int idx, void **base)
static int watch_readback_valid
static int write_watchpoint_regs(void)
static struct pt_watch_regs watch_readback
static struct pt_watch_regs watch_mirror
void fill_fpregset(const struct regcache *regcache, gdb_fpregset_t *fpregsetp, int regno)
static void mips_show_dr(const char *func, CORE_ADDR addr, int len, enum target_hw_bp_type type)
static CORE_ADDR mips64_linux_register_addr(struct gdbarch *gdbarch, int regno, int store)
static int have_ptrace_regsets
void mips_fill_gregset(const struct regcache *regcache, mips_elf_gregset_t *gregsetp, int regno)
void mips_supply_gregset(struct regcache *regcache, const mips_elf_gregset_t *gregsetp)
int mips_linux_restart_reg_p(struct gdbarch *gdbarch)
void mips64_fill_gregset(const struct regcache *regcache, mips64_elf_gregset_t *gregsetp, int regno)
void mips64_fill_fpregset(const struct regcache *regcache, mips64_elf_fpregset_t *fpregsetp, int regno)
void mips64_supply_fpregset(struct regcache *regcache, const mips64_elf_fpregset_t *fpregsetp)
void mips64_supply_gregset(struct regcache *regcache, const mips64_elf_gregset_t *gregsetp)
mips64_elf_greg_t mips64_elf_gregset_t[MIPS64_ELF_NGREG]
#define MIPS64_CAUSE
#define MIPS64_BADVADDR
#define DSP_CONTROL
#define MMLO
#define MMHI
#define MIPS64_MMLO
#define PC
#define FPC_CSR
#define MIPS64_FPC_CSR
mips_elf_greg_t mips_elf_gregset_t[ELF_NGREG]
#define MIPS64_FPC_EIR
#define CAUSE
#define DSP_BASE
#define BADVADDR
#define MIPS64_MMHI
#define MIPS64_FPR_BASE
#define MIPS64_PC
@ MIPS_RESTART_REGNUM
#define FPC_EIR
mips64_elf_fpreg_t mips64_elf_fpregset_t[MIPS64_ELF_NFPREG]
#define FPR_BASE
CORE_ADDR mips_linux_watch_get_watchlo(struct pt_watch_regs *regs, int n)
void mips_linux_watch_set_watchlo(struct pt_watch_regs *regs, int n, CORE_ADDR value)
uint32_t mips_linux_watch_get_irw_mask(struct pt_watch_regs *regs, int n)
uint32_t mips_linux_watch_get_num_valid(struct pt_watch_regs *regs)
uint32_t mips_linux_watch_type_to_irw(enum target_hw_bp_type type)
int mips_linux_watch_try_one_watch(struct pt_watch_regs *regs, CORE_ADDR addr, int len, uint32_t irw)
void mips_linux_watch_populate_regs(struct mips_watchpoint *current_watches, struct pt_watch_regs *regs)
int mips_linux_read_watch_registers(long lwpid, struct pt_watch_regs *watch_readback, int *watch_readback_valid, int force)
uint32_t mips_linux_watch_get_watchhi(struct pt_watch_regs *regs, int n)
#define R_MASK
uint32_t num_valid
#define MAX_DEBUG_REGISTER
#define W_MASK
#define PTRACE_SET_WATCH_REGS
const struct target_desc * tdesc_mips_linux
Definition mips-linux.c:8
const struct mips_regnum * mips_regnum(struct gdbarch *gdbarch)
Definition mips-tdep.c:228
unsigned int mips_abi_regsize(struct gdbarch *gdbarch)
Definition mips-tdep.c:309
int mips_isa_regsize(struct gdbarch *gdbarch)
Definition mips-tdep.c:290
@ MIPS_ZERO_REGNUM
Definition mips-tdep.h:135
const struct target_desc * tdesc_mips64_dsp_linux
const struct target_desc * tdesc_mips64_linux
Definition mips64-linux.c:8
#define PTRACE_GETREGS
#define PTRACE_GETFPREGS
#define PTRACE_SETREGS
#define PTRACE_SETFPREGS
int register_size(struct gdbarch *gdbarch, int regnum)
Definition regcache.c:170
void(* func)(remote_target *remote, char *)
enum var_types type
Definition scm-param.c:142
ptid_t ptid
Definition linux-nat.h:211
int fp_implementation_revision
Definition mips-tdep.h:74
int fp_control_status
Definition mips-tdep.h:75
enum target_hw_bp_type type
struct mips_watchpoint * next
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
Definition utils.c:3166
void gdb_printf(struct ui_file *stream, const char *format,...)
Definition utils.c:1886
void gdb_puts(const char *linebuffer, struct ui_file *stream)
Definition utils.c:1809
#define gdb_stdlog
Definition utils.h:190