50#include "count-one-bits.h"
55#include "sim/sim-arm.h"
58#include "coff/internal.h"
68#include "gdbsupport/selftest.h"
75#define arm_debug_printf(fmt, ...) \
76 debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__)
85#define MSYMBOL_SET_SPECIAL(msym) \
86 (msym)->set_target_flag_1 (true)
88#define MSYMBOL_IS_SPECIAL(msym) \
89 (msym)->target_flag_1 ()
97 {
return this->value < other.
value; }
226{
"r0",
"r1",
"r2",
"r3",
227 "r4",
"r5",
"r6",
"r7",
228 "r8",
"r9",
"r10",
"r11",
229 "r12",
"sp",
"lr",
"pc",
230 "f0",
"f1",
"f2",
"f3",
231 "f4",
"f5",
"f6",
"f7",
257 int regnum, gdb_byte *buf);
260 int regnum,
const gdb_byte *buf);
316static inline ULONGEST
352 const CORE_ADDR msp_val
354 const CORE_ADDR psp_val
367 if (msp_val == cache->
msp_s)
369 else if (msp_val == cache->
msp_ns)
373 warning (_(
"Invalid state, unable to determine msp alias, assuming "
379 if (psp_val == cache->
psp_s)
381 else if (psp_val == cache->
psp_ns)
385 warning (_(
"Invalid state, unable to determine psp alias, assuming "
391 if (msp_val == cache->
sp)
393 else if (psp_val == cache->
sp)
397 warning (_(
"Invalid state, unable to determine sp alias, assuming "
412 else if (cache->
psp_s == cache->
sp)
416 warning (_(
"Invalid state, unable to determine sp alias, assuming "
467 gdb_assert_not_reached (
"Invalid SP selection");
514 gdb_assert_not_reached (
"Invalid SP selection");
567class arm_instruction_reader
571 virtual uint32_t
read (CORE_ADDR memaddr, bfd_endian byte_order)
const = 0;
576class target_arm_instruction_reader :
public arm_instruction_reader
579 uint32_t
read (CORE_ADDR memaddr, bfd_endian byte_order)
const override
588 (
struct gdbarch *
gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end,
594#define DISPLACED_STEPPING_ARCH_VERSION 5
624 return (cpsr & t_bit) != 0;
645 return (cpsr & t_bit) != 0;
666 = data->section_maps[section_idx];
669 if (!data->section_maps_sorted[section_idx])
671 std::sort (map.begin (), map.end ());
672 data->section_maps_sorted[section_idx] =
true;
676 arm_mapping_symbol_vec::const_iterator it
677 = std::lower_bound (map.begin (), map.end (), map_key);
685 if (it->value == map_key.
value)
688 *start = it->value + sec->
addr ();
693 if (it > map.begin ())
695 arm_mapping_symbol_vec::const_iterator prev_it
699 *start = prev_it->value + sec->
addr ();
700 return prev_it->type;
731 (
unsigned long) memaddr);
853 switch ((addr & 0xff000000))
905 return (val & 0x03fffffc);
927 if (strstr (
name,
"_from_thumb") != NULL)
933 if (startswith (
name,
"__truncdfsf2"))
935 if (startswith (
name,
"__aeabi_d2f"))
939 if (startswith (
name,
"__tls_get_addr"))
941 if (startswith (
name,
"__aeabi_read_tp"))
965#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
966 ((bits ((insn1), 0, 3) << 12) \
967 | (bits ((insn1), 10, 10) << 11) \
968 | (bits ((insn2), 12, 14) << 8) \
969 | bits ((insn2), 0, 7))
973#define EXTRACT_MOVW_MOVT_IMM_A(insn) \
974 ((bits ((insn), 16, 19) << 12) \
975 | bits ((insn), 0, 11))
982 unsigned int count = imm >> 7;
990 return (imm & 0xff) | ((imm & 0xff) << 16);
992 return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
994 return (imm & 0xff) | ((imm & 0xff) << 8)
995 | ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
998 return (0x80 | (imm & 0x7f)) << (32 - count);
1007 return (insn == 0x46bd
1008 || (insn & 0xff80) == 0xb000
1009 || (insn & 0xfe00) == 0xbc00);
1020 CORE_ADDR start, CORE_ADDR limit,
1029 CORE_ADDR unrecognized_pc = 0;
1031 for (i = 0; i < 16; i++)
1035 while (start < limit)
1037 unsigned short insn;
1038 gdb::optional<bool> ra_signed_state;
1042 if ((insn & 0xfe00) == 0xb400)
1052 mask = (insn & 0xff) | ((insn & 0x100) << 6);
1056 if (mask & (1 << regno))
1063 else if ((insn & 0xff80) == 0xb080)
1065 offset = (insn & 0x7f) << 2;
1074 else if ((insn & 0xf800) == 0xa800)
1076 (insn & 0xff) << 2);
1077 else if ((insn & 0xfe00) == 0x1c00
1081 else if ((insn & 0xf800) == 0x3000
1085 else if ((insn & 0xfe00) == 0x1800
1089 regs[
bits (insn, 6, 8)]);
1090 else if ((insn & 0xff00) == 0x4400
1093 int rd = (
bit (insn, 7) << 3) +
bits (insn, 0, 2);
1094 int rm =
bits (insn, 3, 6);
1095 regs[rd] =
pv_add (regs[rd], regs[rm]);
1097 else if ((insn & 0xff00) == 0x4600)
1099 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
1100 int src_reg = (insn & 0x78) >> 3;
1101 regs[dst_reg] = regs[src_reg];
1103 else if ((insn & 0xf800) == 0x9000)
1108 int regno = (insn >> 8) & 0x7;
1111 offset = (insn & 0xff) << 2;
1117 stack.
store (addr, 4, regs[regno]);
1119 else if ((insn & 0xf800) == 0x6000)
1121 int rd =
bits (insn, 0, 2);
1122 int rn =
bits (insn, 3, 5);
1125 offset =
bits (insn, 6, 10) << 2;
1131 stack.
store (addr, 4, regs[rd]);
1133 else if (((insn & 0xf800) == 0x7000
1134 || (insn & 0xf800) == 0x8000)
1138 else if ((insn & 0xf800) == 0xc800
1143 else if ((insn & 0xf800) == 0x9800
1144 || ((insn & 0xf800) == 0x6800
1148 else if ((insn & 0xffc0) == 0x0000
1149 || (insn & 0xffc0) == 0x1c00)
1153 else if ((insn & 0xf800) == 0x2000)
1157 else if ((insn & 0xf800) == 0x4800)
1160 unsigned int constant;
1163 loc = start + 4 +
bits (insn, 0, 7) * 4;
1169 unsigned short inst2;
1172 byte_order_for_code);
1173 uint32_t whole_insn = (insn << 16) | inst2;
1175 if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
1181 int j1, j2, imm1, imm2;
1183 imm1 =
sbits (insn, 0, 10);
1184 imm2 =
bits (inst2, 0, 10);
1185 j1 =
bit (inst2, 13);
1186 j2 =
bit (inst2, 11);
1188 offset = ((imm1 << 12) + (imm2 << 1));
1189 offset ^= ((!j2) << 22) | ((!j1) << 23);
1191 nextpc = start + 4 + offset;
1193 if (
bit (inst2, 12) == 0)
1194 nextpc = nextpc & 0xfffffffc;
1197 bit (inst2, 12) != 0))
1201 else if ((insn & 0xffd0) == 0xe900
1205 pv_t addr = regs[
bits (insn, 0, 3)];
1213 if (inst2 & (1 << regno))
1216 stack.
store (addr, 4, regs[regno]);
1220 regs[
bits (insn, 0, 3)] = addr;
1224 else if ((insn & 0xff20) == 0xed20
1225 && (inst2 & 0x0f00) == 0x0b00
1229 pv_t addr = regs[
bits (insn, 0, 3)];
1232 unsigned int number =
bits (inst2, 0, 7) >> 1;
1235 int vd =
bits (inst2, 12, 15) | (
bits (insn, 6, 6) << 4);
1241 for (; number > 0; number--)
1249 regs[
bits (insn, 0, 3)] = addr;
1252 else if ((insn & 0xff50) == 0xe940
1256 int regno1 =
bits (inst2, 12, 15);
1257 int regno2 =
bits (inst2, 8, 11);
1258 pv_t addr = regs[
bits (insn, 0, 3)];
1260 offset = inst2 & 0xff;
1269 stack.
store (addr, 4, regs[regno1]);
1274 regs[
bits (insn, 0, 3)] = addr;
1277 else if ((insn & 0xfff0) == 0xf8c0
1278 && (inst2 & 0x0c00) == 0x0c00
1281 int regno =
bits (inst2, 12, 15);
1282 pv_t addr = regs[
bits (insn, 0, 3)];
1284 offset = inst2 & 0xff;
1293 stack.
store (addr, 4, regs[regno]);
1296 regs[
bits (insn, 0, 3)] = addr;
1299 else if ((insn & 0xfff0) == 0xf8c0
1302 int regno =
bits (inst2, 12, 15);
1305 offset = inst2 & 0xfff;
1311 stack.
store (addr, 4, regs[regno]);
1314 else if ((insn & 0xffd0) == 0xf880
1319 else if ((insn & 0xffd0) == 0xf800
1320 && (inst2 & 0x0d00) == 0x0c00
1325 else if ((insn & 0xffd0) == 0xe890
1327 && (inst2 & 0x8000) == 0x0000
1333 else if ((insn & 0xff70) == 0xe950
1339 else if ((insn & 0xfff0) == 0xf850
1340 && (inst2 & 0x0d00) == 0x0c00
1345 else if ((insn & 0xfff0) == 0xf8d0
1350 else if ((insn & 0xfbf0) == 0xf100
1351 && (inst2 & 0x8000) == 0x0000)
1353 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1354 | (
bits (inst2, 12, 14) << 8)
1355 |
bits (inst2, 0, 7));
1357 regs[
bits (inst2, 8, 11)]
1362 else if ((insn & 0xfbf0) == 0xf200
1363 && (inst2 & 0x8000) == 0x0000)
1365 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1366 | (
bits (inst2, 12, 14) << 8)
1367 |
bits (inst2, 0, 7));
1369 regs[
bits (inst2, 8, 11)]
1373 else if ((insn & 0xfbf0) == 0xf1a0
1374 && (inst2 & 0x8000) == 0x0000)
1376 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1377 | (
bits (inst2, 12, 14) << 8)
1378 |
bits (inst2, 0, 7));
1380 regs[
bits (inst2, 8, 11)]
1385 else if ((insn & 0xfbf0) == 0xf2a0
1386 && (inst2 & 0x8000) == 0x0000)
1388 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1389 | (
bits (inst2, 12, 14) << 8)
1390 |
bits (inst2, 0, 7));
1392 regs[
bits (inst2, 8, 11)]
1396 else if ((insn & 0xfbff) == 0xf04f)
1398 unsigned int imm = ((
bits (insn, 10, 10) << 11)
1399 | (
bits (inst2, 12, 14) << 8)
1400 |
bits (inst2, 0, 7));
1402 regs[
bits (inst2, 8, 11)]
1406 else if ((insn & 0xfbf0) == 0xf240)
1414 else if (insn == 0xea5f
1415 && (inst2 & 0xf0f0) == 0)
1417 int dst_reg = (inst2 & 0x0f00) >> 8;
1418 int src_reg = inst2 & 0xf;
1419 regs[dst_reg] = regs[src_reg];
1422 else if ((insn & 0xff7f) == 0xf85f)
1425 unsigned int constant;
1428 offset =
bits (inst2, 0, 11);
1430 loc = start + 4 + offset;
1432 loc = start + 4 - offset;
1438 else if ((insn & 0xff7f) == 0xe95f)
1441 unsigned int constant;
1444 offset =
bits (inst2, 0, 7) << 2;
1446 loc = start + 4 + offset;
1448 loc = start + 4 - offset;
1457 else if (
IS_PAC (whole_insn))
1461 ra_signed_state =
true;
1468 ra_signed_state =
true;
1470 else if (
IS_BTI (whole_insn))
1474 else if (
IS_PACG (whole_insn))
1478 ra_signed_state =
true;
1484 ra_signed_state =
false;
1496 unrecognized_pc = start;
1502 && ra_signed_state.has_value ())
1507 *ra_signed_state ?
"signed" :
"not signed");
1522 unrecognized_pc = start;
1531 if (unrecognized_pc == 0)
1532 unrecognized_pc = start;
1535 return unrecognized_pc;
1564 return unrecognized_pc;
1576 unsigned int *destreg,
int *offset)
1580 unsigned int low, high, address;
1585 unsigned short insn1
1588 if ((insn1 & 0xf800) == 0x4800)
1590 *destreg =
bits (insn1, 8, 10);
1592 address = (pc & 0xfffffffc) + 4 + (
bits (insn1, 0, 7) << 2);
1594 byte_order_for_code);
1596 else if ((insn1 & 0xfbf0) == 0xf240)
1598 unsigned short insn2
1609 if ((insn1 & 0xfbc0) == 0xf2c0)
1612 *destreg =
bits (insn2, 8, 11);
1614 address = (high << 16 | low);
1623 if ((insn & 0x0e5f0000) == 0x041f0000)
1625 address =
bits (insn, 0, 11) + pc + 8;
1627 byte_order_for_code);
1629 *destreg =
bits (insn, 12, 15);
1632 else if ((insn & 0x0ff00000) == 0x03000000)
1639 if ((insn & 0x0ff00000) == 0x03400000)
1642 *destreg =
bits (insn, 12, 15);
1644 address = (high << 16 | low);
1686 unsigned int basereg;
1701 if (stack_chk_guard.
minsym == NULL
1707 unsigned int destreg;
1712 if ((insn & 0xf800) != 0x6800)
1714 if (
bits (insn, 3, 5) != basereg)
1716 destreg =
bits (insn, 0, 2);
1719 byte_order_for_code);
1721 if ((insn & 0xf800) != 0x6000)
1723 if (destreg !=
bits (insn, 0, 2))
1728 unsigned int destreg;
1733 if ((insn & 0x0e500000) != 0x04100000)
1735 if (
bits (insn, 16, 19) != basereg)
1737 destreg =
bits (insn, 12, 15);
1740 4, byte_order_for_code);
1741 if ((insn & 0x0e500000) != 0x04000000)
1743 if (
bits (insn, 12, 15) != destreg)
1749 return pc + offset + 4;
1751 return pc + offset + 8;
1772 CORE_ADDR func_addr, func_end_addr, limit_pc;
1777 bool func_addr_found
1781 bool func_is_thumb =
false;
1783 if (func_addr_found)
1785 CORE_ADDR post_prologue_pc
1789 if (post_prologue_pc)
1800 if (post_prologue_pc
1803 || startswith (cust->
producer (),
"GNU ")
1805 return post_prologue_pc;
1807 if (post_prologue_pc != 0)
1809 CORE_ADDR analyzed_limit;
1823 post_prologue_pc, NULL);
1827 NULL, target_arm_instruction_reader ());
1829 if (analyzed_limit != post_prologue_pc)
1832 return post_prologue_pc;
1850 CORE_ADDR adjustment = func_is_thumb ? 2 : 4;
1853 = func_end_addr == 0 ? limit_pc : std::min (limit_pc,
1854 func_end_addr - adjustment);
1861 target_arm_instruction_reader ());
1888 CORE_ADDR prologue_start;
1889 CORE_ADDR prologue_end;
1896 if (prologue_end > prologue_start + 64)
1898 prologue_end = prologue_start + 64;
1906 prologue_end = std::min (prologue_end, prev_pc);
1919 if ((insn & 0x0df0f000) == 0x0080d000
1921 || (insn & 0x0df0f000) == 0x0040d000
1923 || (insn & 0x0ffffff0) == 0x01a0d000
1925 || (insn & 0x0fff0000) == 0x08bd0000
1927 || (insn & 0x0fff0000) == 0x049d0000)
1943 gdb_assert ((imm & 0xfffff000) == 0);
1945 uint32_t unrotated_value = imm & 0xff;
1946 uint32_t rotate_amount = (imm & 0xf00) >> 7;
1948 if (rotate_amount == 0)
1949 return unrotated_value;
1951 return ((unrotated_value >> rotate_amount)
1952 | (unrotated_value << (32 - rotate_amount)));
1967 CORE_ADDR prologue_start, CORE_ADDR prologue_end,
1969 const arm_instruction_reader &insn_reader)
1973 CORE_ADDR offset, current_pc;
1975 CORE_ADDR unrecognized_pc = 0;
1992 for (current_pc = prologue_start;
1993 current_pc < prologue_end;
1996 uint32_t insn = insn_reader.read (current_pc, byte_order_for_code);
1998 if (insn == 0xe1a0c00d)
2003 else if ((insn & 0xfff00000) == 0xe2800000
2007 int rd =
bits (insn, 12, 15);
2011 else if ((insn & 0xfff00000) == 0xe2400000
2015 int rd =
bits (insn, 12, 15);
2019 else if ((insn & 0xffff0fff) == 0xe52d0004)
2026 regs[
bits (insn, 12, 15)]);
2029 else if ((insn & 0xffff0000) == 0xe92d0000)
2034 int mask = insn & 0xffff;
2041 if (mask & (1 << regno))
2048 else if ((insn & 0xffff0000) == 0xe54b0000
2049 || (insn & 0xffff00f0) == 0xe14b00b0
2050 || (insn & 0xffffc000) == 0xe50b0000)
2055 else if ((insn & 0xffff0000) == 0xe5cd0000
2056 || (insn & 0xffff00f0) == 0xe1cd00b0
2057 || (insn & 0xffffc000) == 0xe58d0000)
2062 else if ((insn & 0xfff00000) == 0xe8800000
2069 else if ((insn & 0xfffff000) == 0xe24cb000)
2074 else if ((insn & 0xfffff000) == 0xe24dd000)
2079 else if ((insn & 0xffff7fff) == 0xed6d0103
2090 else if ((insn & 0xffbf0fff) == 0xec2d0200
2094 int n_saved_fp_regs;
2095 unsigned int fp_start_reg, fp_bound_reg;
2100 if ((insn & 0x800) == 0x800)
2102 if ((insn & 0x40000) == 0x40000)
2103 n_saved_fp_regs = 3;
2105 n_saved_fp_regs = 1;
2109 if ((insn & 0x40000) == 0x40000)
2110 n_saved_fp_regs = 2;
2112 n_saved_fp_regs = 4;
2116 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
2117 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
2121 regs[fp_start_reg++]);
2124 else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL)
2129 CORE_ADDR dest =
BranchDest (current_pc, insn);
2136 else if ((insn & 0xf0000000) != 0xe0000000)
2146 else if ((insn & 0xfe500000) == 0xe8100000
2151 else if ((insn & 0xfc500000) == 0xe4100000
2155 else if ((insn & 0xffff0ff0) == 0xe1a00000)
2167 unrecognized_pc = current_pc;
2175 if (unrecognized_pc == 0)
2176 unrecognized_pc = current_pc;
2180 int framereg, framesize;
2212 return unrecognized_pc;
2221 CORE_ADDR prologue_start, prologue_end;
2274 if (prologue_end > prologue_start + 64)
2276 prologue_end = prologue_start + 64;
2286 CORE_ADDR frame_loc;
2287 ULONGEST return_value;
2301 prologue_end = prologue_start + 64;
2305 if (prev_pc < prologue_end)
2306 prologue_end = prev_pc;
2309 target_arm_instruction_reader ());
2317 CORE_ADDR unwound_fp, prev_sp;
2325 if (unwound_fp == 0)
2331 prev_sp = unwound_fp + cache->
framesize;
2353 if (*this_cache == NULL)
2361 if (pc <= tdep->lowest_pc)
2362 return UNWIND_OUTERMOST;
2366 return UNWIND_OUTERMOST;
2368 return UNWIND_NO_REASON;
2383 if (*this_cache == NULL)
2402static struct value *
2411 if (*this_cache == NULL)
2510 if (bfd_section_flags (osect->the_bfd_section) & SEC_ALLOC)
2512 bfd_vma start,
size;
2513 start = bfd_section_vma (osect->the_bfd_section);
2514 size = bfd_section_size (osect->the_bfd_section);
2516 if (start <= vma && vma < start +
size)
2541 asection *exidx, *extab;
2542 bfd_vma exidx_vma = 0, extab_vma = 0;
2550 exidx = bfd_get_section_by_name (
objfile->
obfd.get (),
2551 ELF_STRING_ARM_unwind);
2552 gdb::byte_vector exidx_data;
2555 exidx_vma = bfd_section_vma (exidx);
2556 exidx_data.resize (bfd_section_size (exidx));
2558 if (!bfd_get_section_contents (
objfile->
obfd.get (), exidx,
2559 exidx_data.data (), 0,
2560 exidx_data.size ()))
2564 extab = bfd_get_section_by_name (
objfile->
obfd.get (),
".ARM.extab");
2565 gdb::byte_vector extab_data;
2568 extab_vma = bfd_section_vma (extab);
2569 extab_data.resize (bfd_section_size (extab));
2571 if (!bfd_get_section_contents (
objfile->
obfd.get (), extab,
2572 extab_data.data (), 0,
2573 extab_data.size ()))
2579 data->section_maps.resize (
objfile->
obfd->section_count);
2582 for (i = 0; i < exidx_data.size () / 8; i++)
2585 bfd_vma idx = bfd_h_get_32 (
objfile->
obfd, exidx_data.data () + i * 8);
2587 exidx_data.data () + i * 8 + 4);
2588 bfd_vma
addr = 0, word = 0;
2589 int n_bytes = 0, n_words = 0;
2591 gdb_byte *entry = NULL;
2594 idx = ((idx & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2595 idx += exidx_vma + i * 8;
2608 else if ((val & 0xff000000) == 0x80000000)
2615 else if (!(val & 0x80000000))
2618 addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2619 addr += exidx_vma + i * 8 + 4;
2621 if (
addr >= extab_vma &&
addr + 4 <= extab_vma + extab_data.size ())
2624 extab_data.data () +
addr - extab_vma);
2627 if ((word & 0xff000000) == 0x80000000)
2632 else if ((word & 0xff000000) == 0x81000000
2633 || (word & 0xff000000) == 0x82000000)
2637 n_words = ((word >> 16) & 0xff);
2639 else if (!(word & 0x80000000))
2643 int gnu_personality = 0;
2646 pers = ((word & 0x7fffffff) ^ 0x40000000) - 0x40000000;
2654 static const char *personality[] =
2656 "__gcc_personality_v0",
2657 "__gxx_personality_v0",
2658 "__gcj_personality_v0",
2659 "__gnu_objc_personality_v0",
2663 CORE_ADDR pc = pers + pers_sec->
offset ();
2666 for (k = 0; personality[k]; k++)
2668 (pc, personality[k],
objfile))
2670 gnu_personality = 1;
2679 &&
addr + 4 <= extab_vma + extab_data.size ())
2683 +
addr - extab_vma));
2686 n_words = ((word >> 24) & 0xff);
2694 if (
addr < extab_vma
2695 ||
addr + 4 * n_words > extab_vma + extab_data.size ())
2696 n_words = n_bytes = 0;
2701 if (n_bytes || n_words)
2705 n_bytes + n_words * 4 + 1);
2708 *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff);
2713 extab_data.data () +
addr - extab_vma);
2716 *p++ = (gdb_byte) ((word >> 24) & 0xff);
2717 *p++ = (gdb_byte) ((word >> 16) & 0xff);
2718 *p++ = (gdb_byte) ((word >> 8) & 0xff);
2719 *p++ = (gdb_byte) (word & 0xff);
2728 new_exidx_entry.
addr = idx;
2729 new_exidx_entry.
entry = entry;
2753 std::vector<arm_exidx_entry> &map
2757 auto idx = std::lower_bound (map.begin (), map.end (), map_key);
2763 if (idx < map.end ())
2765 if (idx->addr == map_key.
addr)
2768 *start = idx->addr + sec->
addr ();
2773 if (idx > map.begin ())
2777 *start = idx->addr + sec->
addr ();
2831 if ((insn & 0xc0) == 0)
2833 int offset = insn & 0x3f;
2834 vsp += (offset << 2) + 4;
2836 else if ((insn & 0xc0) == 0x40)
2838 int offset = insn & 0x3f;
2839 vsp -= (offset << 2) + 4;
2841 else if ((insn & 0xf0) == 0x80)
2843 int mask = ((insn & 0xf) << 8) | *entry++;
2853 for (i = 0; i < 12; i++)
2854 if (mask & (1 << i))
2864 else if ((insn & 0xf0) == 0x90)
2866 int reg = insn & 0xf;
2876 else if ((insn & 0xf0) == 0xa0)
2878 int count = insn & 0x7;
2879 int pop_lr = (insn & 0x8) != 0;
2883 for (i = 0; i <= count; i++)
2896 else if (insn == 0xb0)
2907 else if (insn == 0xb1)
2909 int mask = *entry++;
2913 if (mask == 0 || mask >= 16)
2917 for (i = 0; i < 4; i++)
2918 if (mask & (1 << i))
2924 else if (insn == 0xb2)
2926 ULONGEST offset = 0;
2931 offset |= (*entry & 0x7f) << shift;
2934 while (*entry++ & 0x80);
2936 vsp += 0x204 + (offset << 2);
2938 else if (insn == 0xb3)
2940 int start = *entry >> 4;
2941 int count = (*entry++) & 0xf;
2945 if (start + count >= 16)
2949 for (i = 0; i <= count; i++)
2958 else if ((insn & 0xf8) == 0xb8)
2960 int count = insn & 0x7;
2964 for (i = 0; i <= count; i++)
2973 else if (insn == 0xc6)
2975 int start = *entry >> 4;
2976 int count = (*entry++) & 0xf;
2980 if (start + count >= 16)
2984 for (i = 0; i <= count; i++)
2990 else if (insn == 0xc7)
2992 int mask = *entry++;
2996 if (mask == 0 || mask >= 16)
3000 for (i = 0; i < 4; i++)
3001 if (mask & (1 << i))
3007 else if ((insn & 0xf8) == 0xc0)
3009 int count = insn & 0x7;
3013 for (i = 0; i <= count; i++)
3019 else if (insn == 0xc8)
3021 int start = *entry >> 4;
3022 int count = (*entry++) & 0xf;
3026 if (start + count >= 16)
3031 for (i = 0; i <= count; i++)
3037 else if (insn == 0xc9)
3039 int start = *entry >> 4;
3040 int count = (*entry++) & 0xf;
3044 for (i = 0; i <= count; i++)
3050 else if ((insn & 0xf8) == 0xd0)
3052 int count = insn & 0x7;
3056 for (i = 0; i <= count; i++)
3096 void **this_prologue_cache)
3100 CORE_ADDR addr_in_block, exidx_region, func_start;
3132 for (
int shift = 0; shift <= 1 && !exc_valid; ++shift)
3143 2, byte_order_for_code,
3145 && (insn & 0xff00) == 0xdf00 )
3154 4, byte_order_for_code,
3156 && (insn & 0x0f000000) == 0x0f000000 )
3177 if (func_start > exidx_region)
3187 *this_prologue_cache = cache;
3241 if (*this_cache == NULL)
3261static struct value *
3263 void **this_cache,
int regnum)
3265 if (*this_cache == NULL)
3282 void **this_prologue_cache)
3349 enum bfd_endian byte_order_for_code
3354 if ((insn & 0xff80) == 0x4700)
3395 if (*this_cache == NULL)
3408 void **this_prologue_cache)
3410 CORE_ADDR addr_in_block;
3412 CORE_ADDR pc, start_addr;
3476 warning (_(
"ARM M in lockup state, stack unwinding terminated."));
3489 if (lr == 0xffffffff)
3497 bool fnc_return = (((lr >> 24) & 0xff) == 0xfe);
3503 error (_(
"While unwinding an exception frame, found unexpected Link "
3504 "Register value %s that requires the security extension, "
3505 "but the extension was not found or is disabled. This "
3506 "should not happen and may be caused by corrupt data or a "
3512 warning (_(
"Non-secure to secure stack unwinding disabled."));
3520 if ((xpsr & 0x1ff) != 0)
3552 bool exc_return = (((lr >> 24) & 0xff) == 0xff);
3556 bool secure_stack_used =
false;
3557 bool default_callee_register_stacking =
false;
3558 bool exception_domain_is_secure =
false;
3562 bool process_stack_used = (
bit (lr, 2) != 0);
3566 secure_stack_used = (
bit (lr, 6) != 0);
3567 default_callee_register_stacking = (
bit (lr, 5) != 0);
3568 exception_domain_is_secure = (
bit (lr, 0) != 0);
3574 if (secure_stack_used && !exception_domain_is_secure
3577 warning (_(
"Non-secure to secure stack unwinding disabled."));
3584 if (process_stack_used)
3586 if (secure_stack_used)
3595 if (secure_stack_used)
3605 if (process_stack_used)
3674 uint32_t sp_r0_offset = 0;
3678 && (!default_callee_register_stacking || !exception_domain_is_secure))
3689 sp_r0_offset = 0x28;
3711 bool extended_frame_used = (
bit (lr, 4) == 0);
3712 if (extended_frame_used)
3719 byte_order, &fpccr))
3721 warning (_(
"Could not fetch required FPCCR content. Further "
3722 "unwinding is impossible."));
3729 byte_order, &fpcar))
3731 warning (_(
"Could not fetch FPCAR content. Further unwinding of "
3732 "FP register values will be unreliable."));
3736 bool fpccr_aspen =
bit (fpccr, 31);
3737 bool fpccr_lspen =
bit (fpccr, 30);
3738 bool fpccr_ts =
bit (fpccr, 26);
3739 bool fpccr_lspact =
bit (fpccr, 0);
3747 bool fpcar_points_to_this_frame = ((unwound_sp + sp_r0_offset + 0x20)
3749 bool read_fp_regs_from_stack = (!(fpccr_aspen && fpccr_lspen
3751 && fpcar_points_to_this_frame));
3754 if (read_fp_regs_from_stack)
3756 CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x20;
3757 for (
int i = 0; i < 8; i++)
3764 + sp_r0_offset + 0x60);
3766 if (tdep->
have_sec_ext && !default_callee_register_stacking
3770 if (read_fp_regs_from_stack)
3772 CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x68;
3773 for (
int i = 8; i < 16; i++)
3781 unwound_sp + sp_r0_offset + 0xA8);
3787 unwound_sp + sp_r0_offset + 0x68);
3794 unwound_sp + sp_r0_offset + 0x20);
3805 warning (_(
"Could not fetch required XPSR content. Further "
3806 "unwinding is impossible."));
3811 if (
bit (xpsr, 9) != 0)
3820 internal_error (_(
"While unwinding an exception frame, "
3821 "found unexpected Link Register value "
3822 "%s. This should not happen and may "
3823 "be caused by corrupt data or a bug in"
3838 if (*this_cache == NULL)
3844 return UNWIND_OUTERMOST;
3846 return UNWIND_NO_REASON;
3859 if (*this_cache == NULL)
3873static struct value *
3881 if (*this_cache == NULL)
3940 void **this_prologue_cache)
3957 "arm m exception lockup sec_fnc",
3971 if (*this_cache == NULL)
3999static struct value *
4037 else if (tdep->
is_m)
4061 CORE_ADDR ra_auth_code
4065 if (ra_auth_code != 0)
4084 bool override_with_sp_value =
false;
4092 && (cache->
msp_s == cache->
sp);
4098 && (cache->
psp_s == cache->
sp);
4102 override_with_sp_value = is_msp || is_msp_s || is_msp_ns
4103 || is_psp || is_psp_s || is_psp_ns;
4106 else if (tdep->
is_m)
4109 && (cache->
sp == cache->
msp);
4111 && (cache->
sp == cache->
psp);
4113 override_with_sp_value = is_msp || is_psp;
4116 if (override_with_sp_value)
4132 internal_error (_(
"Unexpected register %d"),
regnum);
4141 unsigned int insn, insn2;
4142 int found_return = 0, found_stack_adjust = 0;
4143 CORE_ADDR func_start, func_end;
4168 while (scan_pc < func_end && !found_return)
4176 if ((insn & 0xff80) == 0x4700)
4178 else if (insn == 0x46f7)
4182 if ((insn & 0xff00) == 0xbd00)
4198 else if (insn == 0xf85d
4199 && (insn2 & 0x0fff) == 0x0b04)
4201 if ((insn2 & 0xf000) == 0xf000)
4204 else if ((insn & 0xffbf) == 0xecbd
4205 && (insn2 & 0x0e00) == 0x0a00)
4223 if (pc - 4 < func_start)
4232 found_stack_adjust = 1;
4233 else if (insn == 0xe8bd)
4234 found_stack_adjust = 1;
4235 else if (insn == 0xf85d
4236 && (insn2 & 0x0fff) == 0x0b04)
4237 found_stack_adjust = 1;
4238 else if ((insn & 0xffbf) == 0xecbd
4239 && (insn2 & 0x0e00) == 0x0a00)
4240 found_stack_adjust = 1;
4242 return found_stack_adjust;
4251 CORE_ADDR func_start, func_end;
4266 if ((insn & 0x0ffffff0) == 0x012fff10)
4269 else if ((insn & 0x0ffffff0) == 0x01a0f000)
4272 else if ((insn & 0x0fff0000) == 0x08bd0000
4273 && (insn & 0x0000c000) != 0)
4284 if (pc < func_start + 4)
4324 memcpy (si->
data, contents,
len);
4387 internal_error (_(
"Invalid VFP CPRC type: %d."),
4409 internal_error (_(
"Invalid VFP CPRC type: %d."),
4456 case TYPE_CODE_COMPLEX:
4488 case TYPE_CODE_ARRAY:
4519 gdb_assert (count == 0);
4522 else if (count == 0)
4525 gdb_assert ((t->
length () % unitlen) == 0);
4526 return t->
length () / unitlen;
4531 case TYPE_CODE_STRUCT:
4543 if (sub_count == -1)
4549 gdb_assert (count == 0);
4552 else if (count == 0)
4555 if (t->
length () != unitlen * count)
4560 case TYPE_CODE_UNION:
4569 if (sub_count == -1)
4571 count = (count > sub_count ? count : sub_count);
4575 gdb_assert (count == 0);
4578 else if (count == 0)
4581 if (t->
length () != unitlen * count)
4605 if (c <= 0 || c > 4)
4641 struct value **args, CORE_ADDR sp,
4643 CORE_ADDR struct_addr)
4652 unsigned vfp_regs_free = (1 << 16) - 1;
4658 if (ftype->
code () == TYPE_CODE_PTR)
4688 for (argnum = 0; argnum < nargs; argnum++)
4691 struct type *arg_type;
4694 const bfd_byte *val;
4698 int may_use_core_reg = 1;
4701 len = arg_type->
length ();
4703 typecode = arg_type->
code ();
4704 val = args[argnum]->contents ().data ();
4738 may_use_core_reg = 0;
4741 shift = unit_length / 4;
4742 mask = (1 << (shift * vfp_base_count)) - 1;
4743 for (regno = 0; regno < 16; regno += shift)
4744 if (((vfp_regs_free >> regno) & mask) == mask)
4753 vfp_regs_free &= ~(mask << regno);
4754 reg_scaled = regno / shift;
4756 for (i = 0; i < vfp_base_count; i++)
4760 if (reg_char ==
'q')
4762 val + i * unit_length);
4765 xsnprintf (name_buf,
sizeof (name_buf),
"%c%d",
4766 reg_char, reg_scaled + i);
4783 if (nstack & (align - 1))
4790 if (may_use_core_reg
4799 if (TYPE_CODE_PTR == typecode
4806 bfd_byte *copy = (bfd_byte *) alloca (len);
4827 if (byte_order == BFD_ENDIAN_BIG)
4841 memset (buf, 0,
sizeof (buf));
4880 return sp & ~ (CORE_ADDR) 7;
4886 if (
flags & (1 << 0))
4888 if (
flags & (1 << 1))
4890 if (
flags & (1 << 2))
4892 if (
flags & (1 << 3))
4894 if (
flags & (1 << 4))
4945 struct type *t, *elem;
4984 struct type *t, *elem;
5115 && t->
code () == TYPE_CODE_FLT
5148 if (reg >= 0 && reg <= 15)
5155 if (reg >= 16 && reg <= 23)
5159 if (reg >= 96 && reg <= 103)
5163 if (reg >= 104 && reg <= 111)
5166 if (reg >= 112 && reg <= 127)
5180 if (reg >= 192 && reg <= 199)
5191 if (reg >= 64 && reg <= 95)
5195 xsnprintf (name_buf,
sizeof (name_buf),
"s%d", reg - 64);
5202 if (reg >= 256 && reg <= 287)
5206 xsnprintf (name_buf,
sizeof (name_buf),
"d%d", reg - 256);
5231 return SIM_ARM_R0_REGNUM + reg;
5235 return SIM_ARM_FP0_REGNUM + reg;
5239 return SIM_ARM_FPS_REGNUM + reg;
5242 internal_error (_(
"Bad REGNUM %d"),
regnum);
5284 int old_len,
int new_len)
5287 int bytes_to_read = new_len - old_len;
5289 new_buf = (gdb_byte *)
xmalloc (new_len);
5290 memcpy (new_buf + bytes_to_read, buf, old_len);
5304#define MAX_IT_BLOCK_PREFIX 14
5308#define IT_SCAN_THRESHOLD 32
5318 CORE_ADDR boundary, func_start;
5321 int i, any, last_it, last_it_count;
5344 && func_start > boundary)
5345 boundary = func_start;
5356 buf = (gdb_byte *)
xmalloc (buf_len);
5360 for (i = 0; i < buf_len; i += 2)
5363 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5396 for (i = 0; i < buf_len -
sizeof (buf) && ! definite; i += 2)
5417 buf_len = bpaddr - boundary;
5426 buf_len = bpaddr - boundary;
5437 if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0)
5442 else if (inst1 & 0x0002)
5444 else if (inst1 & 0x0004)
5458 if (last_it_count < 1)
5464 return bpaddr - buf_len + last_it;
5489#define ARM_NOP 0xe1a00000
5490#define THUMB_NOP 0x4600
5517 (
unsigned long) from);
5518 return (ULONGEST) from;
5525 regno, (
unsigned long) ret);
5539 return (ps & t_bit) == 0;
5552 val & ~(ULONGEST) 0x3);
5555 val & ~(ULONGEST) 0x1);
5573 else if ((val & 2) == 0)
5582 warning (_(
"Single-stepping BX to non-word-aligned ARM instruction."));
5643 warning (_(
"Instruction wrote to PC in an unexpected way when "
5644 "single-stepping"));
5648 internal_error (_(
"Invalid argument to displaced_write_reg"));
5656 regno, (
unsigned long) val);
5670 uint32_t lowbit = 1;
5672 while (bitmask != 0)
5676 for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1)
5682 mask = lowbit * 0xf;
5684 if ((insn & mask) == mask)
5701 (
unsigned long) insn, iname);
5710 uint16_t insn2,
const char *iname,
5714 "unmodified", insn1, insn2, iname);
5772 unsigned int rn =
bits (insn, 16, 19);
5779 dsc->
modinsn[0] = insn & 0xfff0ffff;
5790 unsigned int rn =
bits (insn1, 0, 3);
5791 unsigned int u_bit =
bit (insn1, 7);
5792 int imm12 =
bits (insn2, 0, 11);
5801 (
unsigned int) dsc->
insn_addr, u_bit ?
'+' :
'-',
5824 dsc->
modinsn[0] = insn1 & 0xfff0;
5839 ULONGEST rn_val, rm_val;
5863 unsigned int rn =
bits (insn, 16, 19);
5864 unsigned int rm =
bits (insn, 0, 3);
5871 (
unsigned long) insn);
5873 dsc->
modinsn[0] = (insn & 0xfff0fff0) | 0x1;
5897 int writeback,
unsigned int rn)
5912 rn_val = rn_val & 0xfffffffc;
5926 unsigned int rn =
bits (insn, 16, 19);
5932 (
unsigned long) insn);
5934 dsc->
modinsn[0] = insn & 0xfff0ffff;
5943 uint16_t insn2,
struct regcache *regs,
5946 unsigned int rn =
bits (insn1, 0, 3);
5950 "copro load/store", dsc);
5955 dsc->
modinsn[0] = insn1 & 0xfff0;
5989 next_insn_addr |= 0x1;
6003 unsigned int cond,
int exchange,
int link,
long offset)
6018 if (link && exchange)
6033 unsigned int cond =
bits (insn, 28, 31);
6034 int exchange = (cond == 0xf);
6035 int link = exchange ||
bit (insn, 24);
6039 (exchange) ?
"blx" : (link) ?
"bl" :
"b",
6040 (
unsigned long) insn);
6044 offset = (
bits (insn, 0, 23) << 2) | (
bit (insn, 24) << 1) | 1;
6046 offset =
bits (insn, 0, 23) << 2;
6048 if (
bit (offset, 25))
6049 offset = offset | ~0x3ffffff;
6059 uint16_t insn2,
struct regcache *regs,
6062 int link =
bit (insn2, 14);
6063 int exchange = link && !
bit (insn2, 12);
6066 int j1 =
bit (insn2, 13);
6067 int j2 =
bit (insn2, 11);
6068 int s =
sbits (insn1, 10, 10);
6069 int i1 = !(j1 ^
bit (insn1, 10));
6070 int i2 = !(j2 ^
bit (insn1, 10));
6072 if (!link && !exchange)
6074 offset = (
bits (insn2, 0, 10) << 1);
6075 if (
bit (insn2, 12))
6077 offset |= (
bits (insn1, 0, 9) << 12)
6085 offset |= (
bits (insn1, 0, 5) << 12)
6089 cond =
bits (insn1, 6, 9);
6094 offset = (
bits (insn1, 0, 9) << 12);
6095 offset |= ((i2 << 22) | (i1 << 23) | (s << 24));
6096 offset |= exchange ?
6097 (
bits (insn2, 1, 10) << 2) : (
bits (insn2, 0, 10) << 1);
6101 link ? (exchange) ?
"blx" :
"bl" :
"b",
6102 insn1, insn2, offset);
6115 unsigned int cond = 0;
6117 unsigned short bit_12_15 =
bits (insn, 12, 15);
6120 if (bit_12_15 == 0xd)
6123 offset =
sbits ((insn << 1), 0, 8);
6124 cond =
bits (insn, 8, 11);
6126 else if (bit_12_15 == 0xe)
6128 offset =
sbits ((insn << 1), 0, 11);
6152 unsigned int cond,
unsigned int rm)
6176 unsigned int cond =
bits (insn, 28, 31);
6179 int link =
bit (insn, 5);
6180 unsigned int rm =
bits (insn, 0, 3);
6195 int link =
bit (insn, 7);
6196 unsigned int rm =
bits (insn, 3, 6);
6224 unsigned int rn =
bits (insn, 16, 19);
6225 unsigned int rd =
bits (insn, 12, 15);
6226 unsigned int op =
bits (insn, 21, 24);
6227 int is_mov = (op == 0xd);
6228 ULONGEST rd_val, rn_val;
6234 is_mov ?
"move" :
"ALU",
6235 (
unsigned long) insn);
6258 dsc->
modinsn[0] = insn & 0xfff00fff;
6260 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x10000;
6269 uint16_t insn2,
struct regcache *regs,
6272 unsigned int op =
bits (insn1, 5, 8);
6273 unsigned int rn, rm, rd;
6274 ULONGEST rd_val, rn_val;
6276 rn =
bits (insn1, 0, 3);
6277 rm =
bits (insn2, 0, 3);
6278 rd =
bits (insn2, 8, 11);
6281 gdb_assert (op == 0x2 && rn == 0xf);
6309 dsc->
modinsn[1] = ((insn2 & 0xf0f0) | 0x1);
6328 for (i = 0; i < 3; i++)
6337 unsigned int rd,
unsigned int rn,
unsigned int rm)
6339 ULONGEST rd_val, rn_val, rm_val;
6371 unsigned int op =
bits (insn, 21, 24);
6372 int is_mov = (op == 0xd);
6378 is_mov ?
"move" :
"ALU", (
unsigned long) insn);
6381 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x2;
6383 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x10002;
6397 rm =
bits (insn, 3, 6);
6398 rd = (
bit (insn, 7) << 3) |
bits (insn, 0, 2);
6405 dsc->
modinsn[0] = ((insn & 0xff00) | 0x10);
6422 for (i = 0; i < 4; i++)
6431 unsigned int rd,
unsigned int rn,
unsigned int rm,
6435 ULONGEST rd_val, rn_val, rm_val, rs_val;
6451 for (i = 0; i < 4; i++)
6471 unsigned int op =
bits (insn, 21, 24);
6472 int is_mov = (op == 0xd);
6473 unsigned int rd, rn, rm, rs;
6479 is_mov ?
"move" :
"ALU",
6480 (
unsigned long) insn);
6482 rn =
bits (insn, 16, 19);
6483 rm =
bits (insn, 0, 3);
6484 rs =
bits (insn, 8, 11);
6485 rd =
bits (insn, 12, 15);
6488 dsc->
modinsn[0] = (insn & 0xfff000f0) | 0x302;
6490 dsc->
modinsn[0] = (insn & 0xfff000f0) | 0x10302;
6503 ULONGEST rt_val, rt_val2 = 0, rn_val;
6555 unsigned int op1 =
bits (insn, 20, 24);
6556 unsigned int op2 =
bits (insn, 5, 6);
6557 unsigned int rt =
bits (insn, 12, 15);
6558 unsigned int rn =
bits (insn, 16, 19);
6559 unsigned int rm =
bits (insn, 0, 3);
6560 char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6561 char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6562 int immed = (op1 & 0x4) != 0;
6564 ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0;
6570 unprivileged ?
"unprivileged " :
"",
6571 (
unsigned long) insn);
6573 opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4;
6576 internal_error (_(
"copy_extra_ld_st: instruction decode error"));
6585 if (bytesize[opcode] == 8)
6592 if (bytesize[opcode] == 8)
6609 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6614 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6626 int immed,
int writeback,
int size,
int usermode,
6627 int rt,
int rm,
int rn)
6629 ULONGEST rt_val, rn_val, rm_val = 0;
6680 uint16_t insn2,
struct regcache *regs,
6683 unsigned int u_bit =
bit (insn1, 7);
6684 unsigned int rt =
bits (insn2, 12, 15);
6685 int imm12 =
bits (insn2, 0, 11);
6689 (
unsigned int) dsc->
insn_addr, rt, u_bit ?
'+' :
'-',
6710 pc_val = pc_val & 0xfffffffc;
6734 uint16_t insn2,
struct regcache *regs,
6736 int writeback,
int immed)
6738 unsigned int rt =
bits (insn2, 12, 15);
6739 unsigned int rn =
bits (insn1, 0, 3);
6740 unsigned int rm =
bits (insn2, 0, 3);
6749 rt, rn, insn1, insn2);
6761 dsc->
modinsn[0] = (insn1 & 0xfff0) | 0x2;
6762 dsc->
modinsn[1] = insn2 & 0x0fff;
6769 dsc->
modinsn[0] = (insn1 & 0xfff0) | 0x2;
6770 dsc->
modinsn[1] = (insn2 & 0x0ff0) | 0x3;
6783 int load,
int size,
int usermode)
6785 int immed = !
bit (insn, 25);
6786 int writeback = (
bit (insn, 24) == 0 ||
bit (insn, 21) != 0);
6787 unsigned int rt =
bits (insn, 12, 15);
6788 unsigned int rn =
bits (insn, 16, 19);
6789 unsigned int rm =
bits (insn, 0, 3);
6795 load ? (
size == 1 ?
"ldrb" :
"ldr")
6796 : (
size == 1 ?
"strb" :
"str"),
6797 usermode ?
"t" :
"",
6799 (
unsigned long) insn);
6802 usermode, rt, rm, rn);
6812 dsc->
modinsn[0] = (insn & 0xfff00fff) | 0x20000;
6817 dsc->
modinsn[0] = (insn & 0xfff00ff0) | 0x20003;
6831 dsc->
modinsn[5] = (insn & 0xfff00fff) | 0x20000;
6833 dsc->
modinsn[5] = (insn & 0xfff00ff0) | 0x20003;
6868 int bump_before = dsc->
u.
block.
before ? (inc ? 4 : -4) : 0;
6869 int bump_after = dsc->
u.
block.
before ? 0 : (inc ? 4 : -4);
6871 int regno = inc ? 0 : 15;
6874 && (regmask & 0x8000) != 0;
6884 if (exception_return)
6885 error (_(
"Cannot single-step exception return"));
6900 while (regno <=
ARM_PC_REGNUM && (regmask & (1 << regno)) == 0)
6903 while (regno >= 0 && (regmask & (1 << regno)) == 0)
6906 xfer_addr += bump_before;
6911 xfer_addr += bump_after;
6913 regmask &= ~(1 << regno);
6929 CORE_ADDR pc_stored_at, transferred_regs
6931 CORE_ADDR stm_insn_addr;
6937 if (!store_executed)
6957 offset = pc_val - stm_insn_addr;
6981 unsigned int regs_loaded = count_one_bits (mask);
6982 unsigned int num_to_shuffle = regs_loaded, clobbered;
6986 gdb_assert (num_to_shuffle < 16);
6991 clobbered = (1 << num_to_shuffle) - 1;
6993 while (num_to_shuffle > 0)
6995 if ((mask & (1 << write_reg)) != 0)
6997 unsigned int read_reg = num_to_shuffle - 1;
6999 if (read_reg != write_reg)
7004 read_reg, write_reg);
7008 "place", write_reg);
7010 clobbered &= ~(1 << write_reg);
7019 for (write_reg = 0; clobbered != 0; write_reg++)
7021 if ((clobbered & (1 << write_reg)) != 0)
7027 clobbered &= ~(1 << write_reg);
7037 new_rn_val += regs_loaded * 4;
7039 new_rn_val -= regs_loaded * 4;
7054 int load =
bit (insn, 20);
7055 int user =
bit (insn, 22);
7056 int increment =
bit (insn, 23);
7057 int before =
bit (insn, 24);
7058 int writeback =
bit (insn, 21);
7059 int rn =
bits (insn, 16, 19);
7068 warning (_(
"displaced: Unpredictable LDM or STM with "
7069 "base register r15"));
7074 (
unsigned long) insn);
7090 if ((insn & 0xffff) == 0xffff)
7107 unsigned int regmask = insn & 0xffff;
7108 unsigned int num_in_list = count_one_bits (regmask), new_regmask;
7111 for (i = 0; i < num_in_list; i++)
7133 new_regmask = (1 << num_in_list) - 1;
7136 "%.4x, modified list %.4x",
7137 rn, writeback ?
"!" :
"",
7138 (int) insn & 0xffff, new_regmask);
7140 dsc->
modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff);
7166 int rn =
bits (insn1, 0, 3);
7167 int load =
bit (insn1, 4);
7168 int writeback =
bit (insn1, 5);
7177 warning (_(
"displaced: Unpredictable LDM or STM with "
7178 "base register r15"));
7180 "unpredictable ldm/stm", dsc);
7208 unsigned int num_in_list = count_one_bits (regmask), new_regmask;
7211 for (i = 0; i < num_in_list; i++)
7217 new_regmask = (1 << num_in_list) - 1;
7220 "%.4x, modified list %.4x",
7221 rn, writeback ?
"!" :
"",
7225 dsc->
modinsn[1] = (new_regmask & 0xffff);
7249 (
enum bfd_endian) byte_order);
7282std::vector<CORE_ADDR>
7297 for (CORE_ADDR &pc_ref : next_pcs)
7313 (
unsigned long) resume_addr);
7349 (
unsigned long) insn);
7375 (
unsigned long) insn);
7388 (
unsigned short) insn1, (
unsigned short) insn2);
7404 (
unsigned long) insn);
7419 unsigned int op1 =
bits (insn, 20, 26), op2 =
bits (insn, 4, 7);
7420 unsigned int rn =
bits (insn, 16, 19);
7422 if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
7424 else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
7426 else if ((op1 & 0x60) == 0x20)
7428 else if ((op1 & 0x71) == 0x40)
7431 else if ((op1 & 0x77) == 0x41)
7433 else if ((op1 & 0x77) == 0x45)
7435 else if ((op1 & 0x77) == 0x51)
7442 else if ((op1 & 0x77) == 0x55)
7444 else if (op1 == 0x57)
7453 else if ((op1 & 0x63) == 0x43)
7455 else if ((op2 & 0x1) == 0x0)
7456 switch (op1 & ~0x80)
7462 case 0x71:
case 0x75:
7465 case 0x63:
case 0x67:
case 0x73:
case 0x77:
7479 if (
bit (insn, 27) == 0)
7482 else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20))
7490 case 0x4:
case 0x5:
case 0x6:
case 0x7:
7494 switch ((insn & 0xe00000) >> 21)
7496 case 0x1:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
7509 int rn_f = (
bits (insn, 16, 19) == 0xf);
7510 switch ((insn & 0xe00000) >> 21)
7520 case 0x4:
case 0x5:
case 0x6:
case 0x7:
7534 if (
bits (insn, 16, 19) == 0xf)
7564 unsigned int op2 =
bits (insn, 4, 6);
7565 unsigned int op =
bits (insn, 21, 22);
7616 switch (
bits (insn, 20, 24))
7624 case 0x12:
case 0x16:
7632 uint32_t op1 =
bits (insn, 20, 24), op2 =
bits (insn, 4, 7);
7634 if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0)
7636 else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1)
7638 else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0)
7640 else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8)
7642 else if ((op1 & 0x10) == 0x00 && op2 == 0x9)
7644 else if ((op1 & 0x10) == 0x10 && op2 == 0x9)
7646 else if (op2 == 0xb || (op2 & 0xd) == 0xd)
7661 int a =
bit (insn, 25), b =
bit (insn, 4);
7662 uint32_t op1 =
bits (insn, 20, 24);
7664 if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02)
7665 || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b))
7667 else if ((!a && (op1 & 0x17) == 0x02)
7668 || (a && (op1 & 0x17) == 0x02 && !b))
7670 else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03)
7671 || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b))
7673 else if ((!a && (op1 & 0x17) == 0x03)
7674 || (a && (op1 & 0x17) == 0x03 && !b))
7676 else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06)
7677 || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b))
7679 else if ((!a && (op1 & 0x17) == 0x06)
7680 || (a && (op1 & 0x17) == 0x06 && !b))
7682 else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07)
7683 || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b))
7685 else if ((!a && (op1 & 0x17) == 0x07)
7686 || (a && (op1 & 0x17) == 0x07 && !b))
7697 switch (
bits (insn, 20, 24))
7699 case 0x00:
case 0x01:
case 0x02:
case 0x03:
7702 case 0x04:
case 0x05:
case 0x06:
case 0x07:
7705 case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
7706 case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
7708 "decode/pack/unpack/saturate/reverse", dsc);
7711 if (
bits (insn, 5, 7) == 0)
7713 if (
bits (insn, 12, 15) == 0xf)
7721 case 0x1a:
case 0x1b:
7722 if (
bits (insn, 5, 6) == 0x2)
7727 case 0x1c:
case 0x1d:
7728 if (
bits (insn, 5, 6) == 0x0)
7730 if (
bits (insn, 0, 3) == 0xf)
7738 case 0x1e:
case 0x1f:
7739 if (
bits (insn, 5, 6) == 0x2)
7765 unsigned int opcode =
bits (insn, 20, 24);
7769 case 0x04:
case 0x05:
7772 case 0x08:
case 0x0a:
case 0x0c:
case 0x0e:
7773 case 0x12:
case 0x16:
7776 case 0x09:
case 0x0b:
case 0x0d:
case 0x0f:
7777 case 0x13:
case 0x17:
7780 case 0x10:
case 0x14:
case 0x18:
case 0x1c:
7781 case 0x11:
case 0x15:
case 0x19:
case 0x1d:
7795 uint16_t insn2,
struct regcache *regs,
7800 unsigned int op =
bits (insn1, 5, 8);
7801 unsigned int rn =
bits (insn1, 0, 3);
7803 if (op == 0x2 && rn == 0xf)
7807 "dp (shift reg)", dsc);
7816 uint16_t insn2,
struct regcache *regs,
7819 unsigned int opcode =
bits (insn1, 4, 8);
7823 case 0x04:
case 0x05:
7825 "vfp/neon vmov", dsc);
7827 case 0x08:
case 0x0c:
7828 case 0x0a:
case 0x0e:
7829 case 0x12:
case 0x16:
7831 "vfp/neon vstm/vpush", dsc);
7833 case 0x09:
case 0x0d:
7834 case 0x0b:
case 0x0f:
7835 case 0x13:
case 0x17:
7837 "vfp/neon vldm/vpop", dsc);
7839 case 0x10:
case 0x14:
case 0x18:
case 0x1c:
7842 case 0x11:
case 0x15:
case 0x19:
case 0x1d:
7854 unsigned int op1 =
bits (insn, 20, 25);
7855 int op =
bit (insn, 4);
7856 unsigned int coproc =
bits (insn, 8, 11);
7858 if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
7860 else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
7861 && (coproc & 0xe) != 0xa)
7864 else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
7865 && (coproc & 0xe) != 0xa)
7868 else if ((op1 & 0x3e) == 0x00)
7870 else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
7872 else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
7874 else if (op1 == 0x05 && (coproc & 0xe) != 0xa)
7876 else if ((op1 & 0x30) == 0x20 && !op)
7878 if ((coproc & 0xe) == 0xa)
7883 else if ((op1 & 0x30) == 0x20 && op)
7885 else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa)
7887 else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa)
7889 else if ((op1 & 0x30) == 0x30)
7897 uint16_t insn2,
struct regcache *regs,
7900 unsigned int coproc =
bits (insn2, 8, 11);
7901 unsigned int bit_5_8 =
bits (insn1, 5, 8);
7902 unsigned int bit_9 =
bit (insn1, 9);
7903 unsigned int bit_4 =
bit (insn1, 4);
7909 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7911 else if (bit_5_8 == 0)
7916 if ((coproc & 0xe) == 0xa)
7957 int rd,
unsigned int imm)
7961 dsc->
modinsn[0] = (0x3000 | (rd << 8) | imm);
7973 unsigned int rd =
bits (insn, 8, 10);
7974 unsigned int imm8 =
bits (insn, 0, 7);
7984 uint16_t insn2,
struct regcache *regs,
7987 unsigned int rd =
bits (insn2, 8, 11);
7992 unsigned int imm_3_8 = insn2 & 0x70ff;
7993 unsigned int imm_i = insn1 & 0x0400;
7996 rd, imm_i, imm_3_8, insn1, insn2);
8001 dsc->
modinsn[0] = (0xf1a0 | rd | imm_i);
8002 dsc->
modinsn[1] = ((rd << 8) | imm_3_8);
8007 dsc->
modinsn[0] = (0xf100 | rd | imm_i);
8008 dsc->
modinsn[1] = ((rd << 8) | imm_3_8);
8022 unsigned int rt =
bits (insn1, 8, 10);
8024 int imm8 = (
bits (insn1, 0, 7) << 2);
8043 pc = pc & 0xfffffffc;
8069 int non_zero =
bit (insn1, 11);
8070 unsigned int imm5 = (
bit (insn1, 9) << 6) | (
bits (insn1, 3, 7) << 1);
8072 int rn =
bits (insn1, 0, 2);
8075 dsc->
u.
branch.
cond = (rn_val && non_zero) || (!rn_val && !non_zero);
8091 non_zero ?
"cbnz" :
"cbz",
8103 uint16_t insn2,
struct regcache *regs,
8106 ULONGEST rn_val, rm_val;
8107 int is_tbh =
bit (insn2, 4);
8108 CORE_ADDR halfwords = 0;
8130 is_tbh ?
"tbh" :
"tbb",
8131 (
unsigned int) rn_val, (
unsigned int) rm_val,
8132 (
unsigned int) halfwords);
8196 dsc->
modinsn[0] = (insn1 & 0xfeff);
8205 unsigned int num_in_list = count_one_bits (dsc->
u.
block.
regmask);
8207 unsigned int new_regmask;
8209 for (i = 0; i < num_in_list + 1; i++)
8212 new_regmask = (1 << (num_in_list + 1)) - 1;
8215 "modified list %.4x",
8222 dsc->
modinsn[0] = (insn1 & ~0x1ff) | (new_regmask & 0xff);
8235 unsigned short op_bit_12_15 =
bits (insn1, 12, 15);
8236 unsigned short op_bit_10_11 =
bits (insn1, 10, 11);
8240 switch (op_bit_12_15)
8243 case 0:
case 1:
case 2:
case 3:
8245 "shift/add/sub/mov/cmp",
8249 switch (op_bit_10_11)
8258 unsigned short op =
bits (insn1, 7, 9);
8259 if (op == 6 || op == 7)
8261 else if (
bits (insn1, 6, 7) != 0)
8272 case 5:
case 6:
case 7:
case 8:
case 9:
8276 if (op_bit_10_11 < 2)
8283 switch (
bits (insn1, 8, 11))
8285 case 1:
case 3:
case 9:
case 11:
8295 if (
bits (insn1, 0, 3))
8310 if (op_bit_10_11 < 2)
8316 if (
bits (insn1, 9, 11) != 7)
8329 internal_error (_(
"thumb_process_displaced_16bit_insn: Instruction decode error"));
8334 uint16_t insn1, uint16_t insn2,
8338 int rt =
bits (insn2, 12, 15);
8339 int rn =
bits (insn1, 0, 3);
8340 int op1 =
bits (insn1, 7, 8);
8342 switch (
bits (insn1, 5, 6))
8361 "ldrb{reg, immediate}/ldrbt",
8369 "pld/unalloc memhint", dsc);
8382 int insn2_bit_8_11 =
bits (insn2, 8, 11);
8386 else if (op1 == 0x1)
8391 if (insn2_bit_8_11 == 0xc || (insn2_bit_8_11 & 0x9) == 0x9)
8394 dsc,
bit (insn2, 8), 1);
8395 else if (insn2_bit_8_11 == 0xe)
8414 uint16_t insn2,
struct regcache *regs,
8418 unsigned short op =
bit (insn2, 15);
8419 unsigned int op1 =
bits (insn1, 11, 12);
8425 switch (
bits (insn1, 9, 10))
8431 if (
bits (insn1, 7, 8) == 1 &&
bits (insn1, 4, 5) == 1
8432 &&
bits (insn2, 5, 7) == 0)
8439 "load/store dual/ex", dsc);
8443 switch (
bits (insn1, 7, 8))
8472 || (
bits (insn1, 7, 9) != 0x7))
8482 int dp_op =
bits (insn1, 4, 8);
8483 int rn =
bits (insn1, 0, 3);
8484 if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf)
8497 switch (
bits (insn1, 9, 10))
8505 "neon elt/struct load/store",
8509 switch (
bits (insn1, 7, 8))
8517 "mul/mua/diff", dsc);
8535 internal_error (_(
"thumb_process_displaced_32bit_insn: Instruction decode error"));
8549 insn1, (
unsigned long) from);
8565 CORE_ADDR to,
struct regcache *regs,
8587 (
unsigned long) insn, (
unsigned long) from);
8589 if ((insn & 0xf0000000) == 0xf0000000)
8591 else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24))
8593 case 0x0:
case 0x1:
case 0x2:
case 0x3:
8597 case 0x4:
case 0x5:
case 0x6:
8605 case 0x8:
case 0x9:
case 0xa:
case 0xb:
8609 case 0xc:
case 0xd:
case 0xe:
case 0xf:
8615 internal_error (_(
"arm_process_displaced_insn: Instruction decode error"));
8626 unsigned int i, len, offset;
8629 const gdb_byte *bkp_insn;
8633 for (i = 0; i < dsc->
numinsns; i++)
8637 dsc->
modinsn[i], (
unsigned long) to + offset);
8640 (
unsigned short) dsc->
modinsn[i],
8641 (
unsigned long) to + offset);
8674 CORE_ADDR from, CORE_ADDR to,
8675 struct regcache *regs,
bool completed_p)
8696 pc = from + (pc - to);
8725 static asymbol *asym;
8726 static combined_entry_type ce;
8727 static struct coff_symbol_struct csym;
8728 static struct bfd fake_bfd;
8729 static bfd_target fake_target;
8731 if (csym.native == NULL)
8739 fake_target.flavour = bfd_target_coff_flavour;
8740 fake_bfd.xvec = &fake_target;
8741 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
8743 csym.symbol.the_bfd = &fake_bfd;
8744 csym.symbol.name =
"fake";
8745 asym = (asymbol *) & csym;
8749 info->symbols = &asym;
8752 info->symbols = NULL;
8763 info->flags |= USER_SPECIFIED_MACHINE_TYPE;
8797#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8798#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8799#define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8800#define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8827 unsigned short inst1;
8844static const gdb_byte *
8861 gdb_assert_not_reached (
"unexpected arm breakpoint kind");
8891 for (CORE_ADDR pc : next_pcs)
8921 if (TYPE_CODE_FLT ==
type->
code ())
8923 switch (tdep->fp_model)
8950 internal_error (_(
"arm_extract_return_value: "
8951 "Floating point model not supported"));
8955 else if (
type->
code () == TYPE_CODE_INT
8995 memcpy (valbuf, tmpbuf,
9018 if (TYPE_CODE_STRUCT !=
code && TYPE_CODE_UNION !=
code
9019 && TYPE_CODE_ARRAY !=
code && TYPE_CODE_COMPLEX !=
code)
9074 if ((TYPE_CODE_STRUCT ==
code) || (TYPE_CODE_UNION ==
code))
9100 if (field_type_code == TYPE_CODE_FLT)
9130 const gdb_byte *valbuf)
9135 if (
type->
code () == TYPE_CODE_FLT)
9140 switch (tdep->fp_model)
9160 internal_error (_(
"arm_store_return_value: Floating "
9161 "point model not supported"));
9165 else if (
type->
code () == TYPE_CODE_INT
9170 ||
type->
code () == TYPE_CODE_ENUM)
9209 memcpy (tmpbuf, valbuf,
9224 struct value **read_value,
const gdb_byte *writebuf)
9238 gdb_byte *readbuf =
nullptr;
9239 if (read_value !=
nullptr)
9242 readbuf = (*read_value)->contents_raw ().data ();
9245 for (i = 0; i < vfp_base_count; i++)
9247 if (reg_char ==
'q')
9251 writebuf + i * unit_length);
9255 readbuf + i * unit_length);
9262 xsnprintf (name_buf,
sizeof (name_buf),
"%c%d", reg_char, i);
9274 if (valtype->
code () == TYPE_CODE_STRUCT
9275 || valtype->
code () == TYPE_CODE_UNION
9276 || valtype->
code () == TYPE_CODE_ARRAY)
9296 if (read_value !=
nullptr)
9306 else if (valtype->
code () == TYPE_CODE_COMPLEX)
9315 if (read_value !=
nullptr)
9318 gdb_byte *readbuf = (*read_value)->contents_raw ().data ();
9371 int target_len = strlen (
name) + strlen (
"__acle_se_") + 1;
9378 if (
minsym.minsym !=
nullptr)
9389 return (sec !=
nullptr
9403 CORE_ADDR start_addr;
9411 if (start_addr != 0)
9422 if (startswith (
name,
"_call_via_")
9423 || startswith (
name,
"__ARM_call_via_"))
9427 static const char *table[15] =
9428 {
"r0",
"r1",
"r2",
"r3",
"r4",
"r5",
"r6",
"r7",
9429 "r8",
"r9",
"sl",
"fp",
"ip",
"sp",
"lr"
9432 int offset = strlen (
name) - 2;
9434 for (regno = 0; regno <= 14; regno++)
9435 if (strcmp (&
name[offset], table[regno]) == 0)
9442 namelen = strlen (
name);
9443 if (
name[0] ==
'_' &&
name[1] ==
'_'
9444 && ((namelen > 2 + strlen (
"_from_thumb")
9445 && startswith (
name + namelen - strlen (
"_from_thumb"),
"_from_thumb"))
9446 || (namelen > 2 + strlen (
"_from_arm")
9447 && startswith (
name + namelen - strlen (
"_from_arm"),
"_from_arm"))))
9450 int target_len = namelen - 2;
9455 if (
name[namelen - 1] ==
'b')
9456 target_len -= strlen (
"_from_thumb");
9458 target_len -= strlen (
"_from_arm");
9467 if (minsym.
minsym != NULL)
9492 internal_error (_(
"could not update architecture"));
9509 internal_error (_(
"Invalid fp model accepted: %s."),
9526The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9531The current ARM floating point model is \"%s\".\n"),
9549 internal_error (_(
"Invalid ABI accepted: %s."),
9566The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9570 gdb_printf (file, _(
"The current ARM ABI is \"%s\".\n"),
9579 _(
"The current execution mode assumed "
9580 "(when symbols are unavailable) is \"%s\".\n"),
9589 _(
"The current execution mode assumed "
9590 "(even when symbols are available) is \"%s\".\n"),
9599 _(
"Usage of non-secure to secure exception stack unwinding is %s.\n"),
9624 const char *style =
"";
9628 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
9629 if (startswith (opt,
"reg-names-"))
9631 style = &opt[strlen (
"reg-names-")];
9632 len = strcspn (style,
",");
9635 gdb_printf (file,
"The disassembly style is \"%.*s\".\n", len, style);
9646 static const char *
const s_pseudo_names[] = {
9647 "s0",
"s1",
"s2",
"s3",
"s4",
"s5",
"s6",
"s7",
9648 "s8",
"s9",
"s10",
"s11",
"s12",
"s13",
"s14",
"s15",
9649 "s16",
"s17",
"s18",
"s19",
"s20",
"s21",
"s22",
"s23",
9650 "s24",
"s25",
"s26",
"s27",
"s28",
"s29",
"s30",
"s31",
9658 static const char *
const q_pseudo_names[] = {
9659 "q0",
"q1",
"q2",
"q3",
"q4",
"q5",
"q6",
"q7",
9660 "q8",
"q9",
"q10",
"q11",
"q12",
"q13",
"q14",
"q15",
9688 return (val == C_THUMBEXT
9689 || val == C_THUMBSTAT
9690 || val == C_THUMBEXTFUNC
9691 || val == C_THUMBSTATFUNC
9692 || val == C_THUMBLABEL);
9705 elf_symbol_type *elfsym = (elf_symbol_type *) sym;
9707 if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal)
9708 == ST_BRANCH_TO_THUMB)
9723 const char *
name = bfd_asymbol_name (sym);
9727 gdb_assert (
name[0] ==
'$');
9728 if (
name[1] !=
'a' &&
name[1] !=
't' &&
name[1] !=
'd')
9736 = data->section_maps[bfd_asymbol_section (sym)->index];
9738 new_map_sym.
value = sym->value;
9742 map.push_back (new_map_sym);
9754 ULONGEST val, t_bit;
9773static enum register_status
9775 int regnum, gdb_byte *buf)
9778 gdb_byte reg_buf[8];
9779 int offset, double_regnum;
9780 enum register_status
status;
9782 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum << 1);
9795 memcpy (buf + offset, reg_buf, 8);
9797 offset = 8 - offset;
9801 memcpy (buf + offset, reg_buf, 8);
9809static enum register_status
9811 int regnum, gdb_byte *buf)
9819static enum register_status
9821 int regnum, gdb_byte *buf)
9825 gdb_byte reg_buf[8];
9826 int offset, double_regnum;
9829 gdb_assert (
regnum >= num_regs);
9841 enum register_status
status;
9845 gdb_assert (
regnum < 32);
9849 offset = (
regnum & 1) ? 0 : 4;
9851 offset = (
regnum & 1) ? 4 : 0;
9853 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum >> 1);
9859 memcpy (buf, reg_buf + offset, 4);
9873 int regnum,
const gdb_byte *buf)
9876 int offset, double_regnum;
9878 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum << 1);
9889 offset = 8 - offset;
9897 int regnum,
const gdb_byte *buf)
9907 int regnum,
const gdb_byte *buf)
9911 gdb_byte reg_buf[8];
9912 int offset, double_regnum;
9915 gdb_assert (
regnum >= num_regs);
9929 gdb_assert (
regnum < 32);
9933 offset = (
regnum & 1) ? 0 : 4;
9935 offset = (
regnum & 1) ? 4 : 0;
9937 xsnprintf (name_buf,
sizeof (name_buf),
"d%d",
regnum >> 1);
9942 memcpy (reg_buf + offset, buf, 4);
9947static struct value *
9950 const int *reg_p = (
const int *) baton;
9957 unsigned int elfosabi;
9960 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
9962 if (elfosabi == ELFOSABI_ARM)
10063 return "arm(v[^- ]*)?";
10094 bool have_sec_ext =
false;
10095 int vfp_register_count = 0;
10096 bool have_s_pseudos =
false, have_q_pseudos =
false;
10097 bool have_wmmx_registers =
false;
10098 bool have_neon =
false;
10099 bool have_fpa_registers =
true;
10100 const struct target_desc *tdesc = info.target_desc;
10101 bool have_vfp =
false;
10102 bool have_mve =
false;
10103 bool have_pacbti =
false;
10104 int mve_vpr_regnum = -1;
10106 bool have_m_profile_msp =
false;
10107 int m_profile_msp_regnum = -1;
10108 int m_profile_psp_regnum = -1;
10109 int m_profile_msp_ns_regnum = -1;
10110 int m_profile_psp_ns_regnum = -1;
10111 int m_profile_msp_s_regnum = -1;
10112 int m_profile_psp_s_regnum = -1;
10113 int tls_regnum = 0;
10120 int ei_osabi, e_flags;
10122 switch (bfd_get_flavour (info.abfd))
10124 case bfd_target_coff_flavour:
10130 case bfd_target_elf_flavour:
10131 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
10132 e_flags = elf_elfheader (info.abfd)->e_flags;
10134 if (ei_osabi == ELFOSABI_ARM)
10141 else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
10143 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
10147 case EF_ARM_EABI_UNKNOWN:
10152 case EF_ARM_EABI_VER4:
10153 case EF_ARM_EABI_VER5:
10162 switch (bfd_elf_get_obj_attr_int (info.abfd,
10166 case AEABI_VFP_args_base:
10172 case AEABI_VFP_args_vfp:
10178 case AEABI_VFP_args_toolchain:
10184 case AEABI_VFP_args_compatible:
10205 warning (_(
"unknown ARM EABI version 0x%x"), eabi_ver);
10215 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10218 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10219 Tag_CPU_arch_profile);
10226 && (attr_arch == TAG_CPU_ARCH_V6_M
10227 || attr_arch == TAG_CPU_ARCH_V6S_M
10228 || attr_arch == TAG_CPU_ARCH_V7E_M
10229 || attr_arch == TAG_CPU_ARCH_V8M_BASE
10230 || attr_arch == TAG_CPU_ARCH_V8M_MAIN
10231 || attr_arch == TAG_CPU_ARCH_V8_1M_MAIN
10232 || attr_profile ==
'M'))
10239 int attr_pac_extension
10240 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10241 Tag_PAC_extension);
10243 int attr_bti_extension
10244 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10245 Tag_BTI_extension);
10247 int attr_pacret_use
10248 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10252 = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
10255 if (attr_pac_extension != 0 || attr_bti_extension != 0
10256 || attr_pacret_use != 0 || attr_bti_use != 0)
10257 have_pacbti =
true;
10264 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
10272 case EF_ARM_SOFT_FLOAT:
10275 case EF_ARM_VFP_FLOAT:
10278 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
10284 if (e_flags & EF_ARM_BE8)
10285 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
10300 static const char *
const arm_sp_names[] = {
"r13",
"sp", NULL };
10301 static const char *
const arm_lr_names[] = {
"r14",
"lr", NULL };
10302 static const char *
const arm_pc_names[] = {
"r15",
"pc", NULL };
10304 const struct tdesc_feature *feature;
10308 "org.gnu.gdb.arm.core");
10309 if (feature == NULL)
10312 "org.gnu.gdb.arm.m-profile");
10313 if (feature == NULL)
10347 "org.gnu.gdb.arm.m-system");
10348 if (feature !=
nullptr)
10352 register_count,
"msp");
10355 warning (_(
"M-profile m-system feature is missing required register msp."));
10358 have_m_profile_msp =
true;
10359 m_profile_msp_regnum = register_count++;
10363 register_count,
"psp");
10366 warning (_(
"M-profile m-system feature is missing required register psp."));
10369 m_profile_psp_regnum = register_count++;
10374 "org.gnu.gdb.arm.fpa");
10375 if (feature != NULL)
10385 have_fpa_registers =
false;
10388 "org.gnu.gdb.xscale.iwmmxt");
10389 if (feature != NULL)
10391 static const char *
const iwmmxt_names[] = {
10392 "wR0",
"wR1",
"wR2",
"wR3",
"wR4",
"wR5",
"wR6",
"wR7",
10393 "wR8",
"wR9",
"wR10",
"wR11",
"wR12",
"wR13",
"wR14",
"wR15",
10394 "wCID",
"wCon",
"wCSSF",
"wCASF",
"",
"",
"",
"",
10395 "wCGR0",
"wCGR1",
"wCGR2",
"wCGR3",
"",
"",
"",
"",
10418 have_wmmx_registers =
true;
10425 "org.gnu.gdb.arm.vfp");
10426 if (feature != NULL)
10428 static const char *
const vfp_double_names[] = {
10429 "d0",
"d1",
"d2",
"d3",
"d4",
"d5",
"d6",
"d7",
10430 "d8",
"d9",
"d10",
"d11",
"d12",
"d13",
"d14",
"d15",
10431 "d16",
"d17",
"d18",
"d19",
"d20",
"d21",
"d22",
"d23",
10432 "d24",
"d25",
"d26",
"d27",
"d28",
"d29",
"d30",
"d31",
10438 for (i = 0; i < 32; i++)
10442 vfp_double_names[i]);
10446 if (!valid_p && i == 16)
10458 have_s_pseudos =
true;
10460 vfp_register_count = i;
10466 "org.gnu.gdb.arm.neon");
10467 if (feature != NULL)
10477 have_q_pseudos =
true;
10483 if (feature !=
nullptr)
10486 register_count,
"tpidruro");
10490 tls_regnum = register_count;
10501 if (feature !=
nullptr)
10505 register_count,
"vpr");
10508 warning (_(
"MVE feature is missing required register vpr."));
10513 mve_vpr_regnum = register_count;
10519 gdb_assert (!have_q_pseudos);
10525 have_q_pseudos =
true;
10530 "org.gnu.gdb.arm.m-profile-pacbti");
10531 if (feature !=
nullptr)
10541 have_pacbti =
true;
10546 "org.gnu.gdb.arm.secext");
10547 if (feature !=
nullptr)
10552 register_count,
"msp_ns");
10555 warning (_(
"M-profile secext feature is missing required register msp_ns."));
10558 m_profile_msp_ns_regnum = register_count++;
10562 register_count,
"psp_ns");
10565 warning (_(
"M-profile secext feature is missing required register psp_ns."));
10568 m_profile_psp_ns_regnum = register_count++;
10572 register_count,
"msp_s");
10575 warning (_(
"M-profile secext feature is missing required register msp_s."));
10578 m_profile_msp_s_regnum = register_count++;
10582 register_count,
"psp_s");
10585 warning (_(
"M-profile secext feature is missing required register psp_s."));
10588 m_profile_psp_s_regnum = register_count++;
10590 have_sec_ext =
true;
10602 = gdbarch_tdep<arm_gdbarch_tdep> (best_arch->
gdbarch);
10604 if (arm_abi !=
ARM_ABI_AUTO && arm_abi != tdep->arm_abi)
10616 if (is_m != tdep->
is_m)
10628 if (best_arch != NULL)
10637 tdep->arm_abi = arm_abi;
10638 tdep->fp_model = fp_model;
10643 gdb_assert (vfp_register_count == 0
10644 || vfp_register_count == 16
10645 || vfp_register_count == 32);
10663 if (have_m_profile_msp)
10676 switch (info.byte_order_for_code)
10678 case BFD_ENDIAN_BIG:
10686 case BFD_ENDIAN_LITTLE:
10695 internal_error (_(
"arm_gdbarch_init: bad byte order for float format"));
10824 if (tdep->
jb_pc >= 0)
10844 if (is_m && have_pacbti)
10860 int num_pseudos = 0;
10929 gdb_printf (file, _(
"arm_dump_tdep: fp_model = %i\n"),
10930 (
int) tdep->fp_model);
10931 gdb_printf (file, _(
"arm_dump_tdep: have_fpa_registers = %i\n"),
10933 gdb_printf (file, _(
"arm_dump_tdep: have_wmmx_registers = %i\n"),
10935 gdb_printf (file, _(
"arm_dump_tdep: vfp_register_count = %i\n"),
10937 gdb_printf (file, _(
"arm_dump_tdep: have_s_pseudos = %s\n"),
10939 gdb_printf (file, _(
"arm_dump_tdep: s_pseudo_base = %i\n"),
10941 gdb_printf (file, _(
"arm_dump_tdep: s_pseudo_count = %i\n"),
10943 gdb_printf (file, _(
"arm_dump_tdep: have_q_pseudos = %s\n"),
10945 gdb_printf (file, _(
"arm_dump_tdep: q_pseudo_base = %i\n"),
10947 gdb_printf (file, _(
"arm_dump_tdep: q_pseudo_count = %i\n"),
10949 gdb_printf (file, _(
"arm_dump_tdep: have_neon = %i\n"),
10951 gdb_printf (file, _(
"arm_dump_tdep: have_mve = %s\n"),
10953 gdb_printf (file, _(
"arm_dump_tdep: mve_vpr_regnum = %i\n"),
10955 gdb_printf (file, _(
"arm_dump_tdep: mve_pseudo_base = %i\n"),
10957 gdb_printf (file, _(
"arm_dump_tdep: mve_pseudo_count = %i\n"),
10959 gdb_printf (file, _(
"arm_dump_tdep: m_profile_msp_regnum = %i\n"),
10961 gdb_printf (file, _(
"arm_dump_tdep: m_profile_psp_regnum = %i\n"),
10963 gdb_printf (file, _(
"arm_dump_tdep: m_profile_msp_ns_regnum = %i\n"),
10965 gdb_printf (file, _(
"arm_dump_tdep: m_profile_psp_ns_regnum = %i\n"),
10967 gdb_printf (file, _(
"arm_dump_tdep: m_profile_msp_s_regnum = %i\n"),
10969 gdb_printf (file, _(
"arm_dump_tdep: m_profile_psp_s_regnum = %i\n"),
10971 gdb_printf (file, _(
"arm_dump_tdep: Lowest pc = 0x%lx\n"),
10973 gdb_printf (file, _(
"arm_dump_tdep: have_pacbti = %s\n"),
10975 gdb_printf (file, _(
"arm_dump_tdep: pacbti_pseudo_base = %i\n"),
10977 gdb_printf (file, _(
"arm_dump_tdep: pacbti_pseudo_count = %i\n"),
10979 gdb_printf (file, _(
"arm_dump_tdep: is_m = %s\n"),
10980 tdep->
is_m ?
"yes" :
"no");
10986static void arm_record_test (
void);
10987static void arm_analyze_prologue_test ();
10997 char regdesc[1024], *rdptr = regdesc;
10998 size_t rest =
sizeof (regdesc);
11007 bfd_target_elf_flavour,
11012 _(
"Various ARM-specific commands."),
11013 _(
"Various ARM-specific commands."),
11018 const disasm_options_t *disasm_options
11019 = &disassembler_options_arm ()->options;
11020 int num_disassembly_styles = 0;
11021 for (i = 0; disasm_options->name[i] != NULL; i++)
11022 if (startswith (disasm_options->name[i],
"reg-names-"))
11023 num_disassembly_styles++;
11027 num_disassembly_styles + 1);
11028 for (i = j = 0; disasm_options->name[i] != NULL; i++)
11029 if (startswith (disasm_options->name[i],
"reg-names-"))
11031 size_t offset = strlen (
"reg-names-");
11032 const char *style = disasm_options->name[i];
11034 if (strcmp (&style[offset],
"std") == 0)
11036 length = snprintf (rdptr, rest,
"%s - %s\n", &style[offset],
11037 disasm_options->description[i]);
11045 std::string helptext = string_printf (
"%s%s%s",
11046 _(
"The valid values are:\n"),
11048 _(
"The default is \"std\"."));
11052 _(
"Set the disassembly style."),
11053 _(
"Show the disassembly style."),
11060 _(
"Set usage of ARM 32-bit mode."),
11061 _(
"Show usage of ARM 32-bit mode."),
11062 _(
"When off, a 26-bit PC will be used."),
11070 _(
"Set the floating point type."),
11071 _(
"Show the floating point type."),
11072 _(
"auto - Determine the FP typefrom the OS-ABI.\n\
11073softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
11074fpa - FPA co-processor (GCC compiled).\n\
11075softvfp - Software FP with pure-endian doubles.\n\
11076vfp - VFP co-processor."),
11083 _(
"Show the ABI."),
11091 _(
"Set the mode assumed when symbols are unavailable."),
11092 _(
"Show the mode assumed when symbols are unavailable."),
11097 _(
"Set the mode assumed even when symbols are available."),
11098 _(
"Show the mode assumed even when symbols are available."),
11105 _(
"Set usage of non-secure to secure exception stack unwinding."),
11106 _(
"Show usage of non-secure to secure exception stack unwinding."),
11107 _(
"When on, the debugger can trigger memory access traps."),
11113 _(
"Set ARM debugging."),
11114 _(
"Show ARM debugging."),
11115 _(
"When on, arm-specific debugging is enabled."),
11121 selftests::register_test (
"arm-record", selftests::arm_record_test);
11122 selftests::register_test (
"arm_analyze_prologue", selftests::arm_analyze_prologue_test);
11129#define ARM_INSN_SIZE_BYTES 4
11130#define THUMB_INSN_SIZE_BYTES 2
11131#define THUMB2_INSN_SIZE_BYTES 4
11136#define INSN_S_L_BIT_NUM 20
11138#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
11141 unsigned int reg_len = LENGTH; \
11144 REGS = XNEWVEC (uint32_t, reg_len); \
11145 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
11150#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
11153 unsigned int mem_len = LENGTH; \
11156 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
11157 memcpy(&MEMS->len, &RECORD_BUF[0], \
11158 sizeof(struct arm_mem_r) * LENGTH); \
11164#define INSN_RECORDED(ARM_RECORD) \
11165 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
11200 uint32_t ones =
bits (insn, bit_num - 1, (bit_num -1) + (
len - 1));
11245 ULONGEST u_regval[2]= {0};
11247 uint32_t reg_src1 = 0, reg_src2 = 0;
11248 uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
11253 if (14 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
11264 u_regval[0] = u_regval[0] + 8;
11266 offset_8 = (immed_high << 4) | immed_low;
11268 if (14 == arm_insn_r->
opcode)
11270 tgt_mem_addr = u_regval[0] + offset_8;
11274 tgt_mem_addr = u_regval[0] - offset_8;
11278 record_buf_mem[0] = 2;
11279 record_buf_mem[1] = tgt_mem_addr;
11284 record_buf_mem[0] = 4;
11285 record_buf_mem[1] = tgt_mem_addr;
11286 record_buf_mem[2] = 4;
11287 record_buf_mem[3] = tgt_mem_addr + 4;
11291 else if (12 == arm_insn_r->
opcode || 8 == arm_insn_r->
opcode)
11300 if (15 == reg_src2)
11303 u_regval[0] = u_regval[0] + 8;
11306 if (12 == arm_insn_r->
opcode)
11308 tgt_mem_addr = u_regval[0] + u_regval[1];
11312 tgt_mem_addr = u_regval[1] - u_regval[0];
11316 record_buf_mem[0] = 2;
11317 record_buf_mem[1] = tgt_mem_addr;
11322 record_buf_mem[0] = 4;
11323 record_buf_mem[1] = tgt_mem_addr;
11324 record_buf_mem[2] = 4;
11325 record_buf_mem[3] = tgt_mem_addr + 4;
11329 else if (11 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
11330 || 2 == arm_insn_r->
opcode || 6 == arm_insn_r->
opcode)
11336 offset_8 = (immed_high << 4) | immed_low;
11340 if (15 == arm_insn_r->
opcode || 6 == arm_insn_r->
opcode)
11342 tgt_mem_addr = u_regval[0] + offset_8;
11346 tgt_mem_addr = u_regval[0] - offset_8;
11350 record_buf_mem[0] = 2;
11351 record_buf_mem[1] = tgt_mem_addr;
11356 record_buf_mem[0] = 4;
11357 record_buf_mem[1] = tgt_mem_addr;
11358 record_buf_mem[2] = 4;
11359 record_buf_mem[3] = tgt_mem_addr + 4;
11366 else if (9 == arm_insn_r->
opcode || 13 == arm_insn_r->
opcode
11367 || 0 == arm_insn_r->
opcode || 4 == arm_insn_r->
opcode)
11376 if (13 == arm_insn_r->
opcode || 4 == arm_insn_r->
opcode)
11378 tgt_mem_addr = u_regval[0] + u_regval[1];
11382 tgt_mem_addr = u_regval[1] - u_regval[0];
11386 record_buf_mem[0] = 2;
11387 record_buf_mem[1] = tgt_mem_addr;
11392 record_buf_mem[0] = 4;
11393 record_buf_mem[1] = tgt_mem_addr;
11394 record_buf_mem[2] = 4;
11395 record_buf_mem[3] = tgt_mem_addr + 4;
11411 uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
11412 uint32_t record_buf[8], record_buf_mem[8];
11413 uint32_t reg_src1 = 0;
11415 ULONGEST u_regval = 0;
11422 if (arm_insn_r->
cond)
11426 if (5 == ((opcode1 & 0xE0) >> 5))
11438 if (3 == opcode1 &&
bit (arm_insn_r->
arm_insn, 4))
11450 if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->
cond
11454 if (in_inclusive_range (insn_op1, 0U, 3U))
11460 else if (in_inclusive_range (insn_op1, 4U, 15U))
11476 if (!opcode1 && 2 == opcode2 && !
bit (arm_insn_r->
arm_insn, 20)
11483 if ((0 == insn_op1) || (2 == insn_op1))
11489 else if (1 == insn_op1)
11495 else if (3 == insn_op1)
11510 else if (3 == insn_op1)
11547 if (0 == insn_op1 || 1 == insn_op1)
11556 else if (2 == insn_op1)
11563 else if (3 == insn_op1)
11580 else if (3 == insn_op1)
11608 if (8 == arm_insn_r->
opcode)
11610 record_buf_mem[0] = 4;
11615 record_buf_mem[0] = 1;
11617 record_buf_mem[1] = u_regval;
11622 else if (1 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11628 else if (2 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11632 record_buf[1] = record_buf[0] + 1;
11635 else if (3 == insn_op1 && !
bit (arm_insn_r->
arm_insn, 20))
11641 else if (
bit (arm_insn_r->
arm_insn, 20) && insn_op1 <= 3)
11651 if (24 == opcode1 &&
bit (arm_insn_r->
arm_insn, 21)
11674 uint32_t record_buf[8], record_buf_mem[8];
11675 ULONGEST u_regval[2] = {0};
11677 uint32_t reg_src1 = 0;
11678 uint32_t opcode1 = 0;
11684 if (!((opcode1 & 0x19) == 0x10))
11694 else if ((arm_insn_r->
decode < 8) && ((opcode1 & 0x19) == 0x10))
11698 if (3 == arm_insn_r->
decode && 0x12 == opcode1
11702 if (9 == arm_insn_r->
opcode)
11711 else if (7 == arm_insn_r->
decode && 0x12 == opcode1)
11727 else if (1 == arm_insn_r->
decode && 0x12 == opcode1
11735 else if (1 == arm_insn_r->
decode && 0x16 == opcode1
11744 && (8 == arm_insn_r->
opcode || 10 == arm_insn_r->
opcode)
11753 else if (9 == arm_insn_r->
decode && opcode1 < 0x10)
11759 if (0 == arm_insn_r->
opcode || 1 == arm_insn_r->
opcode)
11766 else if (4 <= arm_insn_r->
opcode && 7 >= arm_insn_r->
opcode)
11775 else if (9 == arm_insn_r->
decode && opcode1 > 0x10)
11786 if (8 == arm_insn_r->
opcode)
11788 record_buf_mem[0] = 4;
11793 record_buf_mem[0] = 1;
11795 record_buf_mem[1] = u_regval[0];
11800 else if (11 == arm_insn_r->
decode || 13 == arm_insn_r->
decode
11801 || 15 == arm_insn_r->
decode)
11803 if ((opcode1 & 0x12) == 2)
11814 if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4)
11820 else if ((opcode1 & 0x05) == 0x1)
11833 else if ((opcode1 & 0x05) == 0x5)
11855 if ((opcode1 & 0x05) == 0x0)
11859 record_buf[1] = record_buf[0] + 1;
11869 else if ((opcode1 & 0x05) == 0x1)
11882 else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5)
11905 if ((opcode1 & 0x05) == 0x0)
11911 else if ((opcode1 & 0x05) == 0x1)
11924 else if ((opcode1 & 0x05) == 0x4)
11930 else if ((opcode1 & 0x05) == 0x5)
11966 uint32_t record_buf[8], record_buf_mem[8];
11971 if ((9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode)
11977 if (9 == arm_insn_r->
opcode)
11988 else if (arm_insn_r->
opcode <= 15)
12010 uint32_t record_buf[8];
12033 unsigned int op1 =
bits (arm_insn_r->
arm_insn, 20, 22);
12038 else if (op1 == 0x4)
12096 uint32_t reg_base , reg_dest;
12097 uint32_t offset_12, tgt_mem_addr;
12098 uint32_t record_buf[8], record_buf_mem[8];
12099 unsigned char wback;
12140 tgt_mem_addr = (uint32_t) u_regval + offset_12;
12145 tgt_mem_addr = (uint32_t) u_regval - offset_12;
12153 record_buf_mem[0] = 1;
12158 record_buf_mem[0] = 4;
12163 record_buf_mem[1] = tgt_mem_addr;
12165 record_buf_mem[1] = (uint32_t) u_regval;
12187 uint32_t shift_imm = 0;
12188 uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0;
12189 uint32_t offset_12 = 0, tgt_mem_addr = 0;
12190 uint32_t record_buf[8], record_buf_mem[8];
12193 ULONGEST u_regval[2];
12213 if (15 != reg_dest)
12220 record_buf[0] = reg_dest;
12239 if (15 == reg_src2)
12243 u_regval[0] = u_regval[0] + 8;
12249 tgt_mem_addr = u_regval[0] + u_regval[1];
12253 tgt_mem_addr = u_regval[1] - u_regval[0];
12256 switch (arm_insn_r->
opcode)
12270 record_buf_mem[0] = 4;
12285 record_buf_mem[0] = 1;
12289 gdb_assert_not_reached (
"no decoding pattern found");
12292 record_buf_mem[1] = tgt_mem_addr;
12295 if (9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode
12296 || 13 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
12305 record_buf[0] = reg_src2;
12327 offset_12 = u_regval[0] << shift_imm;
12331 offset_12 = (!shift_imm) ? 0 : u_regval[0] >> shift_imm;
12337 if (
bit (u_regval[0], 31))
12339 offset_12 = 0xFFFFFFFF;
12349 offset_12 = s_word >> shift_imm;
12359 offset_12 = (((
bit (u_regval[1], 29)) << 31) \
12360 | (u_regval[0]) >> 1);
12364 offset_12 = (u_regval[0] >> shift_imm) \
12366 (
sizeof(uint32_t) - shift_imm));
12371 gdb_assert_not_reached (
"no decoding pattern found");
12379 tgt_mem_addr = u_regval[1] + offset_12;
12383 tgt_mem_addr = u_regval[1] - offset_12;
12386 switch (arm_insn_r->
opcode)
12400 record_buf_mem[0] = 4;
12415 record_buf_mem[0] = 1;
12419 gdb_assert_not_reached (
"no decoding pattern found");
12422 record_buf_mem[1] = tgt_mem_addr;
12425 if (9 == arm_insn_r->
opcode || 11 == arm_insn_r->
opcode
12426 || 13 == arm_insn_r->
opcode || 15 == arm_insn_r->
opcode
12435 record_buf[0] = reg_src2;
12452 uint32_t register_count = 0, register_bits;
12453 uint32_t reg_base, addr_mode;
12454 uint32_t record_buf[24], record_buf_mem[48];
12474 while (register_bits)
12476 if (register_bits & 0x00000001)
12478 register_bits = register_bits >> 1;
12500 while (register_bits)
12502 if (register_bits & 0x00000001)
12504 register_bits = register_bits >> 1;
12511 record_buf_mem[1] = (uint32_t) u_regval
12516 record_buf_mem[1] = (uint32_t) u_regval;
12520 record_buf_mem[1] = (uint32_t) u_regval
12528 gdb_assert_not_reached (
"no decoding pattern found");
12551 uint32_t record_buf[8];
12572 _(
"Process record does not support instruction "
12573 "0x%0x at address %s.\n"),arm_insn_r->
arm_insn,
12584 uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
12585 uint32_t record_buf[4];
12594 if (bit_l && bit_c)
12596 record_buf[0] = reg_t;
12599 else if (bit_l && !bit_c)
12602 if (bits_a == 0x00)
12604 record_buf[0] = reg_t;
12608 else if (bits_a == 0x07)
12613 record_buf[0] = reg_t;
12617 else if (!bit_l && !bit_c)
12620 if (bits_a == 0x00)
12627 else if (bits_a == 0x07)
12633 else if (!bit_l && bit_c)
12636 if (!(bits_a & 0x04))
12638 record_buf[0] = (reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4))
12647 reg_v = reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4);
12654 reg_v = reg_v | (
bit (arm_insn_r->
arm_insn, 7) << 4);
12670 uint32_t opcode, single_reg;
12671 uint8_t op_vldm_vstm;
12672 uint32_t record_buf[8], record_buf_mem[128];
12673 ULONGEST u_regval = 0;
12679 op_vldm_vstm = opcode & 0x1b;
12682 if ((opcode & 0x1e) == 0x04)
12720 else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a
12721 || op_vldm_vstm == 0x12)
12723 uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count;
12724 uint32_t memory_index = 0;
12729 imm_off32 = imm_off8 << 2;
12730 memory_count = imm_off8;
12733 start_address = u_regval;
12735 start_address = u_regval - imm_off32;
12739 record_buf[0] = reg_rn;
12743 while (memory_count > 0)
12747 record_buf_mem[memory_index] = 4;
12748 record_buf_mem[memory_index + 1] = start_address;
12749 start_address = start_address + 4;
12750 memory_index = memory_index + 2;
12754 record_buf_mem[memory_index] = 4;
12755 record_buf_mem[memory_index + 1] = start_address;
12756 record_buf_mem[memory_index + 2] = 4;
12757 record_buf_mem[memory_index + 3] = start_address + 4;
12758 start_address = start_address + 8;
12759 memory_index = memory_index + 4;
12766 else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b
12767 || op_vldm_vstm == 0x13)
12769 uint32_t reg_count, reg_vd;
12770 uint32_t reg_index = 0;
12781 reg_vd = reg_vd | (bit_d << 4);
12784 record_buf[reg_index++] =
bits (arm_insn_r->
arm_insn, 16, 19);
12790 reg_count = reg_count / 2;
12791 if (single_reg && bit_d)
12798 while (reg_count > 0)
12800 record_buf[reg_index++] =
ARM_D0_REGNUM + reg_vd + reg_count - 1;
12806 else if ((opcode & 0x13) == 0x10)
12808 uint32_t start_address, reg_rn, imm_off32, imm_off8;
12809 uint32_t memory_index = 0;
12814 imm_off32 = imm_off8 << 2;
12817 start_address = u_regval + imm_off32;
12819 start_address = u_regval - imm_off32;
12823 record_buf_mem[memory_index] = 4;
12824 record_buf_mem[memory_index + 1] = start_address;
12829 record_buf_mem[memory_index] = 4;
12830 record_buf_mem[memory_index + 1] = start_address;
12831 record_buf_mem[memory_index + 2] = 4;
12832 record_buf_mem[memory_index + 3] = start_address + 4;
12837 else if ((opcode & 0x13) == 0x11)
12839 uint32_t reg_vd =
bits (arm_insn_r->
arm_insn, 12, 15);
12843 reg_vd = reg_vd | (
bit (arm_insn_r->
arm_insn, 22) << 4);
12848 reg_vd = (reg_vd << 1) |
bit (arm_insn_r->
arm_insn, 22);
12865 uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
12866 uint32_t record_buf[4];
12867 enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV};
12868 enum insn_types curr_insn_type = INSN_INV;
12877 opc1 = opc1 & ~0x04;
12885 curr_insn_type = INSN_T0;
12887 curr_insn_type = INSN_T1;
12892 curr_insn_type = INSN_T1;
12894 curr_insn_type = INSN_T2;
12898 else if (opc1 == 0x01)
12901 curr_insn_type = INSN_T1;
12903 curr_insn_type = INSN_T2;
12906 else if (opc1 == 0x02 && !(opc3 & 0x01))
12911 curr_insn_type = INSN_T0;
12913 curr_insn_type = INSN_T1;
12918 curr_insn_type = INSN_T1;
12920 curr_insn_type = INSN_T2;
12924 else if (opc1 == 0x03)
12929 curr_insn_type = INSN_T0;
12931 curr_insn_type = INSN_T1;
12936 curr_insn_type = INSN_T1;
12938 curr_insn_type = INSN_T2;
12942 else if (opc1 == 0x08)
12945 curr_insn_type = INSN_T1;
12947 curr_insn_type = INSN_T2;
12950 else if (opc1 == 0x0b)
12953 if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01))
12958 curr_insn_type = INSN_T0;
12960 curr_insn_type = INSN_T1;
12965 curr_insn_type = INSN_T1;
12967 curr_insn_type = INSN_T2;
12971 else if ((opc2 == 0x01 && opc3 == 0x01)
12972 || (opc2 == 0x00 && opc3 == 0x03))
12977 curr_insn_type = INSN_T0;
12979 curr_insn_type = INSN_T1;
12984 curr_insn_type = INSN_T1;
12986 curr_insn_type = INSN_T2;
12990 else if (opc2 == 0x01 && opc3 == 0x03)
12993 curr_insn_type = INSN_T1;
12995 curr_insn_type = INSN_T2;
12998 else if (opc2 == 0x07 && opc3 == 0x03)
13001 curr_insn_type = INSN_T1;
13003 curr_insn_type = INSN_T2;
13005 else if (opc3 & 0x01)
13008 if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c)
13011 curr_insn_type = INSN_T2;
13015 curr_insn_type = INSN_T1;
13017 curr_insn_type = INSN_T2;
13021 else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e)
13024 curr_insn_type = INSN_T1;
13026 curr_insn_type = INSN_T2;
13029 else if ((opc2 & 0x0e) == 0x02)
13030 curr_insn_type = INSN_T2;
13032 else if ((opc2 & 0x0e) == 0x04)
13033 curr_insn_type = INSN_T3;
13037 switch (curr_insn_type)
13040 reg_vd = reg_vd | (bit_d << 4);
13047 reg_vd = reg_vd | (bit_d << 4);
13053 reg_vd = (reg_vd << 1) | bit_d;
13064 gdb_assert_not_reached (
"no decoding pattern found");
13077 uint32_t op1, op1_ebit, coproc;
13083 if ((coproc & 0x0e) == 0x0a)
13090 if ((op1 & 0x3e) == 0x04)
13131 uint32_t op, op1_ebit, coproc, bits_24_25;
13133 = gdbarch_tdep<arm_gdbarch_tdep> (arm_insn_r->
gdbarch);
13143 if (bits_24_25 == 0x3)
13147 ULONGEST svc_operand, svc_number;
13149 svc_operand = (0x00ffffff & arm_insn_r->
arm_insn);
13152 svc_number = svc_operand - 0x900000;
13164 else if (bits_24_25 == 0x02)
13168 if ((coproc & 0x0e) == 0x0a)
13178 uint32_t record_buf[1];
13181 if (record_buf[0] == 15)
13198 if ((coproc & 0x0e) == 0x0a)
13212 unsigned int op1 =
bits (arm_insn_r->
arm_insn, 20, 25);
13216 if ((coproc & 0x0e) != 0x0a)
13222 else if (op1 == 4 || op1 == 5)
13224 if ((coproc & 0x0e) == 0x0a)
13235 else if (op1 == 0 || op1 == 1)
13242 if ((coproc & 0x0e) == 0x0a)
13262 uint32_t record_buf[8];
13263 uint32_t reg_src1 = 0;
13268 record_buf[1] = reg_src1;
13282 uint32_t record_buf[8];
13283 uint32_t reg_src1 = 0;
13288 record_buf[1] = reg_src1;
13302 uint32_t record_buf[8], record_buf_mem[8];
13304 uint32_t reg_src1 = 0, reg_src2 = 0;
13305 uint32_t opcode1 = 0, opcode2 = 0, opcode3 = 0;
13307 ULONGEST u_regval[2] = {0};
13316 if (in_inclusive_range (opB, 4U, 7U))
13320 record_buf[0] = reg_src1;
13323 else if (in_inclusive_range (opB, 0U, 2U))
13331 record_buf_mem[0] = 4;
13333 record_buf_mem[0] = 1;
13335 record_buf_mem[0] = 2;
13336 record_buf_mem[1] = u_regval[0] + u_regval[1];
13345 record_buf[0] = reg_src1;
13353 if ((3 == opcode2) && (!opcode3))
13363 record_buf[1] = (
bit (thumb_insn_r->
arm_insn, 7) << 3
13374 reg_src1 = reg_src1 + 8;
13377 record_buf[1] = reg_src1;
13394 uint32_t record_buf[8], record_buf_mem[8];
13396 uint32_t reg_src1 = 0;
13397 uint32_t opcode = 0, immed_5 = 0;
13399 ULONGEST u_regval = 0;
13407 record_buf[0] = reg_src1;
13416 record_buf_mem[0] = 4;
13417 record_buf_mem[1] = u_regval + (immed_5 * 4);
13434 uint32_t record_buf[8], record_buf_mem[8];
13436 uint32_t reg_src1 = 0;
13437 uint32_t opcode = 0, immed_8 = 0, immed_5 = 0;
13439 ULONGEST u_regval = 0;
13447 record_buf[0] = reg_src1;
13450 else if (1 == opcode)
13454 record_buf[0] = reg_src1;
13457 else if (2 == opcode)
13462 record_buf_mem[0] = 4;
13463 record_buf_mem[1] = u_regval + (immed_8 * 4);
13466 else if (0 == opcode)
13472 record_buf_mem[0] = 2;
13473 record_buf_mem[1] = u_regval + (immed_5 * 2);
13491 uint32_t opcode = 0;
13492 uint32_t register_bits = 0, register_count = 0;
13493 uint32_t index = 0, start_address = 0;
13494 uint32_t record_buf[24], record_buf_mem[48];
13497 ULONGEST u_regval = 0;
13501 if (opcode == 0 || opcode == 1)
13506 record_buf[0] = reg_src1;
13512 uint32_t opcode2 =
bits (thumb_insn_r->
arm_insn, 8, 11);
13541 while (register_bits)
13543 if (register_bits & 0x00000001)
13545 register_bits = register_bits >> 1;
13547 start_address = u_regval - \
13548 (4 * (
bit (thumb_insn_r->
arm_insn, 8) + register_count));
13550 while (register_count)
13552 record_buf_mem[(register_count * 2) - 1] = start_address;
13553 record_buf_mem[(register_count * 2) - 2] = 4;
13554 start_address = start_address + 4;
13569 while (register_bits)
13571 if (register_bits & 0x00000001)
13572 record_buf[index++] = register_count;
13573 register_bits = register_bits >> 1;
13593 _(
"Process record does not support instruction "
13594 "0x%0x at address %s.\n"),
13621 = gdbarch_tdep<arm_gdbarch_tdep> (thumb_insn_r->
gdbarch);
13625 uint32_t reg_src1 = 0;
13626 uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0;
13627 uint32_t index = 0, start_address = 0;
13628 uint32_t record_buf[24], record_buf_mem[48];
13630 ULONGEST u_regval = 0;
13642 while (register_bits)
13644 if (register_bits & 0x00000001)
13645 record_buf[index++] = register_count;
13646 register_bits = register_bits >> 1;
13649 record_buf[index++] = reg_src1;
13652 else if (0 == opcode2)
13659 while (register_bits)
13661 if (register_bits & 0x00000001)
13663 register_bits = register_bits >> 1;
13665 start_address = u_regval;
13667 while (register_count)
13669 record_buf_mem[(register_count * 2) - 1] = start_address;
13670 record_buf_mem[(register_count * 2) - 2] = 4;
13671 start_address = start_address + 4;
13675 else if (0x1F == opcode1)
13705 uint32_t record_buf[8];
13706 uint32_t bits_h = 0;
13710 if (2 == bits_h || 3 == bits_h)
13716 else if (1 == bits_h)
13739 uint32_t reg_rn, op;
13740 uint32_t register_bits = 0, register_count = 0;
13741 uint32_t index = 0, start_address = 0;
13742 uint32_t record_buf[24], record_buf_mem[48];
13744 ULONGEST u_regval = 0;
13749 if (0 == op || 3 == op)
13763 else if (1 == op || 2 == op)
13768 register_bits =
bits (thumb2_insn_r->
arm_insn, 0, 15);
13769 while (register_bits)
13771 if (register_bits & 0x00000001)
13772 record_buf[index++] = register_count;
13775 register_bits = register_bits >> 1;
13777 record_buf[index++] = reg_rn;
13784 register_bits =
bits (thumb2_insn_r->
arm_insn, 0, 15);
13786 while (register_bits)
13788 if (register_bits & 0x00000001)
13791 register_bits = register_bits >> 1;
13797 start_address = u_regval;
13802 start_address = u_regval - register_count * 4;
13806 while (register_count)
13808 record_buf_mem[register_count * 2 - 1] = start_address;
13809 record_buf_mem[register_count * 2 - 2] = 4;
13810 start_address = start_address + 4;
13813 record_buf[0] = reg_rn;
13834 uint32_t reg_rd, reg_rn, offset_imm;
13835 uint32_t reg_dest1, reg_dest2;
13836 uint32_t address, offset_addr;
13837 uint32_t record_buf[8], record_buf_mem[8];
13838 uint32_t op1, op2, op3;
13840 ULONGEST u_regval[2];
13848 if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
13851 record_buf[0] = reg_dest1;
13856 if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
13859 record_buf[2] = reg_dest2;
13868 if (0 == op1 && 0 == op2)
13872 address = u_regval[0] + (offset_imm * 4);
13873 record_buf_mem[0] = 4;
13874 record_buf_mem[1] = address;
13877 record_buf[0] = reg_rd;
13880 else if (1 == op1 && 0 == op2)
13883 record_buf[0] = reg_rd;
13885 address = u_regval[0];
13886 record_buf_mem[1] = address;
13891 record_buf_mem[0] = 1;
13897 record_buf_mem[0] = 2 ;
13903 address = u_regval[0];
13904 record_buf_mem[0] = 4;
13905 record_buf_mem[2] = 4;
13906 record_buf_mem[3] = address + 4;
13917 offset_addr = u_regval[0] + (offset_imm * 4);
13919 offset_addr = u_regval[0] - (offset_imm * 4);
13921 address = offset_addr;
13924 address = u_regval[0];
13926 record_buf_mem[0] = 4;
13927 record_buf_mem[1] = address;
13928 record_buf_mem[2] = 4;
13929 record_buf_mem[3] = address + 4;
13931 record_buf[0] = reg_rn;
13949 uint32_t reg_rd, op;
13950 uint32_t record_buf[8];
13955 if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
13962 record_buf[0] = reg_rd;
13979 uint32_t record_buf[8];
13983 record_buf[0] = reg_rd;
13997 uint32_t op, op1, op2;
13998 uint32_t record_buf[8];
14005 if (!(op1 & 0x2) && 0x38 == op)
14019 else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
14039 uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
14040 uint32_t address, offset_addr;
14041 uint32_t record_buf[8], record_buf_mem[8];
14044 ULONGEST u_regval[2];
14055 offset_addr = u_regval[0] + offset_imm;
14056 address = offset_addr;
14061 if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
14067 offset_addr = u_regval[1] << shift_imm;
14068 address = u_regval[0] + offset_addr;
14076 offset_addr = u_regval[0] + offset_imm;
14078 offset_addr = u_regval[0] - offset_imm;
14080 address = offset_addr;
14083 address = u_regval[0];
14092 record_buf_mem[0] = 1;
14097 record_buf_mem[0] = 2;
14102 record_buf_mem[0] = 4;
14106 gdb_assert_not_reached (
"no decoding pattern found");
14110 record_buf_mem[1] = address;
14112 record_buf[0] = reg_rn;
14127 uint32_t record_buf[8];
14128 uint32_t reg_rt, reg_rn;
14135 record_buf[0] = reg_rt;
14136 record_buf[1] = reg_rn;
14153 uint32_t record_buf[8];
14155 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
14170 uint32_t opcode1 = 0, opcode2 = 0;
14171 uint32_t record_buf[8];
14176 if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
14180 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 16, 19);
14181 record_buf[1] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
14185 else if (1 == opcode1 || 3 == opcode2)
14188 record_buf[0] =
bits (thumb2_insn_r->
arm_insn, 16, 19);
14189 record_buf[1] =
bits (thumb2_insn_r->
arm_insn, 12, 15);
14218 uint32_t l_bit, a_bit, b_bits;
14219 uint32_t record_buf[128], record_buf_mem[128];
14220 uint32_t reg_rn, reg_vd, address, f_elem;
14221 uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0;
14229 reg_vd = (
bit (thumb2_insn_r->
arm_insn, 22) << 4) | reg_vd;
14230 f_ebytes = (1 <<
bits (thumb2_insn_r->
arm_insn, 6, 7));
14231 f_elem = 8 / f_ebytes;
14235 ULONGEST u_regval = 0;
14237 address = u_regval;
14242 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
14244 if (b_bits == 0x07)
14246 else if (b_bits == 0x0a)
14248 else if (b_bits == 0x06)
14250 else if (b_bits == 0x02)
14255 for (index_r = 0; index_r < bf_regs; index_r++)
14257 for (index_e = 0; index_e < f_elem; index_e++)
14259 record_buf_mem[index_m++] = f_ebytes;
14260 record_buf_mem[index_m++] = address;
14261 address = address + f_ebytes;
14267 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
14269 if (b_bits == 0x09 || b_bits == 0x08)
14271 else if (b_bits == 0x03)
14276 for (index_r = 0; index_r < bf_regs; index_r++)
14277 for (index_e = 0; index_e < f_elem; index_e++)
14279 for (loop_t = 0; loop_t < 2; loop_t++)
14281 record_buf_mem[index_m++] = f_ebytes;
14282 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
14285 address = address + (2 * f_ebytes);
14289 else if ((b_bits & 0x0e) == 0x04)
14291 for (index_e = 0; index_e < f_elem; index_e++)
14293 for (loop_t = 0; loop_t < 3; loop_t++)
14295 record_buf_mem[index_m++] = f_ebytes;
14296 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
14299 address = address + (3 * f_ebytes);
14303 else if (!(b_bits & 0x0e))
14305 for (index_e = 0; index_e < f_elem; index_e++)
14307 for (loop_t = 0; loop_t < 4; loop_t++)
14309 record_buf_mem[index_m++] = f_ebytes;
14310 record_buf_mem[index_m++] = address + (loop_t * f_ebytes);
14313 address = address + (4 * f_ebytes);
14319 uint8_t bft_size =
bits (thumb2_insn_r->
arm_insn, 10, 11);
14321 if (bft_size == 0x00)
14323 else if (bft_size == 0x01)
14325 else if (bft_size == 0x02)
14331 if (!(b_bits & 0x0b) || b_bits == 0x08)
14334 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09)
14337 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a)
14340 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b)
14343 for (index_m = 0; index_m < thumb2_insn_r->
mem_rec_count; index_m++)
14345 record_buf_mem[index_m] = f_ebytes;
14346 record_buf_mem[index_m] = address + (index_m * f_ebytes);
14355 if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06)
14358 else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08)
14361 else if ((b_bits & 0x0e) == 0x04)
14364 else if (!(b_bits & 0x0e))
14370 if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c)
14373 else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d)
14376 else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e)
14379 else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f)
14382 for (index_r = 0; index_r < thumb2_insn_r->
reg_rec_count; index_r++)
14389 record_buf[index_r] = reg_rn;
14405 uint32_t op, op1, op2;
14413 if (!(op2 & 0x64 ))
14418 else if ((op2 & 0x64) == 0x4)
14423 else if ((op2 & 0x60) == 0x20)
14428 else if (op2 & 0x40)
14434 else if (op1 == 0x02)
14441 else if (op2 & 0x20)
14452 else if (op1 == 0x03)
14454 if (!(op2 & 0x71 ))
14459 else if (!((op2 & 0x71) ^ 0x10))
14464 else if (!((op2 & 0x67) ^ 0x01))
14469 else if (!((op2 & 0x67) ^ 0x03))
14474 else if (!((op2 & 0x67) ^ 0x05))
14479 else if (!((op2 & 0x70) ^ 0x20))
14484 else if (!((op2 & 0x78) ^ 0x30))
14489 else if (!((op2 & 0x78) ^ 0x38))
14494 else if (op2 & 0x40)
14507class abstract_instruction_reader
14513 virtual ULONGEST
read (CORE_ADDR memaddr,
const size_t len,
14514 enum bfd_endian byte_order) = 0;
14519class instruction_reader :
public abstract_instruction_reader
14522 ULONGEST
read (CORE_ADDR memaddr,
const size_t len,
14523 enum bfd_endian byte_order)
override
14571 uint32_t insn_id = 0;
14572 enum bfd_endian code_endian
14575 = reader.read (arm_record->
this_addr, insn_size, code_endian);
14582 if (arm_record->
cond == 0xf)
14588 ret = arm_handle_insn[insn_id] (arm_record);
14599 arm_record->
cond = -1;
14601 ret = thumb_handle_insn[insn_id] (arm_record);
14611 arm_record->
cond = -1;
14628 gdb_assert_not_reached (
"not a valid instruction, could not decode");
14644template<
typename T>
14645class instruction_reader_selftest :
public abstract_instruction_reader
14648 template<
size_t SIZE>
14649 instruction_reader_selftest (
const T (&insns)[
SIZE])
14650 : m_insns (insns), m_insns_size (
SIZE)
14653 ULONGEST
read (CORE_ADDR memaddr,
const size_t length,
14654 enum bfd_endian byte_order)
override
14656 SELF_CHECK (length ==
sizeof (
T));
14657 SELF_CHECK (memaddr %
sizeof (
T) == 0);
14658 SELF_CHECK ((memaddr /
sizeof (
T)) < m_insns_size);
14660 return m_insns[memaddr /
sizeof (
T)];
14665 const size_t m_insns_size;
14669arm_record_test (
void)
14672 info.bfd_arch_info = bfd_scan_arch (
"arm");
14676 SELF_CHECK (
gdbarch != NULL);
14687 static const uint16_t insns[] = {
14694 instruction_reader_selftest<uint16_t> reader (insns);
14698 SELF_CHECK (ret == 0);
14701 SELF_CHECK (arm_record.
arm_regs[0] == 3);
14707 SELF_CHECK (ret == 0);
14710 SELF_CHECK (arm_record.
arm_regs[0] == 5);
14722 static const uint32_t insns[] = {
14727 instruction_reader_selftest<uint32_t> reader (insns);
14731 SELF_CHECK (ret == 0);
14734 SELF_CHECK (arm_record.
arm_regs[0] == 7);
14746 static const uint32_t insns[] = {
14751 instruction_reader_selftest<uint32_t> reader (insns);
14755 SELF_CHECK (ret == 0);
14761class test_arm_instruction_reader :
public arm_instruction_reader
14764 explicit test_arm_instruction_reader (gdb::array_view<const uint32_t> insns)
14768 uint32_t
read (CORE_ADDR memaddr,
enum bfd_endian byte_order)
const override
14770 SELF_CHECK (memaddr % 4 == 0);
14771 SELF_CHECK (memaddr / 4 < m_insns.size ());
14773 return m_insns[memaddr / 4];
14777 const gdb::array_view<const uint32_t> m_insns;
14781arm_analyze_prologue_test ()
14783 for (bfd_endian endianness : {BFD_ENDIAN_LITTLE, BFD_ENDIAN_BIG})
14786 info.byte_order = endianness;
14787 info.byte_order_for_code = endianness;
14788 info.bfd_arch_info = bfd_scan_arch (
"arm");
14792 SELF_CHECK (
gdbarch != NULL);
14797 const uint32_t insns[] = {
14804 test_arm_instruction_reader mem_reader (insns);
14820 xfree (record->arm_regs);
14821 xfree (record->arm_mems);
14831 CORE_ADDR insn_addr)
14834 uint32_t no_of_rec = 0;
14836 ULONGEST t_bit = 0, insn_id = 0;
14838 ULONGEST u_regval = 0;
14855 instruction_reader reader;
14856 enum bfd_endian code_endian
14859 = reader.read (arm_record.
this_addr, 2, code_endian);
14867 if (!(u_regval & t_bit))
14876 if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
14895 for (no_of_rec = 0; no_of_rec < arm_record.
reg_rec_count; no_of_rec++)
14905 for (no_of_rec = 0; no_of_rec < arm_record.
mem_rec_count; no_of_rec++)
14931 if (tdesc ==
nullptr)
14947 if (tdesc ==
nullptr)
#define IS_BTI(instruction)
#define sbits(obj, st, fn)
#define bits(obj, st, fn)
void gdbarch_register(enum bfd_architecture bfd_architecture, gdbarch_init_ftype *init, gdbarch_dump_tdep_ftype *dump_tdep, gdbarch_supports_arch_info_ftype *supports_arch_info)
int default_print_insn(bfd_vma memaddr, disassemble_info *info)
int gdbarch_update_p(struct gdbarch_info info)
struct gdbarch * get_current_arch(void)
struct gdbarch * target_gdbarch(void)
static std::vector< const char * > arches
int core_addr_lessthan(CORE_ADDR lhs, CORE_ADDR rhs)
struct gdbarch_list * gdbarch_list_lookup_by_info(struct gdbarch_list *arches, const struct gdbarch_info *info)
struct gdbarch * gdbarch_find_by_info(struct gdbarch_info info)
void arm_get_next_pcs_ctor(struct arm_get_next_pcs *self, struct arm_get_next_pcs_ops *ops, int byte_order, int byte_order_for_code, int has_thumb2_breakpoint, struct regcache *regcache)
std::vector< CORE_ADDR > arm_get_next_pcs(struct arm_get_next_pcs *self)
static int thumb_copy_bx_blx_reg(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_ld_mem_hints(arm_insn_decode_record *thumb2_insn_r)
static void install_alu_shifted_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rd, unsigned int rn, unsigned int rm, unsigned rs)
static int arm_return_in_memory(struct gdbarch *gdbarch, struct type *type)
static int decode_thumb_32bit_ld_mem_hints(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_register_sim_regno(struct gdbarch *gdbarch, int regnum)
static void bx_write_pc(struct regcache *regs, ULONGEST val)
static void thumb_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_neon_quad_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
int arm_process_record(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR insn_addr)
static CORE_ADDR arm_cache_get_prev_sp_value(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep)
static int thumb_copy_unmodified_32bit(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, const char *iname, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_decode_svc_copro(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static gdb_byte * extend_buffer_earlier(gdb_byte *buf, CORE_ADDR endaddr, int old_len, int new_len)
static int arm_exidx_unwind_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static int thumb_copy_pc_relative_16bit(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int rd, unsigned int imm)
static struct value * arm_prologue_prev_register(frame_info_ptr this_frame, void **this_cache, int prev_regnum)
static int install_svc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_copy_load_literal(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int size)
ULONGEST arm_get_next_pcs_read_memory_unsigned_integer(CORE_ADDR memaddr, int len, int byte_order)
static void arm_show_unwind_secure_frames(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static void install_preload(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rn)
static bool arm_is_sgstubs_section(struct obj_section *sec)
static struct cmd_list_element * showarmcmdlist
static int arm_copy_preload(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int sbo_sbz(uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
static int thumb2_record_ps_dest_generic(arm_insn_decode_record *thumb2_insn_r)
static void arm_dwarf2_frame_init_reg(struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, frame_info_ptr this_frame)
static struct arm_prologue_cache * arm_make_epilogue_frame_cache(frame_info_ptr this_frame)
static int arm_vfp_cprc_sub_candidate(struct type *t, enum arm_vfp_cprc_base_type *base_type)
static enum arm_float_model arm_fp_model
static int thumb_32bit_copy_undef(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, arm_displaced_step_copy_insn_closure *dsc)
static void print_fpu_flags(struct ui_file *file, int flags)
static int thumb2_copy_table_branch(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_copy_b(struct gdbarch *gdbarch, uint16_t insn, arm_displaced_step_copy_insn_closure *dsc)
static void thumb_process_displaced_32bit_insn(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_alu_imm(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define REG_ALLOC(REGS, LENGTH, RECORD_BUF)
void arm_process_displaced_insn(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_svc(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_coproc_insn(arm_insn_decode_record *thumb2_insn_r)
static CORE_ADDR arm_push_dummy_call(struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr)
#define MAX_IT_BLOCK_PREFIX
static void cleanup_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_get_next_pcs_syscall_next_pc(struct arm_get_next_pcs *self)
static ULONGEST arm_type_align(gdbarch *gdbarch, struct type *t)
static int arm_record_asimd_vfp_coproc(arm_insn_decode_record *arm_insn_r)
static gdb_byte * arm_find_exidx_entry(CORE_ADDR memaddr, CORE_ADDR *start)
static struct target_desc * tdesc_arm_list[ARM_FP_TYPE_INVALID][2]
struct frame_unwind arm_m_exception_unwind
static void thumb_scan_prologue(struct gdbarch *gdbarch, CORE_ADDR prev_pc, CORE_ADDR block_addr, struct arm_prologue_cache *cache)
static int arm_record_ld_st_multiple(arm_insn_decode_record *arm_insn_r)
static int arm_breakpoint_kind_from_current_state(struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR *pcptr)
static int thumb_record_ld_st_reg_offset(arm_insn_decode_record *thumb_insn_r)
static void arm_store_return_value(struct type *type, struct regcache *regs, const gdb_byte *valbuf)
static const unsigned char op_lit0
static int arm_copy_undef(struct gdbarch *gdbarch, uint32_t insn, arm_displaced_step_copy_insn_closure *dsc)
static int arm_record_ld_st_imm_offset(arm_insn_decode_record *arm_insn_r)
static const char *const fp_model_strings[]
static enum unwind_stop_reason arm_prologue_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
static unsigned int thumb2_record_decode_insn_handler(arm_insn_decode_record *thumb2_insn_r)
static CORE_ADDR thumb_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR start, CORE_ADDR limit, struct arm_prologue_cache *cache)
static int arm_copy_extra_ld_st(struct gdbarch *gdbarch, uint32_t insn, int unprivileged, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void set_disassembly_style_sfunc(const char *, int, struct cmd_list_element *)
ULONGEST displaced_read_reg(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int regno)
static int arm_record_vdata_transfer_insn(arm_insn_decode_record *arm_insn_r)
static int arm_record_extension_space(arm_insn_decode_record *arm_insn_r)
static const struct @8 arm_register_aliases[]
static int gdb_print_insn_arm(bfd_vma memaddr, disassemble_info *info)
static void branch_write_pc(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, ULONGEST val)
static const char * arm_force_mode_string
static int thumb2_record_str_single_data(arm_insn_decode_record *thumb2_insn_r)
static int arm_decode_unconditional(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_record_ldm_stm_swi(arm_insn_decode_record *thumb_insn_r)
static int arm_record_b_bl(arm_insn_decode_record *arm_insn_r)
static void arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
#define arm_debug_printf(fmt,...)
static char * arm_disassembler_options
static ULONGEST reconstruct_t_bit(struct gdbarch *gdbarch, CORE_ADDR lr, ULONGEST psr)
static int thumb2_record_lmul_lmla_div(arm_insn_decode_record *thumb2_insn_r)
static int thumb_copy_pop_pc_16bit(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_record_branch(arm_insn_decode_record *thumb_insn_r)
#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF)
static const gdb_byte arm_default_thumb_le_breakpoint[]
static void arm_pseudo_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
#define ARM_INSN_SIZE_BYTES
static struct type * arm_neon_double_type(struct gdbarch *gdbarch)
static void arm_register_g_packet_guesses(struct gdbarch *gdbarch)
static enum arm_abi_kind arm_abi_global
static const gdb_byte arm_default_arm_be_breakpoint[]
static char arm_find_mapping_symbol(CORE_ADDR memaddr, CORE_ADDR *start)
static const char *const arm_register_names[]
static uint32_t arm_expand_immediate(uint32_t imm)
int arm_is_thumb(struct regcache *regcache)
static const char * arm_gnu_triplet_regexp(struct gdbarch *gdbarch)
static int arm_decode_ext_reg_ld_st(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static struct value * arm_dwarf2_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static int arm_decode_ld_st_word_ubyte(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_prologue_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static int skip_prologue_function(struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb)
static int coff_sym_is_thumb(int val)
static enum register_status arm_pseudo_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
static CORE_ADDR arm_normal_frame_base(frame_info_ptr this_frame, void **this_cache)
static CORE_ADDR arm_skip_cmse_entry(CORE_ADDR pc, const char *name, struct objfile *objfile)
static int arm_copy_copro_load_store(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_block_xfer(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static bool arm_is_alternative_sp_register(arm_gdbarch_tdep *tdep, int regnum)
static int arm_vfp_call_candidate(struct type *t, enum arm_vfp_cprc_base_type *base_type, int *count)
static void cleanup_alu_shifted_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_cache_init(struct arm_prologue_cache *cache, struct gdbarch *gdbarch)
static struct cmd_list_element * setarmcmdlist
static struct target_desc * tdesc_arm_mprofile_list[ARM_M_TYPE_INVALID]
static int arm_copy_unmodified(struct gdbarch *gdbarch, uint32_t insn, const char *iname, arm_displaced_step_copy_insn_closure *dsc)
static struct obj_section * arm_obj_section_from_vma(struct objfile *objfile, bfd_vma vma)
static struct type * arm_neon_quad_type(struct gdbarch *gdbarch)
static int thumb2_record_asimd_struct_ld_st(arm_insn_decode_record *thumb2_insn_r)
static int arm_decode_misc_memhint_neon(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
bool arm_unwind_secure_frames
static CORE_ADDR arm_skip_prologue(struct gdbarch *gdbarch, CORE_ADDR pc)
static void cleanup_alu_reg(struct gdbarch *gdbarch, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static bool is_pacbti_pseudo(struct gdbarch *gdbarch, int regnum)
#define INSN_RECORDED(ARM_RECORD)
static frame_unwind arm_prologue_unwind
static void cleanup_block_load_pc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
int arm_frame_is_thumb(frame_info_ptr frame)
static int thumb2_record_ld_word(arm_insn_decode_record *thumb2_insn_r)
static int thumb_record_ld_st_stack(arm_insn_decode_record *thumb_insn_r)
static void install_alu_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rd, unsigned int rn, unsigned int rm)
static bool is_mve_pseudo(struct gdbarch *gdbarch, int regnum)
static const char * arm_register_name(struct gdbarch *gdbarch, int i)
static struct value * arm_m_exception_prev_register(frame_info_ptr this_frame, void **this_cache, int prev_regnum)
static int arm_vfp_cprc_reg_char(enum arm_vfp_cprc_base_type b)
static int arm_record_unsupported_insn(arm_insn_decode_record *arm_insn_r)
static void cleanup_branch(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_copy_preload_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_branch_misc_cntrl(arm_insn_decode_record *thumb2_insn_r)
static int arm_record_vfp_data_proc_insn(arm_insn_decode_record *arm_insn_r)
static int thumb_copy_16bit_ldr_literal(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void arm_dump_tdep(struct gdbarch *gdbarch, struct ui_file *file)
static void arm_show_fallback_mode(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static int thumb_copy_svc(struct gdbarch *gdbarch, uint16_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2)
static int decode_insn(abstract_instruction_reader &reader, arm_insn_decode_record *arm_record, record_type_t record_type, uint32_t insn_size)
static CORE_ADDR arm_analyze_prologue(struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader)
static void arm_show_abi(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
static const char * current_fp_model
static void deallocate_reg_mem(arm_insn_decode_record *record)
static const gdb_byte arm_default_arm_le_breakpoint[]
static void arm_exidx_new_objfile(struct objfile *objfile)
#define EXTRACT_MOVW_MOVT_IMM_A(insn)
static const char *const arm_abi_strings[]
struct frame_unwind arm_exidx_unwind
static CORE_ADDR arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
std::vector< arm_mapping_symbol > arm_mapping_symbol_vec
static void arm_update_current_architecture(void)
static struct arm_stack_item * push_stack_item(struct arm_stack_item *prev, const gdb_byte *contents, int len)
static int thumb_copy_unmodified_16bit(struct gdbarch *gdbarch, uint16_t insn, const char *iname, arm_displaced_step_copy_insn_closure *dsc)
static void install_copro_load_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int writeback, unsigned int rn)
static int arm_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
#define THUMB_INSN_SIZE_BYTES
static int arm_record_ld_st_reg_offset(arm_insn_decode_record *arm_insn_r)
static void cleanup_preload(struct gdbarch *gdbarch, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_copy_pc_relative_32bit(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void cleanup_copro_load_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static bool is_s_pseudo(struct gdbarch *gdbarch, int regnum)
static int thumb2_decode_dp_shift_reg(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define MSYMBOL_SET_SPECIAL(msym)
static void install_load_store(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int load, int immed, int writeback, int size, int usermode, int rt, int rm, int rn)
static void cleanup_block_store_pc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_stack_frame_destroyed_p(struct gdbarch *gdbarch, CORE_ADDR pc)
int arm_pc_is_thumb(struct gdbarch *gdbarch, CORE_ADDR memaddr)
#define MSYMBOL_IS_SPECIAL(msym)
static int arm_code_of_frame_writable(struct gdbarch *gdbarch, frame_info_ptr frame)
static int thumb2_copy_block_xfer(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_skip_bx_reg(frame_info_ptr frame, CORE_ADDR pc)
static void cleanup_alu_imm(struct gdbarch *gdbarch, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_data_proc_sreg_mimm(arm_insn_decode_record *thumb2_insn_r)
static CORE_ADDR arm_frame_align(struct gdbarch *gdbarch, CORE_ADDR sp)
static int arm_m_addr_is_magic(struct gdbarch *gdbarch, CORE_ADDR addr)
static int thumb_instruction_restores_sp(unsigned short insn)
static int arm_copy_b_bl_blx(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
void _initialize_arm_tdep()
static int arm_copy_alu_shifted_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_instruction_restores_sp(unsigned int insn)
static const char * arm_fallback_mode_string
static int arm_record_strx(arm_insn_decode_record *arm_insn_r, uint32_t *record_buf, uint32_t *record_buf_mem, arm_record_strx_t str_type)
static void cleanup_load(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_ld_st_dual_ex_tbb(arm_insn_decode_record *thumb2_insn_r)
static unsigned arm_vfp_cprc_unit_length(enum arm_vfp_cprc_base_type b)
static struct arm_prologue_cache * arm_m_exception_cache(frame_info_ptr this_frame)
static int arm_record_exreg_ld_st_insn(arm_insn_decode_record *arm_insn_r)
static int arm_get_longjmp_target(frame_info_ptr frame, CORE_ADDR *pc)
static enum unwind_stop_reason arm_m_exception_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
static int thumb2_copy_b_bl_blx(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_vfp_abi_for_function(struct gdbarch *gdbarch, struct type *func_type)
static int displaced_in_arm_mode(struct regcache *regs)
static struct gdbarch * arm_gdbarch_init(struct gdbarch_info info, struct gdbarch_list *arches)
void displaced_write_reg(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc)
static int arm_stack_frame_destroyed_p_1(struct gdbarch *gdbarch, CORE_ADDR pc)
static void load_write_pc(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, ULONGEST val)
static CORE_ADDR arm_adjust_breakpoint_address(struct gdbarch *gdbarch, CORE_ADDR bpaddr)
static const registry< bfd >::key< arm_per_bfd > arm_bfd_data_key
std::vector< CORE_ADDR > arm_software_single_step(struct regcache *regcache)
static const char ** valid_disassembly_styles
static enum gdb_osabi arm_elf_osabi_sniffer(bfd *abfd)
static void arm_stub_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static int arm_epilogue_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static int thumb_record_shift_add_sub(arm_insn_decode_record *thumb_insn_r)
static void install_b_bl_blx(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int cond, int exchange, int link, long offset)
#define ARM_BE_BREAKPOINT
static struct arm_prologue_cache * arm_make_prologue_cache(frame_info_ptr this_frame)
static int arm_m_exception_unwind_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static void set_fp_model_sfunc(const char *args, int from_tty, struct cmd_list_element *c)
static bool is_q_pseudo(struct gdbarch *gdbarch, int regnum)
static int arm_record_coproc_data_proc(arm_insn_decode_record *arm_insn_r)
static const char *const arm_mode_strings[]
static struct arm_prologue_cache * arm_exidx_fill_cache(frame_info_ptr this_frame, gdb_byte *entry)
#define THUMB_BE_BREAKPOINT
static int arm_record_media(arm_insn_decode_record *arm_insn_r)
static int thumb_record_add_sub_cmp_mov(arm_insn_decode_record *thumb_insn_r)
static void arm_show_force_mode(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
int arm_psr_thumb_bit(struct gdbarch *gdbarch)
struct frame_unwind arm_stub_unwind
static void arm_record_special_symbol(struct gdbarch *gdbarch, struct objfile *objfile, asymbol *sym)
#define IT_SCAN_THRESHOLD
static void install_bx_blx_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int link, unsigned int cond, unsigned int rm)
static void thumb_process_displaced_16bit_insn(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_media(struct gdbarch *gdbarch, uint32_t insn, arm_displaced_step_copy_insn_closure *dsc)
static int thumb2_record_ld_st_multiple(arm_insn_decode_record *thumb2_insn_r)
static const gdb_byte arm_default_thumb_be_breakpoint[]
CORE_ADDR arm_get_next_pcs_addr_bits_remove(struct arm_get_next_pcs *self, CORE_ADDR val)
static unsigned int thumb_expand_immediate(unsigned int imm)
static const registry< bfd >::key< arm_exidx_data > arm_exidx_data_key
static struct arm_stack_item * pop_stack_item(struct arm_stack_item *si)
static int arm_copy_unpred(struct gdbarch *gdbarch, uint32_t insn, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_miscellaneous(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
struct frame_base arm_normal_base
static int arm_dwarf_reg_to_regnum(struct gdbarch *gdbarch, int reg)
static int insn_references_pc(uint32_t insn, uint32_t bitmask)
static int thumb2_copy_alu_imm(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define THUMB2_INSN_SIZE_BYTES
static void arm_scan_prologue(frame_info_ptr this_frame, struct arm_prologue_cache *cache)
static int thumb2_copy_copro_load_store(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_cache_get_sp_register(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, int regnum)
static void arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
static void arm_set_abi(const char *args, int from_tty, struct cmd_list_element *c)
static enum register_status arm_neon_quad_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
#define THUMB_LE_BREAKPOINT
static int thumb2_decode_ext_reg_ld_st(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_record_data_proc_imm(arm_insn_decode_record *arm_insn_r)
static int thumb2_copy_load_reg_imm(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int writeback, int immed)
const target_desc * arm_read_mprofile_description(arm_m_profile_type m_type)
static const char * arm_abi_string
static enum register_status arm_mve_pseudo_read(struct gdbarch *gdbarch, readable_regcache *regcache, int regnum, gdb_byte *buf)
static std::string arm_get_pc_address_flags(frame_info_ptr frame, CORE_ADDR pc)
static int thumb_copy_cbnz_cbz(struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static CORE_ADDR arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, unsigned int *destreg, int *offset)
static void cleanup_block_load_all(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, unsigned int rn, unsigned int rm)
static int arm_copy_bx_blx_reg(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
#define DISPLACED_STEPPING_ARCH_VERSION
static int arm_record_data_proc_misc_ld_str(arm_insn_decode_record *arm_insn_r)
void arm_displaced_init_closure(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, arm_displaced_step_copy_insn_closure *dsc)
void arm_displaced_step_fixup(struct gdbarch *gdbarch, struct displaced_step_copy_insn_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, bool completed_p)
static int arm_stub_unwind_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
static struct value * value_of_arm_user_reg(frame_info_ptr frame, const void *baton)
static void arm_extract_return_value(struct type *type, struct regcache *regs, gdb_byte *valbuf)
static int arm_copy_ldr_str_ldrb_strb(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int load, int size, int usermode)
static void install_pc_relative(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int rd)
static void arm_m_exception_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static int thumb_copy_alu_reg(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_breakpoint_kind_from_pc(struct gdbarch *gdbarch, CORE_ADDR *pcptr)
static void arm_cache_switch_prev_sp(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, int sp_regnum)
static void cleanup_svc(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int thumb_decode_pc_relative_16bit(struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void show_disassembly_style_sfunc(struct ui_file *, int, struct cmd_list_element *, const char *)
static int arm_decode_b_bl_ldmstm(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static enum return_value_convention arm_return_value(struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, struct value **read_value, const gdb_byte *writebuf)
static int arm_decode_svc_copro(struct gdbarch *gdbarch, uint32_t insn, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static const gdb_byte * arm_sw_breakpoint_from_kind(struct gdbarch *gdbarch, int kind, int *size)
static void arm_write_pc(struct regcache *regcache, CORE_ADDR pc)
static int thumb_record_ld_st_imm_offset(arm_insn_decode_record *thumb_insn_r)
static int thumb2_copy_preload(struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static int arm_decode_dp_misc(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static void show_fp_model(struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value)
CORE_ADDR arm_skip_stub(frame_info_ptr frame, CORE_ADDR pc)
static bool arm_m_addr_is_lockup(CORE_ADDR addr)
static struct type * arm_register_type(struct gdbarch *gdbarch, int regnum)
static void arm_epilogue_frame_this_id(frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id)
static CORE_ADDR arm_addr_bits_remove(struct gdbarch *gdbarch, CORE_ADDR val)
static int arm_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
static struct arm_prologue_cache * arm_make_stub_cache(frame_info_ptr this_frame)
static void alu_write_pc(regcache *regs, arm_displaced_step_copy_insn_closure *dsc, ULONGEST val)
static void cleanup_pop_pc_16bit_all(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static struct value * arm_epilogue_frame_prev_register(frame_info_ptr this_frame, void **this_cache, int regnum)
static void arm_print_float_info(struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, const char *args)
int(* sti_arm_hdl_fp_t)(arm_insn_decode_record *)
static int arm_copy_alu_reg(struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
static const char * disassembly_style
static int thumb_record_misc(arm_insn_decode_record *thumb_insn_r)
int arm_get_next_pcs_is_thumb(struct arm_get_next_pcs *self)
static struct type * arm_ext_type(struct gdbarch *gdbarch)
const target_desc * arm_read_description(arm_fp_type fp_type, bool tls)
static void arm_mve_pseudo_write(struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf)
static const struct frame_unwind arm_epilogue_frame_unwind
static void arm_cache_set_active_sp_value(struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, CORE_ADDR val)
#define ARM_LE_BREAKPOINT
#define ARM_DISPLACED_MODIFIED_INSNS
target_desc * arm_create_target_description(arm_fp_type fp_type, bool tls)
target_desc * arm_create_mprofile_target_description(arm_m_profile_type m_type)
int arm_instruction_changes_pc(uint32_t this_instr)
int thumb2_instruction_changes_pc(unsigned short inst1, unsigned short inst2)
int condition_true(unsigned long cond, unsigned long status_reg)
int thumb_insn_size(unsigned short inst1)
int thumb_instruction_changes_pc(unsigned short inst)
#define UNMAKE_THUMB_ADDR(addr)
#define ARM_INT_REGISTER_SIZE
#define IS_AUT(instruction)
#define ARM_VFP2_REGS_SIZE
#define IS_PAC(instruction)
#define IS_PACG(instruction)
#define IS_THUMB_ADDR(addr)
#define ARM_CORE_REGS_SIZE
#define BranchDest(addr, instr)
#define ARM_FP_REGISTER_SIZE
#define IS_AUTG(instruction)
#define IS_PACBTI(instruction)
#define MAKE_THUMB_ADDR(addr)
bool find_pc_partial_function(CORE_ADDR pc, const char **name, CORE_ADDR *address, CORE_ADDR *endaddr, const struct block **block)
bool find_reg(struct gdbarch *gdbarch, int reg, CORE_ADDR *offset_p)
bool store_would_trash(pv_t addr)
void store(pv_t addr, CORE_ADDR size, pv_t value)
enum register_status raw_read(int regnum, gdb_byte *buf)
enum register_status raw_read_part(int regnum, int offset, int len, gdb_byte *buf)
enum register_status cooked_read(int regnum, gdb_byte *buf)
void cooked_write(int regnum, const gdb_byte *buf)
void raw_write_part(int regnum, int offset, int len, const gdb_byte *buf)
void raw_write(int regnum, const gdb_byte *buf)
struct cmd_list_element * showlist
struct cmd_list_element * setlist
struct cmd_list_element * showdebuglist
struct cmd_list_element * setdebuglist
set_show_commands add_setshow_enum_cmd(const char *name, enum command_class theclass, const char *const *enumlist, const char **var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
set_show_commands add_setshow_prefix_cmd(const char *name, command_class theclass, const char *set_doc, const char *show_doc, cmd_list_element **set_subcommands_list, cmd_list_element **show_subcommands_list, cmd_list_element **set_list, cmd_list_element **show_list)
set_show_commands add_setshow_boolean_cmd(const char *name, enum command_class theclass, bool *var, const char *set_doc, const char *show_doc, const char *help_doc, cmd_func_ftype *set_func, show_value_ftype *show_func, struct cmd_list_element **set_list, struct cmd_list_element **show_list)
void write_memory(CORE_ADDR memaddr, const bfd_byte *myaddr, ssize_t len)
ULONGEST read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
void write_memory_unsigned_integer(CORE_ADDR addr, int len, enum bfd_endian byte_order, ULONGEST value)
int safe_read_memory_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order, ULONGEST *return_value)
ULONGEST read_code_unsigned_integer(CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
static void store_signed_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, LONGEST val)
static void store_unsigned_integer(gdb_byte *addr, int len, enum bfd_endian byte_order, ULONGEST val)
static ULONGEST extract_unsigned_integer(gdb::array_view< const gdb_byte > buf, enum bfd_endian byte_order)
@ RETURN_VALUE_ABI_RETURNS_ADDRESS
@ RETURN_VALUE_REGISTER_CONVENTION
@ RETURN_VALUE_STRUCT_CONVENTION
char * get_disassembler_options(struct gdbarch *gdbarch)
void set_disassembler_options(const char *prospective_options)
#define displaced_debug_printf(fmt,...)
void * dwarf2_frame_allocate_fn_data(frame_info_ptr this_frame, void **this_cache, fn_prev_register cookie, unsigned long size)
void * dwarf2_frame_get_fn_data(frame_info_ptr this_frame, void **this_cache, fn_prev_register cookie)
void dwarf2_append_unwinders(struct gdbarch *gdbarch)
void dwarf2_frame_set_init_reg(struct gdbarch *gdbarch, void(*init_reg)(struct gdbarch *, int, struct dwarf2_frame_state_reg *, frame_info_ptr))
@ DWARF2_FRAME_REG_SAVED_VAL_EXP
ssize_t read(int fd, void *buf, size_t count)
struct value * value_of_register(int regnum, frame_info_ptr frame)
void frame_base_set_default(struct gdbarch *gdbarch, const struct frame_base *default_base)
int default_frame_sniffer(const struct frame_unwind *self, frame_info_ptr this_frame, void **this_prologue_cache)
enum unwind_stop_reason default_frame_unwind_stop_reason(frame_info_ptr this_frame, void **this_cache)
struct value * frame_unwind_got_constant(frame_info_ptr frame, int regnum, ULONGEST val)
void frame_unwind_append_unwinder(struct gdbarch *gdbarch, const struct frame_unwind *unwinder)
frame_info_ptr get_next_frame(frame_info_ptr this_frame)
int frame_relative_level(frame_info_ptr fi)
ULONGEST get_frame_register_unsigned(frame_info_ptr frame, int regnum)
ULONGEST frame_unwind_register_unsigned(frame_info_ptr next_frame, int regnum)
CORE_ADDR get_frame_pc(frame_info_ptr frame)
struct frame_id frame_id_build(CORE_ADDR stack_addr, CORE_ADDR code_addr)
struct gdbarch * get_frame_arch(frame_info_ptr this_frame)
enum frame_type get_frame_type(frame_info_ptr frame)
bool get_frame_pc_masked(frame_info_ptr frame)
ULONGEST get_frame_memory_unsigned(frame_info_ptr this_frame, CORE_ADDR addr, int len)
CORE_ADDR get_frame_func(frame_info_ptr this_frame)
void set_frame_previous_pc_masked(frame_info_ptr frame)
frame_info_ptr get_current_frame(void)
CORE_ADDR get_frame_address_in_block(frame_info_ptr this_frame)
frame_info_ptr get_prev_frame(frame_info_ptr this_frame)
CORE_ADDR get_frame_base(frame_info_ptr fi)
#define FRAME_OBSTACK_ZALLOC(TYPE)
static gdb_bfd_section_range gdb_bfd_sections(bfd *abfd)
void set_gdbarch_char_signed(struct gdbarch *gdbarch, int char_signed)
void set_gdbarch_return_value_as_value(struct gdbarch *gdbarch, gdbarch_return_value_as_value_ftype *return_value_as_value)
void set_gdbarch_disassembler_options(struct gdbarch *gdbarch, char **disassembler_options)
enum bfd_endian gdbarch_byte_order(struct gdbarch *gdbarch)
void set_gdbarch_breakpoint_kind_from_pc(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_pc_ftype *breakpoint_kind_from_pc)
void set_gdbarch_register_sim_regno(struct gdbarch *gdbarch, gdbarch_register_sim_regno_ftype *register_sim_regno)
const char * gdbarch_register_name(struct gdbarch *gdbarch, int regnr)
void set_gdbarch_valid_disassembler_options(struct gdbarch *gdbarch, const disasm_options_and_args_t *valid_disassembler_options)
void set_gdbarch_frame_align(struct gdbarch *gdbarch, gdbarch_frame_align_ftype *frame_align)
void set_gdbarch_max_insn_length(struct gdbarch *gdbarch, ULONGEST max_insn_length)
void set_gdbarch_code_of_frame_writable(struct gdbarch *gdbarch, gdbarch_code_of_frame_writable_ftype *code_of_frame_writable)
void set_gdbarch_write_pc(struct gdbarch *gdbarch, gdbarch_write_pc_ftype *write_pc)
void set_gdbarch_get_longjmp_target(struct gdbarch *gdbarch, gdbarch_get_longjmp_target_ftype *get_longjmp_target)
void set_gdbarch_skip_prologue(struct gdbarch *gdbarch, gdbarch_skip_prologue_ftype *skip_prologue)
void set_gdbarch_addr_bits_remove(struct gdbarch *gdbarch, gdbarch_addr_bits_remove_ftype *addr_bits_remove)
void set_gdbarch_elf_make_msymbol_special(struct gdbarch *gdbarch, gdbarch_elf_make_msymbol_special_ftype *elf_make_msymbol_special)
void set_gdbarch_displaced_step_buffer_length(struct gdbarch *gdbarch, ULONGEST displaced_step_buffer_length)
int gdbarch_addr_bit(struct gdbarch *gdbarch)
void set_gdbarch_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name)
void set_gdbarch_get_pc_address_flags(struct gdbarch *gdbarch, gdbarch_get_pc_address_flags_ftype *get_pc_address_flags)
void set_gdbarch_skip_trampoline_code(struct gdbarch *gdbarch, gdbarch_skip_trampoline_code_ftype *skip_trampoline_code)
void set_gdbarch_wchar_signed(struct gdbarch *gdbarch, int wchar_signed)
void set_gdbarch_have_nonsteppable_watchpoint(struct gdbarch *gdbarch, int have_nonsteppable_watchpoint)
void set_gdbarch_gnu_triplet_regexp(struct gdbarch *gdbarch, gdbarch_gnu_triplet_regexp_ftype *gnu_triplet_regexp)
bool gdbarch_displaced_step_copy_insn_closure_by_addr_p(struct gdbarch *gdbarch)
int gdbarch_num_regs(struct gdbarch *gdbarch)
void set_gdbarch_breakpoint_kind_from_current_state(struct gdbarch *gdbarch, gdbarch_breakpoint_kind_from_current_state_ftype *breakpoint_kind_from_current_state)
void set_gdbarch_inner_than(struct gdbarch *gdbarch, gdbarch_inner_than_ftype *inner_than)
enum bfd_endian gdbarch_byte_order_for_code(struct gdbarch *gdbarch)
void set_gdbarch_sp_regnum(struct gdbarch *gdbarch, int sp_regnum)
void set_gdbarch_register_reggroup_p(struct gdbarch *gdbarch, gdbarch_register_reggroup_p_ftype *register_reggroup_p)
void set_gdbarch_long_double_format(struct gdbarch *gdbarch, const struct floatformat **long_double_format)
void set_gdbarch_pc_regnum(struct gdbarch *gdbarch, int pc_regnum)
void set_gdbarch_adjust_breakpoint_address(struct gdbarch *gdbarch, gdbarch_adjust_breakpoint_address_ftype *adjust_breakpoint_address)
void set_gdbarch_register_type(struct gdbarch *gdbarch, gdbarch_register_type_ftype *register_type)
void set_gdbarch_print_insn(struct gdbarch *gdbarch, gdbarch_print_insn_ftype *print_insn)
const struct target_desc * gdbarch_target_desc(struct gdbarch *gdbarch)
void set_gdbarch_record_special_symbol(struct gdbarch *gdbarch, gdbarch_record_special_symbol_ftype *record_special_symbol)
void set_gdbarch_coff_make_msymbol_special(struct gdbarch *gdbarch, gdbarch_coff_make_msymbol_special_ftype *coff_make_msymbol_special)
void set_gdbarch_stack_frame_destroyed_p(struct gdbarch *gdbarch, gdbarch_stack_frame_destroyed_p_ftype *stack_frame_destroyed_p)
void set_gdbarch_pseudo_register_write(struct gdbarch *gdbarch, gdbarch_pseudo_register_write_ftype *pseudo_register_write)
void set_gdbarch_num_pseudo_regs(struct gdbarch *gdbarch, int num_pseudo_regs)
void set_gdbarch_dwarf2_reg_to_regnum(struct gdbarch *gdbarch, gdbarch_dwarf2_reg_to_regnum_ftype *dwarf2_reg_to_regnum)
CORE_ADDR gdbarch_addr_bits_remove(struct gdbarch *gdbarch, CORE_ADDR addr)
void set_gdbarch_type_align(struct gdbarch *gdbarch, gdbarch_type_align_ftype *type_align)
void set_gdbarch_pseudo_register_read(struct gdbarch *gdbarch, gdbarch_pseudo_register_read_ftype *pseudo_register_read)
void set_gdbarch_num_regs(struct gdbarch *gdbarch, int num_regs)
const struct bfd_arch_info * gdbarch_bfd_arch_info(struct gdbarch *gdbarch)
void set_gdbarch_sw_breakpoint_from_kind(struct gdbarch *gdbarch, gdbarch_sw_breakpoint_from_kind_ftype *sw_breakpoint_from_kind)
void set_gdbarch_print_float_info(struct gdbarch *gdbarch, gdbarch_print_float_info_ftype *print_float_info)
void set_gdbarch_double_format(struct gdbarch *gdbarch, const struct floatformat **double_format)
void set_gdbarch_float_format(struct gdbarch *gdbarch, const struct floatformat **float_format)
void set_gdbarch_push_dummy_call(struct gdbarch *gdbarch, gdbarch_push_dummy_call_ftype *push_dummy_call)
void set_gdbarch_vbit_in_delta(struct gdbarch *gdbarch, int vbit_in_delta)
const displaced_step_copy_insn_closure * gdbarch_displaced_step_copy_insn_closure_by_addr(struct gdbarch *gdbarch, inferior *inf, CORE_ADDR addr)
struct gdbarch * gdbarch_alloc(const struct gdbarch_info *info, gdbarch_tdep_up tdep)
std::unique_ptr< gdbarch_tdep_base > gdbarch_tdep_up
function_call_return_method
struct type * arch_composite_type(struct gdbarch *gdbarch, const char *name, enum type_code code)
const struct floatformat * floatformats_ieee_double_littlebyte_bigword[BFD_ENDIAN_UNKNOWN]
struct type * init_vector_type(struct type *elt_type, int n)
const struct floatformat * floatformats_ieee_single[BFD_ENDIAN_UNKNOWN]
struct type * init_float_type(type_allocator &alloc, int bit, const char *name, const struct floatformat **floatformats, enum bfd_endian byte_order)
const struct builtin_type * builtin_type(struct gdbarch *gdbarch)
const struct floatformat * floatformats_arm_ext[BFD_ENDIAN_UNKNOWN]
unsigned type_align(struct type *type)
const struct floatformat * floatformats_ieee_double[BFD_ENDIAN_UNKNOWN]
void append_composite_type_field(struct type *t, const char *name, struct type *field)
bool is_fixed_point_type(struct type *type)
struct type * check_typedef(struct type *type)
#define TYPE_IS_REFERENCE(t)
#define TYPE_HAS_DYNAMIC_LENGTH(t)
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t err
mach_port_t kern_return_t mach_port_t mach_msg_type_name_t msgportsPoly mach_port_t kern_return_t pid_t pid mach_port_t kern_return_t mach_port_t task mach_port_t kern_return_t int flags
mach_port_t mach_port_t name mach_port_t mach_port_t name kern_return_t int status
struct inferior * current_inferior(void)
struct language_pass_by_ref_info language_pass_by_reference(struct type *type)
struct bound_minimal_symbol lookup_minimal_symbol(const char *name, const char *sfile, struct objfile *objf)
struct bound_minimal_symbol lookup_minimal_symbol_by_pc(CORE_ADDR pc)
struct minimal_symbol * lookup_minimal_symbol_by_pc_name(CORE_ADDR pc, const char *name, struct objfile *objf)
observable< struct objfile * > new_objfile
struct obj_section * find_pc_section(CORE_ADDR pc)
static int in_plt_section(CORE_ADDR pc)
void gdbarch_init_osabi(struct gdbarch_info info, struct gdbarch *gdbarch)
void generic_elf_osabi_sniff_abi_tag_sections(bfd *abfd, asection *sect, enum gdb_osabi *osabi)
void gdbarch_register_osabi_sniffer(enum bfd_architecture arch, enum bfd_flavour flavour, enum gdb_osabi(*sniffer_fn)(bfd *))
bool producer_is_llvm(const char *producer)
struct program_space * current_program_space
pv_t pv_constant(CORE_ADDR k)
pv_t pv_register(int reg, CORE_ADDR k)
pv_t pv_add(pv_t a, pv_t b)
pv_t pv_add_constant(pv_t v, CORE_ADDR k)
int pv_is_register(pv_t a, int r)
int pv_is_constant(pv_t a)
int record_full_arch_list_add_reg(struct regcache *regcache, int regnum)
int record_full_arch_list_add_mem(CORE_ADDR addr, int len)
int record_full_arch_list_add_end(void)
unsigned int record_debug
CORE_ADDR regcache_read_pc(struct regcache *regcache)
enum register_status regcache_raw_read_signed(struct regcache *regcache, int regnum, LONGEST *val)
enum register_status regcache_raw_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
enum register_status regcache_cooked_read_unsigned(struct regcache *regcache, int regnum, ULONGEST *val)
void regcache_write_pc(struct regcache *regcache, CORE_ADDR pc)
void regcache_cooked_write_unsigned(struct regcache *regcache, int regnum, ULONGEST val)
int default_register_reggroup_p(struct gdbarch *gdbarch, int regnum, const struct reggroup *group)
const reggroup *const float_reggroup
const reggroup *const save_reggroup
const reggroup *const all_reggroup
const reggroup *const restore_reggroup
void(* func)(remote_target *remote, char *)
void register_remote_g_packet_guess(struct gdbarch *gdbarch, int bytes, const struct target_desc *tdesc)
void(* cleanup)(struct gdbarch *, struct regcache *, arm_displaced_step_copy_insn_closure *)
struct arm_displaced_step_copy_insn_closure::@9::@12 block
struct arm_displaced_step_copy_insn_closure::@9::@13 preload
int(* copy_svc_os)(struct gdbarch *gdbarch, struct regcache *regs, arm_displaced_step_copy_insn_closure *dsc)
struct arm_displaced_step_copy_insn_closure::@9::@14 svc
struct arm_displaced_step_copy_insn_closure::@9::@11 branch
ULONGEST tmp[DISPLACED_TEMPS]
unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS]
union arm_displaced_step_copy_insn_closure::@9 u
struct arm_displaced_step_copy_insn_closure::@9::@10 ldst
std::vector< std::vector< arm_exidx_entry > > section_maps
bool operator<(const arm_exidx_entry &other) const
const gdb_byte * thumb_breakpoint
const gdb_byte * arm_breakpoint
int m_profile_psp_s_regnum
struct type * arm_ext_type
int m_profile_psp_ns_regnum
const gdb_byte * thumb2_breakpoint
int thumb2_breakpoint_size
int m_profile_msp_ns_regnum
int thumb_breakpoint_size
struct type * neon_double_type
struct type * neon_quad_type
int m_profile_msp_s_regnum
int(* arm_syscall_record)(struct regcache *regcache, unsigned long svc_number)
struct regcache * regcache
struct regcache * regcache
struct arm_mem_r * arm_mems
bool operator<(const arm_mapping_symbol &other) const
DISABLE_COPY_AND_ASSIGN(arm_per_bfd)
std::unique_ptr< bool[]> section_maps_sorted
arm_per_bfd(size_t num_sections)
std::unique_ptr< arm_mapping_symbol_vec[]> section_maps
trad_frame_saved_reg * saved_regs
gdb::optional< bool > ra_signed_state
arm_prologue_cache()=default
struct arm_stack_item * prev
CORE_ADDR value_address() const
struct minimal_symbol * minsym
struct type * builtin_int0
struct type * builtin_uint16
struct type * builtin_double
struct type * builtin_func_ptr
struct type * builtin_data_ptr
struct type * builtin_uint32
struct type * builtin_uint64
struct type * builtin_uint8
struct type * builtin_int16
struct type * builtin_void
struct type * builtin_float
const char * producer() const
union dwarf2_frame_state_reg::@46 loc
struct dwarf2_frame_state_reg::@46::@47 exp
enum dwarf2_frame_reg_rule how
LONGEST loc_bitpos() const
unsigned int bitsize() const
struct type * type() const
struct gdbarch_list * next
const char * linkage_name() const
CORE_ADDR value_address(objfile *objfile) const
struct bfd_section * the_bfd_section
iterator_range< section_iterator > sections()
objfile(gdb_bfd_ref_ptr, const char *, objfile_flags)
auto_obstack objfile_obstack
void set_addr(LONGEST addr)
struct type * target_type() const
struct field & field(int idx) const
unsigned int num_fields() const
void set_name(const char *name)
void set_is_vector(bool is_vector)
static struct value * allocate(struct type *type)
struct type * type() const
struct compunit_symtab * find_pc_compunit_symtab(CORE_ADDR pc)
CORE_ADDR skip_prologue_using_sal(struct gdbarch *gdbarch, CORE_ADDR func_addr)
tdesc_arch_data_up tdesc_data_alloc(void)
const struct tdesc_feature * tdesc_find_feature(const struct target_desc *target_desc, const char *name)
int tdesc_numbered_register(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *name)
static const registry< gdbarch >::key< tdesc_arch_data > tdesc_data
void tdesc_use_registers(struct gdbarch *gdbarch, const struct target_desc *target_desc, tdesc_arch_data_up &&early_data, tdesc_unknown_register_ftype unk_reg_cb)
void set_tdesc_pseudo_register_name(struct gdbarch *gdbarch, gdbarch_register_name_ftype *pseudo_name)
int tdesc_has_registers(const struct target_desc *target_desc)
struct type * tdesc_register_type(struct gdbarch *gdbarch, int regno)
int tdesc_numbered_register_choices(const struct tdesc_feature *feature, struct tdesc_arch_data *data, int regno, const char *const names[])
int tdesc_unnumbered_register(const struct tdesc_feature *feature, const char *name)
std::unique_ptr< tdesc_arch_data, tdesc_arch_data_deleter > tdesc_arch_data_up
void target_float_convert(const gdb_byte *from, const struct type *from_type, gdb_byte *to, const struct type *to_type)
int target_read_code(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
int target_has_registers()
int target_read_memory(CORE_ADDR memaddr, gdb_byte *myaddr, ssize_t len)
trad_frame_saved_reg * trad_frame_alloc_saved_regs(struct gdbarch *gdbarch)
struct value * trad_frame_get_prev_register(frame_info_ptr this_frame, trad_frame_saved_reg this_saved_regs[], int regnum)
void user_reg_add(struct gdbarch *gdbarch, const char *name, user_reg_read_ftype *xread, const void *baton)
int user_reg_map_name_to_regnum(struct gdbarch *gdbarch, const char *name, int len)
const char * paddress(struct gdbarch *gdbarch, CORE_ADDR addr)
void gdb_printf(struct ui_file *stream, const char *format,...)
void gdb_puts(const char *linebuffer, struct ui_file *stream)
struct value * value_at_non_lval(struct type *type, CORE_ADDR addr)
CORE_ADDR value_as_address(struct value *val)
LONGEST value_as_long(struct value *val)
LONGEST unpack_long(struct type *type, const gdb_byte *valaddr)